// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause

// Carry arithmetic, logical shifts, register aliases with element selectors
// and the ADC/SBC immediate spellings: the shapes nat_arm64.s, p256 and
// gcm_arm64.s exercise.  Byte-for-byte against go tool asm.

#include "textflag.h"

#define acc0 V8
#define acc1 V9
#define const0 R15
#define POLY V15

// carry pins the ADC/SBC family: the $0 spellings in two and three
// operands, and the register-carry forms.
TEXT ·carry(SB), NOSPLIT, $0-0
	ADC   $0, R20
	ADC   $0, R20, R4
	SBCS  $0, R4
	SBCS  $0, R4, R12
	SBCS  R15, R4, R12
	SBC   $0, R1
	ADCSW $0, R2, R3
	RET

// shift pins the shifted-register forms including ROR, which only the
// logical family accepts.
TEXT ·shift(SB), NOSPLIT, $0-0
	ANDW R9@>7, R19, R26
	AND  R1@>33, R2, R3
	ADD  R1<<11, R2, R3
	SUB  R1->33, R2
	ORR  R5<<2, R6, R7
	RET

// vecalias pins the vector aliases with element selectors and the
// structure loads with aliased members.
TEXT ·vecalias(SB), NOSPLIT, $0-0
	MOVD   $0xC2, R1
	VMOV   R1, POLY.D[0]
	VMOV   R0, POLY.D[1]
	VEOR   POLY.B16, POLY.B16, POLY.B16
	VLD1   (R0), [acc0.B16]
	VLD1.P (R0), [acc0.B16, acc1.B16]
	VST1   [acc0.B16, acc1.B16], (R1)
	VST1.P [acc0.B16, acc1.B16], 32(R1)
	RET