// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause

package arch

import (
	"encoding/hex"
	"strings"
	"testing"
)

// The BF16 and VP2INTERSECT encodings have no toolchain oracle: go tool asm
// knows neither family.  The golden words below are transcribed from the
// Intel SDM instruction entries and cross-checked against binutils-gdb's own
// assembler testsuite: every row marked "GNU" matches a vector in
// gas/testsuite/gas/i386/avx512_bf16.d, avx512_bf16_vl.d or
// x86-64-vp2intersect.d byte for byte, so no entry rests on transcription
// alone.  The GNU dumps print AT&T order (sources first, destination last),
// which is the order the operands are built in here too.
func amd64ExtInstr(t *testing.T, mnem string, class ExtOperandKind) ExtInstr {
	t.Helper()
	for _, in := range Extensions(AMD64) {
		if in.Name == mnem && amd64LengthClass(in.Bytes) == class {
			return in
		}
	}
	t.Fatalf("no extended %s encoding at the %s vector length", mnem, class)
	return ExtInstr{}
}

func TestAmd64ExtGoldenBytes(t *testing.T) {
	for _, tt := range []struct {
		name string
		mnem string
		ops  []ExtOperand
		want string // hex, little-endian bytes in memory order
		GNU  string // the matching binutils-gdb line, empty for a derived register form
	}{
		// AVX512-BF16, EVEX.NDS.F2.0F38.W0.
		{"vcvtne2ps2bf16 zmm", "VCVTNE2PS2BF16",
			[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtZmm(6)},
			"62f2574872f4", "62 f2 57 48 72 f4 vcvtne2ps2bf16 %zmm4,%zmm5,%zmm6"},
		{"vcvtne2ps2bf16 ymm", "VCVTNE2PS2BF16",
			[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
			"62f2572872f4", "62 f2 57 28 72 f4 vcvtne2ps2bf16 %ymm4,%ymm5,%ymm6"},
		{"vcvtne2ps2bf16 xmm", "VCVTNE2PS2BF16",
			[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
			"62f2570872f4", "62 f2 57 08 72 f4 vcvtne2ps2bf16 %xmm4,%xmm5,%xmm6"},
		{"vcvtneps2bf16 zmm to ymm", "VCVTNEPS2BF16",
			[]ExtOperand{ExtZmm(5), ExtYmm(6)},
			"62f27e4872f5", "62 f2 7e 48 72 f5 vcvtneps2bf16 %zmm5,%ymm6"},
		{"vcvtneps2bf16 ymm to xmm", "VCVTNEPS2BF16",
			[]ExtOperand{ExtYmm(5), ExtXmm(6)},
			"62f27e2872f5", "62 f2 7e 28 72 f5 vcvtneps2bf16 %ymm5,%xmm6"},
		{"vcvtneps2bf16 xmm to xmm", "VCVTNEPS2BF16",
			[]ExtOperand{ExtXmm(5), ExtXmm(6)},
			"62f27e0872f5", "62 f2 7e 08 72 f5 vcvtneps2bf16 %xmm5,%xmm6"},
		{"vdpbf16ps zmm", "VDPBF16PS",
			[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtZmm(6)},
			"62f2564852f4", "62 f2 56 48 52 f4 vdpbf16ps %zmm4,%zmm5,%zmm6"},
		{"vdpbf16ps ymm", "VDPBF16PS",
			[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
			"62f2562852f4", "62 f2 56 28 52 f4 vdpbf16ps %ymm4,%ymm5,%ymm6"},
		{"vdpbf16ps xmm", "VDPBF16PS",
			[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
			"62f2560852f4", "62 f2 56 08 52 f4 vdpbf16ps %xmm4,%xmm5,%xmm6"},

		// AVX512-VP2INTERSECT, EVEX.NDS.F2.0F38.  The mask destination is
		// the ModR/M reg field, so a k register above k7 must refuse.
		{"vp2intersectd zmm k0", "VP2INTERSECTD",
			[]ExtOperand{ExtZmm(2), ExtZmm(1), ExtMask(0)},
			"62f26f4868c1", "62 f2 6f 48 68 c1 vp2intersectd %zmm1,%zmm2,%k0"},
		{"vp2intersectd ymm k2", "VP2INTERSECTD",
			[]ExtOperand{ExtYmm(2), ExtYmm(1), ExtMask(2)},
			"62f26f2868d1", "62 f2 6f 28 68 d1 vp2intersectd %ymm1,%ymm2,%k2"},
		{"vp2intersectd xmm k4", "VP2INTERSECTD",
			[]ExtOperand{ExtXmm(2), ExtXmm(1), ExtMask(4)},
			"62f26f0868e1", "62 f2 6f 08 68 e1 vp2intersectd %xmm1,%xmm2,%k4"},
		{"vp2intersectq zmm k0", "VP2INTERSECTQ",
			[]ExtOperand{ExtZmm(2), ExtZmm(1), ExtMask(0)},
			"62f2ef4868c1", "62 f2 ef 48 68 c1 vp2intersectq %zmm1,%zmm2,%k0"},
		{"vp2intersectq ymm k2", "VP2INTERSECTQ",
			[]ExtOperand{ExtYmm(2), ExtYmm(1), ExtMask(2)},
			"62f2ef2868d1", "62 f2 ef 28 68 d1 vp2intersectq %ymm1,%ymm2,%k2"},
		{"vp2intersectq xmm k4", "VP2INTERSECTQ",
			[]ExtOperand{ExtXmm(2), ExtXmm(1), ExtMask(4)},
			"62f2ef0868e1", "62 f2 ef 08 68 e1 vp2intersectq %xmm1,%xmm2,%k4"},

		// High registers exercise the EVEX extension bits: with both source
		// registers above 15 the B bar and X bar bits clear, while the
		// destination zmm23 keeps R bar set in byte one (derived from the
		// proven class above).
		{"vcvtne2ps2bf16 high registers", "VCVTNE2PS2BF16",
			[]ExtOperand{ExtZmm(21), ExtZmm(20), ExtZmm(23)},
			"62a2574072fc", ""},
	} {
		in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
		got, err := in.Encode(tt.ops)
		if err != nil {
			t.Errorf("%s: encode: %v", tt.name, err)
			continue
		}
		if hex.EncodeToString(got) != tt.want {
			t.Errorf("%s:\n  got  %x\n  want %s", tt.name, got, tt.want)
		}
	}
}

// operandClass names the vector class a golden row exercises, the key the
// helper resolves the table entry with.  A row without a vector operand
// (none today) would have nowhere to go.
func operandClass(t *testing.T, ops []ExtOperand) ExtOperandKind {
	t.Helper()
	for _, op := range ops {
		switch op.Kind {
		case ExtXMM, ExtYMM, ExtZMM:
			return op.Kind
		}
	}
	t.Fatal("the golden row carries no vector operand to pick the entry with")
	return ExtXMM
}

// TestAmd64ExtTemplateIntegrity checks the metadata contract: every entry
// names its manual reference, summary and feature, and every template carries
// the fixed shape of an EVEX register form with the register-derived bits
// zero, so a slip in the table is an error and not a stray byte.
func TestAmd64ExtTemplateIntegrity(t *testing.T) {
	features := map[ExtFeature]bool{
		ExtFeatureBF16:         true,
		ExtFeatureVP2INTERSECT: true,
	}
	for _, in := range Extensions(AMD64) {
		if in.Name == "" || in.Summary == "" || in.Ref == "" {
			t.Errorf("%+v: name, summary and reference are mandatory", in)
		}
		if !features[in.Feature] {
			t.Errorf("%s: feature %q is not an amd64 extension feature", in.Name, in.Feature)
		}
		if len(in.Bytes) != 6 {
			t.Errorf("%s: the template is %d bytes, want the 6-byte EVEX register form", in.Name, len(in.Bytes))
			continue
		}
		if in.Bytes[0] != 0x62 {
			t.Errorf("%s: the template opens with %02x, want the EVEX escape 62", in.Name, in.Bytes[0])
		}
		if in.Bytes[1]&0xf0 != 0 {
			t.Errorf("%s: byte one carries register bits %04b, want them zero", in.Name, in.Bytes[1]>>4)
		}
		if in.Bytes[2]&0x78 != 0 {
			t.Errorf("%s: byte two carries vvvv bits %04b, want them zero", in.Name, in.Bytes[2]>>3&0xf)
		}
		if in.Bytes[2]&0x04 == 0 {
			t.Errorf("%s: byte two lacks the reserved one-bit", in.Name)
		}
		if in.Bytes[3]&0x9f != 0 {
			t.Errorf("%s: byte three carries z, b, V prime or aaa bits, want them zero: %08b", in.Name, in.Bytes[3])
		}
		if in.Bytes[5]&0x3f != 0 || in.Bytes[5]&0xc0 != 0xc0 {
			t.Errorf("%s: byte five is %08b, want mod 11 with the reg and rm fields zero", in.Name, in.Bytes[5])
		}
		if in.Form.Arity() < 2 || in.Form.Arity() > 3 {
			t.Errorf("%s: form %s carries an unusable arity %d", in.Name, in.Form, in.Form.Arity())
		}
	}
}

// TestAmd64ExtEveryEntryCarriesGoldenVector pins the measure the layer is
// judged by: every registered entry is covered by at least one golden vector
// in the byte test above, so an entry without provenance cannot hide.
func TestAmd64ExtEveryEntryCarriesGoldenVector(t *testing.T) {
	covered := map[string]bool{}
	for _, in := range Extensions(AMD64) {
		covered[in.Name+"|"+string(amd64LengthClass(in.Bytes))] = false
	}
	for _, tt := range []struct {
		mnem  string
		class ExtOperandKind
	}{
		{"VCVTNE2PS2BF16", ExtZMM}, {"VCVTNE2PS2BF16", ExtYMM}, {"VCVTNE2PS2BF16", ExtXMM},
		{"VCVTNEPS2BF16", ExtZMM}, {"VCVTNEPS2BF16", ExtYMM}, {"VCVTNEPS2BF16", ExtXMM},
		{"VDPBF16PS", ExtZMM}, {"VDPBF16PS", ExtYMM}, {"VDPBF16PS", ExtXMM},
		{"VP2INTERSECTD", ExtZMM}, {"VP2INTERSECTD", ExtYMM}, {"VP2INTERSECTD", ExtXMM},
		{"VP2INTERSECTQ", ExtZMM}, {"VP2INTERSECTQ", ExtYMM}, {"VP2INTERSECTQ", ExtXMM},
	} {
		key := tt.mnem + "|" + string(tt.class)
		if _, ok := covered[key]; !ok {
			t.Errorf("the golden list covers %s, but the table registers no such entry", key)
			continue
		}
		covered[key] = true
	}
	for key, ok := range covered {
		if !ok {
			t.Errorf("%s has no golden vector", key)
		}
	}
}

func TestAmd64ExtRejects(t *testing.T) {
	for _, tt := range []struct {
		name  string
		mnem  string
		ops   []ExtOperand
		quote string // a fragment the error carries
	}{
		{"wrong vector class", "VCVTNE2PS2BF16",
			[]ExtOperand{ExtZmm(1), ExtZmm(2), ExtYmm(3)},
			"wants a ZMM register"},
		{"destination class is the source's on the narrow convert", "VCVTNEPS2BF16",
			[]ExtOperand{ExtZmm(1), ExtZmm(2)},
			"wants a YMM register"},
		{"vector in the mask position", "VP2INTERSECTD",
			[]ExtOperand{ExtZmm(1), ExtZmm(2), ExtZmm(3)},
			"wants an opmask register"},
		{"mask register beyond k7", "VP2INTERSECTD",
			[]ExtOperand{ExtZmm(1), ExtZmm(2), ExtMask(8)},
			"outside 0-7"},
		{"vector where the general register belongs", "VCVTNE2PS2BF16",
			[]ExtOperand{ExtGpr32(0), ExtZmm(2), ExtZmm(3)},
			"wants a ZMM register"},
		{"wrong arity", "VP2INTERSECTD",
			[]ExtOperand{ExtZmm(1), ExtZmm(2)},
			"takes 3 operands"},
		{"arm64 arrangement suffix", "VCVTNE2PS2BF16",
			[]ExtOperand{{Kind: ExtZMM, Reg: 1, Arr: ExtArrS}, ExtZmm(2), ExtZmm(3)},
			"arrangement"},
		{"predicate qualifier", "VCVTNEPS2BF16",
			[]ExtOperand{{Kind: ExtZMM, Reg: 1, Qual: ExtQualZeroing}, ExtZmm(2)},
			"predicate qualifier"},
	} {
		in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
		_, err := in.Encode(tt.ops)
		if err == nil {
			t.Errorf("%s: encode succeeded, want an error", tt.name)
			continue
		}
		if !strings.Contains(err.Error(), tt.quote) {
			t.Errorf("%s: error %q lacks %q", tt.name, err, tt.quote)
		}
	}
}