// Copyright (c) 2026 Petr Balvín (https://petrbalvin.org) // SPDX-License-Identifier: BSD-3-Clause // Seed corpus for FuzzAssembleLOONG64: the LSX (V) and LASX (X) register // banks, the family GOROOT's loong64 assembler corpus exercises // (cmd/asm/internal/asm/testdata/loong64enc*.s). Every immediate window sits // on an encoder gate: the si5 compares, the biased shifts, the ui8 logic // immediates and the element moves. #include "textflag.h" TEXT ·vecArith(SB), NOSPLIT, $0 VADDV V1, V2, V3 VADDW V1, V2, V3 VADDD V1, V2, V3 VADDQ V1, V2, V3 VSUBV V1, V2, V3 VSSUBV V1, V2, V3 VSADDVU V1, V2, V3 VMULV V1, V2, V3 VMUHVU V1, V2, V3 VDIVB V1, V2, V3 VMODH V1, V2, V3 VANDV V1, V2, V3 VORV V1, V2, V3 VXORV V1, V2, V3 VNORV V1, V2, V3 VANDNV V1, V2, V3 VSEQB V1, V2, V3 VSLTW V1, V2, V3 VSLTBU V1, V2, V3 VSLLB V1, V2, V3 VSRAH V1, V2, V3 VROTRV V1, V2, V3 VILVLW V1, V2, V3 VILVHV V1, V2, V3 VBITCLRW V1, V2, V3 VBITSETB V1, V2, V3 VBITREVW V1, V2, V3 VADDWEVHB V1, V2, V3 VSUBWODVW V1, V2, V3 VMULWEVQV V1, V2, V3 VMADDWODQVU V1, V2, V3 VSHUFV V1, V2, V3 RET TEXT ·vecArithX(SB), NOSPLIT, $0 XVADDV X1, X2, X3 XVADDW X1, X2, X3 XVADDD X1, X2, X3 XVADDQ X1, X2, X3 XVSUBV X1, X2, X3 XVSSUBVU X1, X2, X3 XVMULV X1, X2, X3 XVMUHVU X1, X2, X3 XVDIVB X1, X2, X3 XVANDV X1, X2, X3 XVNORV X1, X2, X3 XVSEQB X1, X2, X3 XVSLTW X1, X2, X3 XVSLLB X1, X2, X3 XVSRAB X1, X2, X3 XVROTRW X1, X2, X3 XVILVLB X1, X2, X3 XVBITCLRV X1, X2, X3 XVADDWEVHB X1, X2, X3 XVMULWODWHU X1, X2, X3 XVMADDWEVQVUV X1, X2, X3 XVSHUFV X1, X2, X3 RET TEXT ·vecImm(SB), NOSPLIT, $0 VANDB $0, V2, V3 VANDB $255, V2, V3 VORB $128, V2, V3 VXORB $255, V2, V3 VNORB $1, V2, V3 VSEQB $-16, V2, V3 VSEQB $15, V2, V3 VSEQH $0, V2, V3 VSEQW $-1, V2, V3 VSEQV $15, V2, V3 VSEQV $-15, V2, V3 VSLTB $-16, V2, V3 VSLTBU $0, V2, V3 VSLTBU $31, V2, V3 VADDBU $0, V2, V3 VADDVU $31, V2, V3 VSUBBU $31, V2, V3 VSLLB $0, V2, V3 VSLLB $7, V2, V3 VSLLH $15, V2, V3 VSLLW $31, V2, V3 VSLLV $63, V2, V3 VSRLB $7, V2, V3 VSRAB $7, V2, V3 VSRAH $15, V2, V3 VSRAW $31, V2, V3 VSRAV $63, V2, V3 VROTRB $7, V2, V3 VROTRH $15, V2, V3 VROTRW $31, V2, V3 VROTRV $63, V2, V3 VBITCLRB $7, V2, V3 VBITSETH $15, V2, V3 VBITREVW $31, V2, V3 VBITREVV $63, V2, V3 XVANDB $0, X2, X3 XVANDB $255, X2, X3 XVSEQB $-16, X2, X3 XVSEQB $15, X2, X3 XVSEQV $15, X2, X3 XVADDVU $31, X2, X3 XVSLLB $0, X2, X3 XVSLLB $7, X2, X3 XVSLLV $63, X2, X3 XVSRAB $7, X2, X3 XVROTRV $63, X2, X3 XVBITCLRB $7, X2, X3 XVBITSETV $63, X2, X3 RET TEXT ·vecUnary(SB), NOSPLIT, $0 VPCNTB V1, V2 VPCNTH V1, V2 VPCNTW V1, V2 VPCNTV V1, V2 VNEGB V1, V2 VNEGW V1, V2 VNEGV V1, V2 VFCLASSF V1, V2 VFCLASSD V1, V2 VFSQRTF V1, V2 VFSQRTD V1, V2 VFRECIPD V1, V2 VFRSQRTF V1, V2 VFRINTF V1, V2 VFRINTRMD V1, V2 VFRINTRNEF V1, V2 VFRINTRZD V1, V2 VFRINTRPF V1, V2 XVPCNTB X1, X2 XVPCNTV X1, X2 XVNEGH X1, X2 XVFSQRTD X1, X2 XVFRECIPF X1, X2 XVFRINTRZD X1, X2 RET TEXT ·vecCond(SB), NOSPLIT, $0 VSETNEV V1, FCC0 VSETEQV V1, FCC1 VSETANYEQB V1, FCC2 VSETANYEQH V2, FCC3 VSETANYEQW V1, FCC4 VSETANYEQV V2, FCC5 VSETALLNEB V1, FCC6 VSETALLNEH V2, FCC7 VSETALLNEW V1, FCC0 VSETALLNEV V0, FCC1 XVSETNEV X1, FCC0 XVSETEQV X2, FCC1 XVSETANYEQV X1, FCC2 XVSETALLNEB X2, FCC3 RET TEXT ·vecShuffle4(SB), NOSPLIT, $0 VSHUFB V0, V1, V2, V3 XVSHUFB X0, X1, X2, X3 RET // The VMOVQ/XVMOVQ move family: the load, the indexed load, the store, the // replicated load, the whole-register move, the GPR broadcast, the element // extract, the element insert and the element broadcast. TEXT ·vecMove(SB), NOSPLIT, $0 VMOVQ 8(R4), V2 VMOVQ (R4)(R5), V2 VMOVQ V2, 8(R4) VMOVQ V2, (R4)(R5) VMOVQ 2(R4), V1.H8 VMOVQ -6(R4), V1.H8 VMOVQ -12(R4), V2.W4 VMOVQ V1, V2 VMOVQ R4, V1.B16 VMOVQ R4, V1.H8 VMOVQ R4, V1.W4 VMOVQ R4, V1.V2 VMOVQ V1.B[3], R5 VMOVQ V1.H[7], R5 VMOVQ V1.W[3], R5 VMOVQ V1.V[1], R5 VMOVQ R5, V1.B[3] VMOVQ R5, V1.H[7] VMOVQ R5, V1.W[3] VMOVQ R5, V1.V[1] VMOVQ V1.B[3], V9.B16 VMOVQ V2.H[2], V8.H8 VMOVQ V3.W[1], V7.W4 VMOVQ V4.V[0], V6.V2 XVMOVQ X1, X2 XVMOVQ X0, X31.B32 XVMOVQ X1, X30.H16 XVMOVQ X2, X29.W8 XVMOVQ X3, X28.V4 XVMOVQ X3, X27.Q2 XVMOVQ X0, X31.W[7] XVMOVQ X1, X29.W[0] XVMOVQ X3, X28.V[3] XVMOVQ X4, X27.V[0] XVMOVQ X31.W[7], X0 XVMOVQ X28.V[3], X8 RET