// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause

// This file carries the extended-instruction layer: instructions the Go
// toolchain does not know at all, described as data and validated against
// golden vectors from the Arm Architecture Reference Manual rather than
// against the toolchain.  It sits beside the generated tables, never inside
// them: arch/arm64_gen.go stays untouched, and Extensions returns the layer
// per architecture; the amd64 side of the layer lives in amd64_ext.go and
// attaches through the same door.
//
// The first entries are the arm64 SVE and SVE2 integer add/subtract/multiply
// family (twenty-three forms over four word shapes) and the SVE and SVE2.1
// predicate family (logical operations, breaks, permutations, tests, the
// first-fault register group and the while compares).  The encodings are
// transcribed from the manual and cross-checked against the Go toolchain's
// generated encoding table and corpus; the golden vectors in
// arm64_ext_test.go pin the bytes.

package arch

import "fmt"

// ExtOperandKind classifies one operand of an extended instruction.
type ExtOperandKind uint8

// Operand kinds.
const (
	ExtZReg ExtOperandKind = iota // scalable vector register Z0-Z31
	ExtPReg                       // predicate register P0-P15
	ExtImm                        // immediate
	// The amd64 layer's register kinds.
	ExtXMM  // 128-bit vector register XMM0-XMM31
	ExtYMM  // 256-bit vector register YMM0-YMM31
	ExtZMM  // 512-bit vector register ZMM0-ZMM31
	ExtKReg // opmask register K0-K7
	ExtR32  // 32-bit general register EAX-R15D
	ExtR64  // 64-bit general register RAX-R15
	ExtMem  // base-relative memory operand, 4660(R8) style
	// The arm64 layer's general and counter registers.
	ExtGReg  // general register R0-R30
	ExtPNReg // predicate-as-counter register PN8-PN15
	ExtVReg  // 128-bit SIMD register V0-V31, the scalar lanes of Z0-Z31
	// ExtSveMem is the arm64 gather/scatter memory operand, the parenthesised
	// register pair or immediate-offset base the SVE loads and stores address
	// through: (R6)(R14), (Z23.D<<1)(R24), (Z4.S.UXTW)(R3), 6(Z7.S).
	ExtSveMem
)

// String returns a short label for the kind.
func (k ExtOperandKind) String() string {
	switch k {
	case ExtZReg:
		return "scalable vector register"
	case ExtPReg:
		return "predicate register"
	case ExtImm:
		return "immediate"
	case ExtXMM:
		return "XMM register"
	case ExtYMM:
		return "YMM register"
	case ExtZMM:
		return "ZMM register"
	case ExtKReg:
		return "opmask register"
	case ExtR32:
		return "32-bit general register"
	case ExtR64:
		return "64-bit general register"
	case ExtMem:
		return "memory operand"
	case ExtGReg:
		return "general register"
	case ExtPNReg:
		return "predicate-as-counter register"
	case ExtVReg:
		return "SIMD register"
	case ExtSveMem:
		return "SVE memory operand"
	default:
		return "operand"
	}
}

// ExtArrangement is the element-size suffix a scalable vector operand
// carries: .B, .H, .S, .D or .Q.  ExtArrNone means the operand is written
// bare, which the SVE forms in this layer reject.
type ExtArrangement uint8

// Arrangements, widest last.
const (
	ExtArrNone ExtArrangement = iota
	ExtArrB                   // 8-bit elements
	ExtArrH                   // 16-bit elements
	ExtArrS                   // 32-bit elements
	ExtArrD                   // 64-bit elements
	ExtArrQ                   // 128-bit elements
)

// String returns the assembler suffix, with the leading dot.
func (a ExtArrangement) String() string {
	switch a {
	case ExtArrB:
		return ".B"
	case ExtArrH:
		return ".H"
	case ExtArrS:
		return ".S"
	case ExtArrD:
		return ".D"
	case ExtArrQ:
		return ".Q"
	default:
		return ""
	}
}

// Width returns the byte width of one element under the arrangement.
func (a ExtArrangement) Width() int {
	switch a {
	case ExtArrB:
		return 1
	case ExtArrH:
		return 2
	case ExtArrS:
		return 4
	case ExtArrD:
		return 8
	case ExtArrQ:
		return 16
	default:
		return 0
	}
}

// elemBits returns the arrangement's element size in bits, the scale the
// shift-immediate classes encode their amounts against.
func (a ExtArrangement) elemBits() int {
	return a.Width() * 8
}

// sizeBits maps the arrangement onto the two-bit size field the integer SVE
// classes carry at bits 23..22: 00=B, 01=H, 10=S, 11=D.  ok is false for the
// arrangements no such class accepts (.Q and the bare spelling).
func (a ExtArrangement) sizeBits() (uint32, bool) {
	switch a {
	case ExtArrB, ExtArrH, ExtArrS, ExtArrD:
		return uint32(a) - 1, true
	default:
		return 0, false
	}
}

// ExtQualifier is the predicate qualifier spelled after the slash.
type ExtQualifier uint8

// Predicate qualifiers.
const (
	ExtQualNone    ExtQualifier = iota // bare Pn (non-predicating position)
	ExtQualMerging                     // /M, inactive lanes keep the destination
	ExtQualZeroing                     // /Z, inactive lanes become zero
	ExtQualAny                         // metadata only: the row takes /M or /Z
)

// String returns the assembler spelling, with the leading slash.
func (q ExtQualifier) String() string {
	switch q {
	case ExtQualMerging:
		return "/M"
	case ExtQualZeroing:
		return "/Z"
	default:
		return ""
	}
}

// ExtOperand is one operand of an extended instruction, already resolved to
// its pieces: a register with its arrangement and qualifier, or an immediate
// with its optional left shift.  The assembler's future hook constructs these
// from the parsed statement; Encode consumes them.
type ExtOperand struct {
	Kind ExtOperandKind
	// Reg is the register number (Z: 0..31, P: 0..15, R: 0..30, PN: 8..15);
	// under ExtMem it is the base general register, 0..15.
	Reg  int
	Arr  ExtArrangement // element-size suffix; ExtArrNone when bare
	Qual ExtQualifier   // predicate qualifier; ExtQualNone elsewhere
	// Imm is the immediate value under ExtImm; under ExtMem it is the
	// signed displacement the base carries.
	Imm int64
	// Shift carries the LSL amount an immediate form shifts the constant by
	// before use (0 or 8 in the SVE add/subtract immediate class).  HasShift
	// separates a spelled shift (validated as written) from an unshifted
	// operand (the encoder may derive the sh bit from the value).
	Shift    int
	HasShift bool
	// Broadcast spells the {1toN} broadcast on an amd64 memory operand: the
	// base-relative location holds one element the hardware splats across
	// every lane of the destination, which the encoder lays down as EVEX.b.
	// Only the memory positions of the entries that carry Bcast accept it.
	Broadcast bool
	// Index and Scale spell the scaled index of an amd64 memory operand,
	// the SIB byte's shape: base plus index times scale.  Scale carries the
	// byte multiplier 1, 2, 4 or 8, and HasIndex separates a spelled index
	// from the plain base-plus-displacement operand.  The index is a
	// general register 0..15, and RSP is no index.
	Index    int
	Scale    int
	HasIndex bool
	// Mask spells the write mask of an amd64 EVEX destination, the {k1}
	// through {k7} decorations: only the masked lanes take the result.
	// HasMask separates a spelled mask from the unmasked destination, and
	// K0 never masks, so the register runs 1..7.  Only the packed
	// destinations of the entries that carry Mask accept it.
	Mask    int
	HasMask bool
	// Zeroing spells the {z} decoration beside a write mask: the inactive
	// lanes become zero instead of keeping the destination.  It is valid
	// only together with a spelled mask.
	Zeroing bool
	// Reg31 names how the thirty-first general-register slot was spelled on
	// an arm64 ExtGReg operand: the zero register ZR or the stack pointer
	// RSP.  Both encode as 31 in the five-bit register fields, and the forms
	// of this layer accept one spelling or the other, never a plain R31, so
	// the marker carries the distinction into the diagnostics.
	Reg31 uint8 // 0 = a register 0..30, 1 = ZR, 2 = RSP
	// The arm64 gather/scatter memory operand (Kind ExtSveMem) carries its
	// addressing in these fields beside Reg, Arr, Imm, Shift and Reg31: the
	// first parenthesised register in Reg (general or scalable vector, told
	// apart by BaseVec, its element size in Arr), the optional UXTW or SXTW
	// extension in Extend, the <<s scale in Shift, the second parenthesised
	// register in Off (-1 when the operand carries no second parenthesis)
	// and the byte displacement of the immediate-offset spellings in Imm.
	BaseVec bool  // the first parenthesis spells a Z register
	Extend  uint8 // 0 = none, 1 = UXTW, 2 = SXTW
	Off     int   // the second parenthesis's register, -1 when absent
	// Round spells the rounding decoration of an amd64 EVEX destination, the
	// {sae} and {rn-sae} through {rz-sae} spellings: EVEX.b selects the
	// rounding context and EVEX.RC, the L'L bits it replaces, the mode.  Only
	// the destinations of the entries that carry Er or Sae accept it.  The
	// arm64 entries all carry the zero value.
	Round ExtRounding
	// List carries the register count of a multi-vector list operand, the
	// [Z13.B, Z14.B, Z15.B] shape of the SVE LD2-LD4 and ST2-ST4
	// multiple-structure loads and stores: consecutive registers under one
	// arrangement, of which the encoding carries the first alone.  A list
	// of one register carries 0, and the amd64 operands never more.
	List int
}

// ExtVector builds a scalable vector operand, ADD Z1.S style.
func ExtVector(reg int, arr ExtArrangement) ExtOperand {
	return ExtOperand{Kind: ExtZReg, Reg: reg, Arr: arr}
}

// ExtPredicate builds a predicate operand with its qualifier, P0/M style.
func ExtPredicate(reg int, qual ExtQualifier) ExtOperand {
	return ExtOperand{Kind: ExtPReg, Reg: reg, Qual: qual}
}

// ExtPredicateSized builds a predicate operand carrying an element-size
// suffix, P4.B style.
func ExtPredicateSized(reg int, arr ExtArrangement) ExtOperand {
	return ExtOperand{Kind: ExtPReg, Reg: reg, Arr: arr}
}

// ExtCounterPredicate builds a predicate-as-counter operand, PN14.S style.
// The counter spellings run PN8-PN15, the convention the toolchain's
// generated table and corpus use for the three-bit counter field.
func ExtCounterPredicate(reg int, arr ExtArrangement) ExtOperand {
	return ExtOperand{Kind: ExtPNReg, Reg: reg, Arr: arr}
}

// ExtGeneral builds a general register operand, R2 style.
func ExtGeneral(reg int) ExtOperand {
	return ExtOperand{Kind: ExtGReg, Reg: reg}
}

// ExtZeroRegister builds the zero-register operand, ZR: the thirty-first
// general-register slot in its zero spelling.
func ExtZeroRegister() ExtOperand {
	return ExtOperand{Kind: ExtGReg, Reg: 31, Reg31: 1}
}

// ExtStackPointer builds the stack-pointer operand, RSP: the thirty-first
// general-register slot in its stack-pointer spelling.
func ExtStackPointer() ExtOperand {
	return ExtOperand{Kind: ExtGReg, Reg: 31, Reg31: 2}
}

// ExtSIMD builds a 128-bit SIMD register operand, V2 style: the low lanes of
// the scalable vector register of the same number, the scalar destination the
// SVE reductions and inserts write.
func ExtSIMD(reg int) ExtOperand {
	return ExtOperand{Kind: ExtVReg, Reg: reg}
}

// ExtSveMemPair builds the two-general-register gather/scatter memory
// operand, (R21)(R7) style, with the optionals scale Shift the <<s suffix
// spells and RSP the second parenthesis's stack-pointer spelling.
func ExtSveMemPair(base, shift, off int, sp bool) ExtOperand {
	op := ExtOperand{Kind: ExtSveMem, Reg: base, Shift: shift, Off: off}
	if sp {
		op.Off, op.Reg31 = 31, 2
	}
	return op
}

// ExtSveMemVector builds the vector-register gather/scatter memory operand,
// (Z23.D<<1)(R24) style: the base is a scalable vector of the given element
// size, optionally shifted, with the general offset register in off (-1 when
// the operand carries no second parenthesis).
func ExtSveMemVector(base int, arr ExtArrangement, shift, off int) ExtOperand {
	return ExtOperand{Kind: ExtSveMem, Reg: base, Arr: arr, Shift: shift, Off: off, BaseVec: true}
}

// ExtSveMemExtended builds the extended 32-bit-offset gather/scatter memory
// operand, (Z4.S.UXTW<<1)(R3) style: the base is a .S vector whose offsets
// the UXTW or SXTW extension widens, with the general offset register in off.
func ExtSveMemExtended(base int, sxtw bool, shift, off int) ExtOperand {
	op := ExtSveMemVector(base, ExtArrS, shift, off)
	op.Extend = 1
	if sxtw {
		op.Extend = 2
	}
	return op
}

// ExtSveMemImmediate builds the immediate-offset gather/scatter memory
// operand, 6(Z7.S) style: the byte displacement rides Imm, the vector base
// carries the element size, and the encoder scales the displacement by the
// access size into the five-bit immediate field.
func ExtSveMemImmediate(base int, arr ExtArrangement, disp int64) ExtOperand {
	return ExtOperand{Kind: ExtSveMem, Reg: base, Arr: arr, Imm: disp, Off: -1, BaseVec: true}
}

// ExtImmediate builds an unshifted immediate operand.
func ExtImmediate(v int64) ExtOperand {
	return ExtOperand{Kind: ExtImm, Imm: v}
}

// ExtShiftedImmediate builds an immediate operand with a spelled LSL amount.
func ExtShiftedImmediate(v int64, shift int) ExtOperand {
	return ExtOperand{Kind: ExtImm, Imm: v, Shift: shift, HasShift: true}
}

// ExtMemory builds a base-relative memory operand, 4660(R8) style: the base
// is a 64-bit general register number, 0..15, and the displacement rides the
// ModR/M disp8 or disp32 form the encoder picks.  No index register and no
// scale: the base-plus-displacement shape alone.
func ExtMemory(base int, disp int64) ExtOperand {
	return ExtOperand{Kind: ExtMem, Reg: base, Imm: disp}
}

// ExtBroadcast builds the {1toN} broadcast spelling of a base-relative memory
// operand, the amd64 packed forms' m16bcst shape: the base is a 64-bit general
// register number, 0..15, the displacement keeps the plain ModR/M semantics,
// and the encoder sets EVEX.b so the single element splats across the lanes.
func ExtBroadcast(base int, disp int64) ExtOperand {
	return ExtOperand{Kind: ExtMem, Reg: base, Imm: disp, Broadcast: true}
}

// ExtScaledMemory builds the base-plus-scaled-index memory operand, the amd64
// SIB shape: the base and the index are 64-bit general register numbers,
// 0..15, the scale is the byte multiplier 1, 2, 4 or 8, and the displacement
// keeps the plain ModR/M disp8 or disp32 semantics.
func ExtScaledMemory(base, index, scale int, disp int64) ExtOperand {
	return ExtOperand{Kind: ExtMem, Reg: base, Imm: disp, Index: index, Scale: scale, HasIndex: true}
}

// ExtField is one named field of the 32-bit encoding word: a bit offset from
// the least significant end and the field's width.
type ExtField struct {
	Off   uint8
	Width uint8
}

// extMask returns the field's bits as a mask.
func extMask(f ExtField) uint32 {
	return ^uint32(0) >> (32 - f.Width)
}

// extSet ORs v into the field of word.
func extSet(word uint32, f ExtField, v uint32) uint32 {
	return word | (v&extMask(f))<<f.Off
}

// The fields the SVE integer classes use.  The 5-bit register fields are
// named after their role in the three-vector class; the predicated class
// reuses extFieldRn for its Zm operand and extFieldPg for the governing
// predicate, which that class narrows to three bits (P0-P7).
//
// The predicate classes place their operands in the same neighbourhood:
// Pd in a four-bit field at bit 0, the governing predicate either narrow
// (three bits, P0-P7) or wide (four bits, P0-P15) at bit 10, the first
// source predicate in the five-bit slot at bit 5, and Pm in a three-bit
// field at bit 16.  The general registers of the while-compare class use
// the five-bit Rm slot at bit 16.
var (
	extFieldRd   = ExtField{0, 5}  // destination (Zd or Zdn)
	extFieldRn   = ExtField{5, 5}  // first source (Zn, or Zm in the predicated class)
	extFieldRm   = ExtField{16, 5} // second source (Zm in the three-vector class)
	extFieldPg   = ExtField{10, 3} // governing predicate P0-P7 (predicated class)
	extFieldImm8 = ExtField{5, 8}  // the immediate, bits 12..5
	extFieldSh   = ExtField{13, 1} // the shift flag: 1 means LSL #8
	extSizeBHSD  = ExtField{22, 2} // element-size field of every class here, bits 23..22
	extFieldPd   = ExtField{0, 4}  // predicate destination P0-P15
	extFieldPn   = ExtField{5, 5}  // predicate source slot P0-P15 (bit 4 unused here)
	extFieldPgN  = ExtField{10, 3} // narrow governing predicate P0-P7
	extFieldPgW  = ExtField{10, 4} // wide governing predicate P0-P15
	extFieldPm   = ExtField{16, 3} // predicate source P0-P7
	extFieldPnc  = ExtField{0, 3}  // predicate-as-counter destination PN8-PN15, field holds reg-8
	extFieldPn4  = ExtField{5, 4}  // predicate source P0-P15 at bits 8..5 (counter family)
	extFieldImm6 = ExtField{5, 6}  // the signed imm6 of the vector-length arithmetic
	// The tsz:imm3 shift-immediate fields: the amount rides a 5..7-bit
	// integer C, split imm3 (the low three bits), a two-bit tsz chunk and
	// a one- or two-bit tsz top.  The three-vector classes split into
	// bits 18..16, 20..19 and 22; the predicated class into bits 7..5,
	// 9..8 and 23..22.  The tsz chunks are the arrangement's own spelling
	// and stand in for the size field these classes do not carry.
	extFieldImm3T16 = ExtField{16, 3} // the low three bits of C, three-vector classes
	extFieldTszM19  = ExtField{19, 2} // the middle tsz chunk of the three-vector classes
	extFieldTszH22  = ExtField{22, 1} // the top tsz bit of the three-vector classes
	extFieldImm3T5  = ExtField{5, 3}  // the low three bits of C, predicated class
	extFieldTszM8   = ExtField{8, 2}  // the middle tsz chunk of the predicated class
	extFieldTszH22W = ExtField{22, 2} // the top tsz chunk of the predicated class
)

// ExtForm enumerates the operand shapes the extension layer defines, in Plan
// 9 order (sources first, destination last).  A destructive SVE operand is
// written once, in destination position: the encoding carries no second copy.
type ExtForm uint8

// Operand shapes.
const (
	// ExtFormVectors is the unpredicated three-vector form, the SVE integer
	// add/subtract (unpredicated) class: ADD Z0.S, Z1.S, Z2.S computes
	// Z0 = Z1 + Z2.  Operands: Zn, Zm, Zd.
	ExtFormVectors ExtForm = iota
	// ExtFormPredicated is the governed destructive form, the SVE integer
	// add/subtract vectors (predicated) class: ADD Z1.S, P0/M, Z0.S computes
	// Z0 = Z0 + Z1 for the active lanes.  Operands: Zm, Pg/M, Zdn.  The
	// governing predicate is a 3-bit field, so only P0-P7 encode here, and
	// the class takes the merging qualifier alone: a zeroing form would need
	// a MOVPRFX expansion, which one data word cannot carry.
	ExtFormPredicated
	// ExtFormImmediate is the add/subtract immediate form, the SVE integer
	// add/subtract (immediate) class: ADD $255, Z0.S computes
	// Z0 = Z0 + 255.  Operands: imm{, LSL #8}, Zdn.  The constant is an
	// unsigned imm8, optionally shifted left by 8 bits; a bare multiple of
	// 256 (up to 65280) derives the shift, the spelling the GNU assembler
	// canonicalises too.  .B takes no shift.
	ExtFormImmediate
	// ExtFormSignedImmediate is the signed immediate form of the SVE integer
	// multiply (immediate) class: MUL $-128, Z0.B computes Z0 = Z0 * -128.
	// Operands: simm8, Zdn.  No shift exists in this class.
	ExtFormSignedImmediate
	// The amd64 layer's operand shapes, sources first, destination last.
	// The vector register class an entry takes comes from the encoding
	// template (the L'L field names it), not from the form.
	// ExtFormAmdVec3 is the EVEX non-destructive three-vector form:
	// VCVTNE2PS2BF16 Z6, Z5, Z4.  Operands: src1, src2, dest.
	ExtFormAmdVec3
	// ExtFormAmdVec2 is the two-vector form: VPOPCNTD Z1, Z2, VCOMISH X1, X2.
	// Operands: src, dest.
	ExtFormAmdVec2
	// ExtFormAmdVec2Half is the two-vector form whose destination is the
	// half-width companion of the source, equal at 128 bits: VCVTNEPS2BF16
	// Y6, Z5.  Operands: src, dest.
	ExtFormAmdVec2Half
	// ExtFormAmdVec2Wide is the two-vector form whose source is the half-width
	// companion of the destination, equal at 128 bits: VCVTPH2DQ Z6, Y5, where
	// L'L names the destination.  Operands: src, dest.
	ExtFormAmdVec2Wide
	// ExtFormAmdVec2Quarter is the two-vector form whose source is the
	// quarter-width companion of the destination, the XMM class at every
	// length: VCVTPH2QQ Z6, X5.  Operands: src, dest.
	ExtFormAmdVec2Quarter
	// ExtFormAmdVec2ToQuarter is the two-vector form whose destination is the
	// quarter-width companion of the source, the XMM class at every length:
	// VCVTQQ2PH X6, Z5.  Operands: src, dest.
	ExtFormAmdVec2ToQuarter
	// ExtFormAmdMask2 is the form with an opmask destination and two vector
	// sources: VP2INTERSECTD K0, Z2, Z1.  Operands: src1, src2, dest.
	ExtFormAmdMask2
	// ExtFormAmdVecGprVec is the three-operand conversion with a
	// general-register source: VCVTSI2SH X1, X2, EAX.  Operands: src1, gpr,
	// dest.
	ExtFormAmdVecGprVec
	// ExtFormAmdGprVec is the two-operand form with a general-register
	// source and a vector destination: VMOVW X1, EAX.  Operands: gpr, dest.
	ExtFormAmdGprVec
	// ExtFormAmdVecGpr is the two-operand form with a vector source and a
	// general-register destination: VMOVW EAX, X1 and VCVTSH2SI EAX, X1.
	// Operands: src, dest.
	ExtFormAmdVecGpr
	// ExtFormAmdVec3Imm is the three-vector form with a control immediate,
	// VGETMANTSH $11, X28, X29, X30 style: the immediate leads, the order
	// the reference listings write it in.  Operands: imm, src1, src2, dest.
	// The immediate's layout is named by the entry's Imm8 kind.
	ExtFormAmdVec3Imm
	// ExtFormAmdMask2Imm is the opmask-destination form with a control
	// immediate: VCMPSH $7, X28, X29, K5.  Operands: imm, src1, src2, dest,
	// where dest is an opmask register and the immediate's layout is named
	// by the entry's Imm8 kind.
	ExtFormAmdMask2Imm
	// ExtFormAmdVec2Imm is the two-vector form with a control immediate,
	// VRNDSCALEPH $0x7b, Z5, Z6 style: the immediate leads, the order the
	// reference listings write it in.  Operands: imm, src, dest, and the
	// immediate's layout is named by the entry's Imm8 kind.
	ExtFormAmdVec2Imm
	// ExtFormAmdMemVec is the memory-load form: VMOVSH X30, 4660(R8) shape,
	// the manual's xmm1, m16 lines that stand beside the register form.
	// Operands: mem, dest.
	ExtFormAmdMemVec
	// ExtFormAmdVecMem is the memory-store form: VMOVSH 4660(R9), X29
	// shape, the manual's m16, xmm1 lines.  Operands: src, mem.
	ExtFormAmdVecMem
	// ExtFormPredicateLogical is the predicate logical-operation form of the
	// SVE2.1 predicate classes: PAND P4.B, P2.B, P1.Z, P14.B computes
	// P14 = P4 AND P2 over the active lanes of P1.  Operands: Pm.B, Pn.B,
	// Pg/Z, Pd.B.  The zeroing qualifier on the governing predicate is part
	// of the spelling; every arrangement is .B and the class carries no size
	// field.
	ExtFormPredicateLogical
	// ExtFormPredicateSelect is PSEL's form, PSEL P4.B, P2.B, P1, P14.B:
	// the governing predicate arrives bare, without a qualifier.  Otherwise
	// identical to ExtFormPredicateLogical.
	ExtFormPredicateSelect
	// ExtFormPredicateLogicalDest is the break form whose first operand is
	// the destination read back: PBRKN P4.B, P2.B, P1.Z, P4.B.  Operands:
	// Pdm.B, Pn.B, Pg/Z, Pdm.B, with operand 1 required to equal operand 4;
	// the encoding carries the register once.
	ExtFormPredicateLogicalDest
	// ExtFormPredicateBreak is the three-operand break form, PBRKA P5.B,
	// P9.Z, P2.B.  Operands: Pn.B, Pg/Z or Pg/M (both spellings encode the
	// one word the manual gives), Pd.B.  The governing predicate is the wide
	// four-bit field, P0-P15.
	ExtFormPredicateBreak
	// ExtFormPredicateBreakZero is ExtFormPredicateBreak with the zeroing
	// qualifier alone, PBRKAS P5.B, P9.Z, P4.B.
	ExtFormPredicateBreakZero
	// ExtFormPredicatePermute is the predicate permutation form, PTRN1 P5.D,
	// P4.D, P2.D.  Operands: Pm.T, Pn.T, Pd.T under one shared arrangement
	// (.B, .H, .S or .D), which feeds the size field.
	ExtFormPredicatePermute
	// ExtFormPredicateFirst is PFIRST's form, PPFIRST P5.B, P9, P5.B, with
	// the destination read back like ExtFormPredicateLogicalDest.  Operands:
	// Pdn.B, Pg (bare), Pdn.B.
	ExtFormPredicateFirst
	// ExtFormPredicateNext is PNEXT's form, PPNEXT P5.D, P4, P5.D, the
	// destination-read-back shape with an arrangement and a size field.
	// Operands: Pdn.T, Pv (bare), Pdn.T.
	ExtFormPredicateNext
	// ExtFormPredicateOne writes or reads a single predicate, PPFALSE P13.B
	// or the unpredicated RDFFR P13.B.  Operands: Pd.B.
	ExtFormPredicateOne
	// ExtFormPredicateWrite is WRFFR's single-source form, PWRFFR P13.B: the
	// one predicate sits in the source slot, not the destination.
	// Operands: Pn.B.
	ExtFormPredicateWrite
	// ExtFormPredicateFFRRead is the predicated first-fault read, PRDFFR
	// P14.Z, P0.B.  Operands: Pg/Z, Pd.B; the governing predicate is the
	// wide four-bit field.
	ExtFormPredicateFFRRead
	// ExtFormPredicateMove is the predicate reverse, PREV P14.S, P13.S.
	// Operands: Pn.T, Pd.T under one shared arrangement.
	ExtFormPredicateMove
	// ExtFormPredicateUnpack is the predicate unpack, PPUNPKHI P14.B, P0.H:
	// the arrangements are fixed by the class (.B source, .H destination)
	// and carry no size field.  Operands: Pn.B, Pd.H.
	ExtFormPredicateUnpack
	// ExtFormPredicateTest is PTEST, PPTEST P14.B, P0, which sets the flags
	// and takes no destination.  Operands: Pn.B, Pg (bare).
	ExtFormPredicateTest
	// ExtFormWhile is the while-compare form, PWHILELT R2, R10, P10.H:
	// P10 counts the lanes where the signed comparison holds.  Operands:
	// Rm (R0-R30), Rn (R0-R30), Pd.T, the arrangement feeding the size
	// field.  The first written register is the comparison bound and the
	// second the start of the count, the order the toolchain's corpus
	// spells and the JIT run under qemu-user confirmed: PWHILELT R1, R0,
	// P0.S with R1=4 builds four active lanes.
	ExtFormWhile
	// ExtFormPredicateCounter is PTRUE's counter-register form, PPTRUE
	// PN14.S: the destination is a predicate-as-counter register, spelled
	// PN8-PN15 and encoded as reg-8 in the three-bit field.  Operands:
	// PNd.T.
	ExtFormPredicateCounter
	// ExtFormNone takes no operands at all, SETFFR.
	ExtFormNone
	// ExtFormZUnary is the SVE2.1 Z-alias unary predicated form, ZABS Z7.D,
	// P4.M, Z13.D.  Operands: Zn.T, Pg/M or Pg/Z (the row's PgQual says
	// which), Zd.T, one shared arrangement feeding the size field, or the
	// row's fixed arrangement where the class locks one (.Q, .D).  Fields:
	// Zn in the source slot, Pg narrow, Zd in the destination.
	ExtFormZUnary
	// ExtFormZPredicatedSource is the Z-alias binary predicated form,
	// ZADD Z15.B, Z0.B, P3.M, Z0.B: the destination's source copy is
	// spelled and must equal the destination.  Operands: Zm.T, Zdn.T,
	// Pg/M, Zdn.T.  Fields: Zm in the first-source slot at bits 9..5, Pg
	// narrow, Zdn in the destination slot; bits 16..20 are class bits no
	// operand touches.
	ExtFormZPredicatedSource
	// ExtFormZImmediateSource is the Z-alias immediate form, ZADD $6,
	// Z7.D, Z7.D: the destination's source copy is spelled and must equal
	// the destination, the register encoding carried once.  Operands:
	// imm{, LSL #8}, Zdn.T, Zdn.T.
	ExtFormZImmediateSource
	// ExtFormZSelect is the vector select, ZSEL Z23.B, Z21.B, P14, Z2.B.
	// Operands: Zm.T, Zn.T, Pv (bare), Zd.T, one shared arrangement.
	ExtFormZSelect
	// ExtFormZGov is the governed compact/expand, ZCOMPACT Z7.D, P4,
	// Z13.D.  Operands: Zn.T, Pg (bare), Zd.T, one shared arrangement.
	ExtFormZGov
	// ExtFormZMove is the vector reverse, ZREV Z1.S, Z26.S.  Operands:
	// Zn.T, Zd.T, one shared arrangement.
	ExtFormZMove
	// ExtFormZMoveBare is MOVPRFX's arrangement-less spelling, ZMOVPRFX
	// Z11, Z6.  Operands: Zn, Zd, no suffixes at all.
	ExtFormZMoveBare
	// ExtFormZUnpack is the vector unpack, ZSUNPKHI Z15.B, Z0.H: the
	// source is locked to .B, the destination's arrangement feeds the size
	// field.  Operands: Zn.B, Zd.T.
	ExtFormZUnpack
	// ExtFormZFromGeneral copies a general register into a vector,
	// ZDUP R2, Z10.D and ZINSR R2, Z10.D: the class locks the arrangement
	// into the word, so the row's Arr is validated and nothing is encoded
	// from it.  Operands: R (R0-R30), Zd.T.
	ExtFormZFromGeneral
	// ExtFormVectorsZm is the unpredicated three-vector form whose
	// spelled order starts with the second source: ZADD Z7.D, Z23.D, Z13.D
	// spells Zm first, where the SVE1-era spellings spell Zn first.  The
	// fields are the standard three-vector slots; only the operand order
	// differs.  Rows with a fixed arrangement (the .D logical aliases, the
	// .Q permutations) validate it and write no size field.
	ExtFormVectorsZm
	// ExtFormZLastReg is the last-active-element to register,
	// ZLASTA Z10.D, P3, R15.  Operands: Zn.T, Pg (bare), R (R0-R30), the
	// arrangement feeding the size field.
	ExtFormZLastReg
	// ExtFormZReadBack is the SVE2 crypto three-operand form whose written
	// order spells the destination twice: ZSM4E Z7.S, Z6.S, Z6.S.  Operands:
	// Zn.T, Zd.T, Zd.T, where operands 2 and 3 name the same register and
	// the encoding carries it once; the row's arrangement is locked into
	// the word.
	ExtFormZReadBack
	// ExtFormZSameReg is the SVE2 AES unary whose source is the destination
	// read back: ZAESIMC Z11.B, Z11.B.  Operands: Zd.T, Zd.T, the same
	// register twice, encoded once in the destination slot.
	ExtFormZSameReg
	// ExtFormCTerm is the SVE2 loop-condition terminator, CTERMEQ ZR, R25.
	// Operands: Rm (R0-R30 or ZR), Rn (R0-R30 or ZR), both in the standard
	// five-bit slots; the class sets no register result, only the flags.
	ExtFormCTerm
	// ExtFormCountP is the count-active-elements form, PCNTP P2.B, P14, R2.
	// Operands: Pn.T, Pg (bare), Rd (R0-R30 or ZR); the arrangement feeds
	// the size field, Pg occupies the wide four-bit field and Pn the
	// five-bit source slot.
	ExtFormCountP
	// ExtFormCountPn is the predicate-counter step with the scalar result
	// dropped, PDECP P14.S, ZR.  Operands: Pn.T, ZR; the predicate occupies
	// the four-bit field at bits 8..5, the zero register the destination
	// slot, and the arrangement feeds the size field.
	ExtFormCountPn
	// ExtFormCountPnW is the predicate-counter step with a scalar result,
	// PSQDECPW R8, P10.D, R8.  Operands: Rd, Pn.T, Rd, where operands 1 and
	// 3 name the same register; the predicate occupies the four-bit field at
	// bits 8..5 and its arrangement feeds the size field.
	ExtFormCountPnW
	// ExtFormReduce is the SVE reduction into a SIMD scalar, ZSADDVD Z6.B,
	// P3, V2.  Operands: Zn.T, Pg (bare), Vd (V0-V31); the governing
	// predicate is the narrow three-bit field and the row's arrangement is
	// either locked into the word or read off Zn where the class sizes from
	// the source.
	ExtFormReduce
	// ExtFormReduceReadBack is the strict-accumulation reduction whose SIMD
	// destination is spelled twice, ZFADDAD Z9.D, V10, P2, V10.  Operands:
	// Zn.T, Vd, Pg (bare), Vd, where operands 2 and 4 name the same
	// register.
	ExtFormReduceReadBack
	// ExtFormSveLoad is the gather load: ZLD1B (Z6.D)(R14), P4.Z, [Z13.D].
	// Operands: mem (the addressing mode the row's SveMode names), Pg/Z
	// (P0-P7, zeroing), Zt.T (the row's locked list arrangement).  The first
	// parenthesised register or the scaled immediate fills the second-source
	// slot, the second parenthesis or the immediate-mode base the first-
	// source slot, the predicate the narrow governing field and the list
	// register the destination slot.
	ExtFormSveLoad
	// ExtFormSveStore is the scatter store: ZST1B [Z7.D], P4, (R21)(R7).
	// Operands: Zt.T (the row's locked list arrangement), Pg (bare, P0-P7),
	// mem.  The field layout mirrors the load with the list first.
	ExtFormSveStore
	// ExtFormNarrow is the SVE2.1 two-to-one narrowing form, ZADDHNB Z22.S,
	// Z10.S, Z8.H: two wide vectors sum and the destination keeps the high
	// half of each result.  Operands: Zm.T2, Zn.T2, Zd.T, where T2 is one
	// step wider than T (.H+.B, .S+.H, .D+.S).  The single size field
	// over-determines the pair, so the arrangements are validated together.
	ExtFormNarrow
	// ExtFormQuadReduce is the SVE2.1 quadword reduction, the accumulator
	// first: ZADDQV Z25.S, P3, V5.S4.  Operands: Zdn.T, Pg (bare, P0-P7),
	// Vn with the counted quadword spelling .B16, .H8, .S4 or .D2 matching
	// Zdn's arrangement.  The fields place Zdn in the first-source slot,
	// the predicate in the narrow governing field and the vector in the
	// destination slot, the reduction class's own layout.
	ExtFormQuadReduce
	// ExtFormShiftWide is the wide-vector shift, ZASR Z7.D, Z6.H, Z13.H:
	// the shift amounts ride a double-width vector locked to .D while the
	// shifted data shares one narrower arrangement, which feeds the size
	// field.  Operands: Zm.D, Zn.T, Zd.T.
	ExtFormShiftWide
	// ExtFormConvert is the SVE2 BFloat16 convert with a governing
	// predicate, ZBFCVT Z13.S, P1.M, Z22.H: a widening convert whose
	// source is locked to .S and destination to .H.  Operands: Zn.S,
	// Pg/M or Pg/Z (the row's PgQual names which), Zd.H.  Fields: Zn in
	// the first-source slot, Pg narrow, Zd in the destination slot.
	ExtFormConvert
	// ExtFormMulPred is the SVE2 BFloat16 multiply-accumulate with an
	// independent destination, ZBFMLA Z23.H, Z13.H, P1.M, Z22.H.  Operands:
	// Zm.H, Zn.H, Pg/M, Zda.H.  Fields: Zm at bits 16..20, Zn in the
	// first-source slot, Pg narrow, Zda in the destination slot.
	ExtFormMulPred
	// ExtFormVLArith is the vector-length arithmetic, ADDVL $9, R11, RSP:
	// a signed imm6 multiple of the vector length added to a general
	// register, either slot spelled RSP.  Operands: imm, Rn|SP, Rd|SP.
	// Fields: the imm6 at bits 10..5, Rn at bits 20..16, Rd at bits 4..0.
	ExtFormVLArith
	// ExtFormVLRead is the vector-length read, RDVL $1, R27.  Operands:
	// imm, Rd (R0-R30).  Fields: the imm6 at bits 10..5, Rd at bits 4..0.
	ExtFormVLRead
	// ExtFormCompare is the SVE2 compare to a predicate destination,
	// ZCMPEQ Z0.H, Z2.H, P0.Z, P14.H: the comparison writes the zeroing
	// predicate P0-P7 spelled with its zeroing qualifier.  Operands: Zm.T,
	// Zn.T, Pg/Z, Pd.T under one shared arrangement, which feeds the size
	// field.  Fields: Zm at bits 16..20, Zn in the first-source slot, Pg
	// narrow, Pd in the four-bit destination slot.
	ExtFormCompare
	// ExtFormCompareWide is the wide compare, ZCMPEQ Z0.D, Z12.S, P0.Z,
	// P14.S: the compared magnitudes ride a double-width vector locked to
	// .D while the compared data shares one narrower arrangement.  Operands:
	// Zm.D, Zn.T, Pg/Z, Pd.T.
	ExtFormCompareWide
	// ExtFormLongMul is the SVE2 BFloat16 lengthened multiply,
	// ZBFMLALB Z7.H, Z6.H, Z23.S: two halfword vectors multiply into a
	// word accumulator, the wide source locked to .S.  Operands: Za.H,
	// Zn.H, Zm.S (the row's Arr names the halfword pair).  Fields: Za at
	// bits 16..20, Zn in the first-source slot, Zm in the destination
	// slot.
	ExtFormLongMul
	// ExtFormThreeSource is the SVE2 three-source bitwise form, ZBCAX
	// Z23.D, Z13.D, Z21.D, Z21.D: two sources combine with the destination
	// under the class's own operation, locked to quadwords.  Operands:
	// Za.D, Zm.D, Zdn.D, Zdn.D, the last two naming the same register,
	// which the encoding carries once in the destination slot.
	ExtFormThreeSource
	// ExtFormCountPnVec is the predicate-counter step whose result stays a
	// vector, ZDECP P14.S, Z26.S: the vector is decremented in place by the
	// predicate's active element count.  Operands: Pm.T, Zdn.T; the
	// predicate occupies the four-bit field at bits 8..5, the vector the
	// destination slot, and the predicate's arrangement feeds the size
	// field.
	ExtFormCountPnVec
	// ExtFormShiftImmPred is the predicated shift by immediate, ZSQSHL
	// $6, Z23.B, P1.M, Z23.B.  Operands: imm, Zdn.T, Pg/M, Zdn.T, the
	// destination spelled twice and encoded once.  The amount rides the
	// class's tsz:imm3 fields: C = esize + amount, split imm3 into bits
	// 7..5, the low tsz pair into bits 9..8 and the top tsz pair into
	// bits 23..22, where the tsz bits are the arrangement's own spelling
	// and double as its size encoding; no separate size field exists.
	// The amount runs 1..esize-1 and the merging qualifier is the only
	// one the class spells.
	ExtFormShiftImmPred
	// ExtFormShiftImmNarrow is the three-vector narrowing shift by
	// immediate, ZSHRNB $9, Z7.S, Z23.H: a right shift of the wide source
	// whose result the narrow destination keeps, one element step down
	// (.H+.B, .S+.H, .D+.S).  Operands: imm, Zn.Tb, Zd.T.  C = 2 x esize
	// - amount over the destination's element size, split imm3 into bits
	// 18..16, the low tsz pair into bits 20..19 and the top tsz bit into
	// bit 22; the amount runs 1..esize.
	ExtFormShiftImmNarrow
	// ExtFormShiftImmWide is the three-vector widening shift by
	// immediate, ZSSHLLB $5, Z22.S, Z10.D: a left shift of the narrow
	// source into a destination one element step up (.B+.H, .H+.S,
	// .S+.D).  Operands: imm, Zn.Tb, Zd.T.  C = esize + amount over the
	// source's element size, split like the narrowing class; the amount
	// runs 0..esize-1.
	ExtFormShiftImmWide
	// ExtFormShiftImmSame is the same-size shift by immediate, ZSRI $6,
	// Z7.D, Z23.D and its accumulating siblings ZSSRA, ZUSRA, ZSRSRA and
	// ZURSRA: a right shift within one shared arrangement, the
	// destination (or the read-modify-write accumulator) in the
	// destination slot.  Operands: imm, Zn.T, Zd.T.  C = 2 x esize -
	// amount over the shared element size, split imm3 into bits 18..16,
	// the low tsz pair into bits 20..19 and the top tsz pair into bits
	// 23..22; the amount runs 1..esize-1.
	ExtFormShiftImmSame
	// ExtFormShiftImmPredRight is the predicated right shift by
	// immediate, ZASR $6, Z23.B, P1.M, Z23.B and ZASRD beside it: the
	// right-shift counterpart of the predicated left shifts.  Operands:
	// imm, Zdn.T, Pg/M, Zdn.T.  C = 2 x esize - amount over the
	// destination's element size, split like the predicated left shifts;
	// the amount runs 1..esize-1.
	ExtFormShiftImmPredRight
	// ExtFormShiftImmXar is the three-source extract and narrow, ZXAR
	// $6, Z23.B, Z21.B, Z21.B: the destination is spelled twice and
	// encoded once.  Operands: imm, Zm.T, Zdn.T, Zdn.T.  C = 2 x esize -
	// amount over the shared element size, split like the same-size
	// class; the amount runs 1..esize-1.
	ExtFormShiftImmXar
)

// Arity returns the operand count the form takes.
func (f ExtForm) Arity() int {
	switch f {
	case ExtFormVectors, ExtFormPredicated, ExtFormPredicatePermute,
		ExtFormPredicateFirst, ExtFormPredicateNext, ExtFormWhile,
		ExtFormPredicateBreak, ExtFormPredicateBreakZero,
		ExtFormZUnary, ExtFormZGov, ExtFormVectorsZm, ExtFormZImmediateSource:
		return 3
	case ExtFormPredicateLogical, ExtFormPredicateSelect, ExtFormPredicateLogicalDest,
		ExtFormZPredicatedSource, ExtFormZSelect, ExtFormThreeSource, ExtFormMulPred,
		ExtFormCompare, ExtFormCompareWide:
		return 4
	case ExtFormImmediate, ExtFormSignedImmediate, ExtFormPredicateFFRRead,
		ExtFormPredicateMove, ExtFormPredicateUnpack, ExtFormPredicateTest,
		ExtFormZMoveBare, ExtFormZFromGeneral,
		ExtFormZMove, ExtFormZUnpack:
		return 2
	case ExtFormAmdVec3, ExtFormAmdMask2, ExtFormAmdVecGprVec:
		return 3
	case ExtFormAmdVec2, ExtFormAmdVec2Half, ExtFormAmdVec2Wide, ExtFormAmdVec2Quarter,
		ExtFormAmdVec2ToQuarter, ExtFormAmdGprVec, ExtFormAmdVecGpr:
		return 2
	case ExtFormAmdVec3Imm, ExtFormAmdMask2Imm:
		return 4
	case ExtFormAmdVec2Imm:
		return 3
	case ExtFormAmdMemVec, ExtFormAmdVecMem:
		return 2
	case ExtFormPredicateOne, ExtFormPredicateWrite, ExtFormPredicateCounter:
		return 1
	case ExtFormZReadBack, ExtFormCountP, ExtFormCountPnW, ExtFormReduce, ExtFormZLastReg:
		return 3
	case ExtFormZSameReg, ExtFormCountPn, ExtFormCTerm, ExtFormVLRead:
		return 2
	case ExtFormCountPnVec:
		return 2
	case ExtFormShiftImmPred, ExtFormShiftImmPredRight, ExtFormShiftImmXar:
		return 4
	case ExtFormShiftImmNarrow, ExtFormShiftImmWide, ExtFormShiftImmSame:
		return 3
	case ExtFormReduceReadBack:
		return 4
	case ExtFormSveLoad, ExtFormSveStore, ExtFormNarrow, ExtFormQuadReduce, ExtFormShiftWide,
		ExtFormConvert, ExtFormLongMul:
		return 3
	case ExtFormVLArith:
		return 3
	case ExtFormNone:
		return 0
	default:
		return 0
	}
}

// Kinds returns the operand kind each position of the form wants, in the
// order the operands arrive.  The registry uses the list to pick the most
// specific rejection when every matching form refuses an operand list.
func (f ExtForm) Kinds() []ExtOperandKind {
	switch f {
	case ExtFormVectors:
		return []ExtOperandKind{ExtZReg, ExtZReg, ExtZReg}
	case ExtFormPredicated:
		return []ExtOperandKind{ExtZReg, ExtPReg, ExtZReg}
	case ExtFormImmediate, ExtFormSignedImmediate:
		return []ExtOperandKind{ExtImm, ExtZReg}
	// The amd64 forms return no kinds: the exact vector class depends on the
	// entry's encoding template (its L'L field), which the form alone cannot
	// name, and the encode paths diagnose the class themselves.
	case ExtFormPredicateLogical, ExtFormPredicateSelect, ExtFormPredicateLogicalDest:
		return []ExtOperandKind{ExtPReg, ExtPReg, ExtPReg, ExtPReg}
	case ExtFormPredicateBreak, ExtFormPredicateBreakZero, ExtFormPredicateFFRRead:
		return []ExtOperandKind{ExtPReg, ExtPReg, ExtPReg}
	case ExtFormPredicatePermute:
		return []ExtOperandKind{ExtPReg, ExtPReg, ExtPReg}
	case ExtFormPredicateFirst, ExtFormPredicateNext:
		return []ExtOperandKind{ExtPReg, ExtPReg, ExtPReg}
	case ExtFormPredicateOne, ExtFormPredicateWrite, ExtFormPredicateCounter:
		return []ExtOperandKind{ExtPReg}
	case ExtFormPredicateMove, ExtFormPredicateUnpack, ExtFormPredicateTest:
		return []ExtOperandKind{ExtPReg, ExtPReg}
	case ExtFormWhile:
		return []ExtOperandKind{ExtGReg, ExtGReg, ExtPReg}
	case ExtFormZUnary, ExtFormZGov, ExtFormZMove, ExtFormVectorsZm:
		return []ExtOperandKind{ExtZReg, ExtZReg, ExtZReg}
	case ExtFormZPredicatedSource:
		return []ExtOperandKind{ExtZReg, ExtZReg, ExtPReg, ExtZReg}
	case ExtFormZImmediateSource:
		return []ExtOperandKind{ExtImm, ExtZReg, ExtZReg}
	case ExtFormZSelect:
		return []ExtOperandKind{ExtZReg, ExtZReg, ExtPReg, ExtZReg}
	case ExtFormZMoveBare:
		return []ExtOperandKind{ExtZReg, ExtZReg}
	case ExtFormZFromGeneral:
		return []ExtOperandKind{ExtGReg, ExtZReg}
	case ExtFormZLastReg:
		return []ExtOperandKind{ExtZReg, ExtPReg, ExtGReg}
	case ExtFormZReadBack:
		return []ExtOperandKind{ExtZReg, ExtZReg, ExtZReg}
	case ExtFormZSameReg:
		return []ExtOperandKind{ExtZReg, ExtZReg}
	case ExtFormCTerm:
		return []ExtOperandKind{ExtGReg, ExtGReg}
	case ExtFormCountP:
		return []ExtOperandKind{ExtPReg, ExtPReg, ExtGReg}
	case ExtFormCountPn:
		return []ExtOperandKind{ExtPReg, ExtGReg}
	case ExtFormCountPnVec:
		return []ExtOperandKind{ExtPReg, ExtZReg}
	case ExtFormShiftImmPred, ExtFormShiftImmPredRight, ExtFormShiftImmXar:
		return []ExtOperandKind{ExtImm, ExtZReg, ExtPReg, ExtZReg}
	case ExtFormShiftImmNarrow, ExtFormShiftImmWide, ExtFormShiftImmSame:
		return []ExtOperandKind{ExtImm, ExtZReg, ExtZReg}
	case ExtFormCountPnW:
		return []ExtOperandKind{ExtGReg, ExtPReg, ExtGReg}
	case ExtFormReduce:
		return []ExtOperandKind{ExtZReg, ExtPReg, ExtVReg}
	case ExtFormReduceReadBack:
		return []ExtOperandKind{ExtZReg, ExtVReg, ExtPReg, ExtVReg}
	case ExtFormSveLoad:
		return []ExtOperandKind{ExtSveMem, ExtPReg, ExtZReg}
	case ExtFormSveStore:
		return []ExtOperandKind{ExtZReg, ExtPReg, ExtSveMem}
	case ExtFormNarrow, ExtFormShiftWide, ExtFormLongMul:
		return []ExtOperandKind{ExtZReg, ExtZReg, ExtZReg}
	case ExtFormVLArith:
		return []ExtOperandKind{ExtImm, ExtGReg, ExtGReg}
	case ExtFormVLRead:
		return []ExtOperandKind{ExtImm, ExtGReg}
	case ExtFormConvert:
		return []ExtOperandKind{ExtZReg, ExtPReg, ExtZReg}
	case ExtFormThreeSource, ExtFormMulPred, ExtFormCompare, ExtFormCompareWide:
		return []ExtOperandKind{ExtZReg, ExtZReg, ExtPReg, ExtZReg}
	case ExtFormQuadReduce:
		return []ExtOperandKind{ExtZReg, ExtPReg, ExtVReg}
	case ExtFormNone:
		return nil
	default:
		return nil
	}
}

// String returns a short label for the form, for diagnostics.
func (f ExtForm) String() string {
	switch f {
	case ExtFormVectors:
		return "unpredicated vectors"
	case ExtFormPredicated:
		return "predicated (merging)"
	case ExtFormImmediate:
		return "unsigned immediate"
	case ExtFormSignedImmediate:
		return "signed immediate"
	case ExtFormAmdVec3:
		return "three vectors"
	case ExtFormAmdVec2:
		return "two vectors"
	case ExtFormAmdVec2Half:
		return "two vectors, half-width destination"
	case ExtFormAmdVec2Wide:
		return "two vectors, half-width source"
	case ExtFormAmdVec2Quarter:
		return "two vectors, quarter-width source"
	case ExtFormAmdVec2ToQuarter:
		return "two vectors, quarter-width destination"
	case ExtFormAmdMask2:
		return "two vectors into an opmask"
	case ExtFormAmdVecGprVec:
		return "vector, general register, vector"
	case ExtFormAmdGprVec:
		return "general register, vector"
	case ExtFormAmdVecGpr:
		return "vector, general register"
	case ExtFormAmdVec3Imm:
		return "immediate, three vectors"
	case ExtFormAmdMask2Imm:
		return "immediate, two vectors into an opmask"
	case ExtFormAmdVec2Imm:
		return "immediate and two vectors"
	case ExtFormAmdMemVec:
		return "memory into a vector"
	case ExtFormAmdVecMem:
		return "a vector into memory"
	case ExtFormPredicateLogical:
		return "predicate logical"
	case ExtFormPredicateSelect:
		return "predicate select"
	case ExtFormPredicateLogicalDest:
		return "predicate logical, shared destination"
	case ExtFormPredicateBreak:
		return "break"
	case ExtFormPredicateBreakZero:
		return "break, zeroing"
	case ExtFormPredicatePermute:
		return "predicate permutation"
	case ExtFormPredicateFirst:
		return "predicate first"
	case ExtFormPredicateNext:
		return "predicate next"
	case ExtFormPredicateOne:
		return "single predicate"
	case ExtFormPredicateWrite:
		return "single source predicate"
	case ExtFormPredicateFFRRead:
		return "FFR read"
	case ExtFormPredicateMove:
		return "predicate move"
	case ExtFormPredicateUnpack:
		return "predicate unpack"
	case ExtFormPredicateTest:
		return "predicate test"
	case ExtFormWhile:
		return "while compare"
	case ExtFormPredicateCounter:
		return "counter predicate"
	case ExtFormVectorsZm:
		return "unpredicated vectors, Zm first"
	case ExtFormZUnary:
		return "predicated vector"
	case ExtFormZPredicatedSource:
		return "predicated vector with source"
	case ExtFormZImmediateSource:
		return "immediate with source"
	case ExtFormZSelect:
		return "vector select"
	case ExtFormZGov:
		return "governed compact"
	case ExtFormZMove:
		return "vector move"
	case ExtFormZMoveBare:
		return "bare vector move"
	case ExtFormZUnpack:
		return "vector unpack"
	case ExtFormZFromGeneral:
		return "general into vector"
	case ExtFormZLastReg:
		return "last element to register"
	case ExtFormZReadBack:
		return "crypto vector, destination read back"
	case ExtFormZSameReg:
		return "crypto vector in place"
	case ExtFormCTerm:
		return "loop terminator"
	case ExtFormCountP:
		return "count to a register"
	case ExtFormCountPn:
		return "counter step, result dropped"
	case ExtFormCountPnVec:
		return "counter step on a vector"
	case ExtFormShiftImmPred:
		return "predicated shift by immediate"
	case ExtFormShiftImmNarrow:
		return "narrowing shift by immediate"
	case ExtFormShiftImmWide:
		return "widening shift by immediate"
	case ExtFormShiftImmSame:
		return "same-size shift by immediate"
	case ExtFormShiftImmPredRight:
		return "predicated right shift by immediate"
	case ExtFormShiftImmXar:
		return "three-source extract and narrow"
	case ExtFormCountPnW:
		return "counter step to a register"
	case ExtFormReduce:
		return "reduction to a SIMD register"
	case ExtFormReduceReadBack:
		return "accumulating reduction, destination read back"
	case ExtFormSveLoad:
		return "gather load"
	case ExtFormSveStore:
		return "scatter store"
	case ExtFormNarrow:
		return "narrowing two-to-one"
	case ExtFormQuadReduce:
		return "quadword reduction"
	case ExtFormShiftWide:
		return "wide shift"
	case ExtFormThreeSource:
		return "three-source bitwise"
	case ExtFormConvert:
		return "widening convert"
	case ExtFormMulPred:
		return "multiply-accumulate"
	case ExtFormLongMul:
		return "lengthened multiply"
	case ExtFormCompare:
		return "compare to a predicate"
	case ExtFormCompareWide:
		return "wide compare to a predicate"
	case ExtFormVLArith:
		return "vector-length arithmetic"
	case ExtFormVLRead:
		return "vector-length read"
	case ExtFormNone:
		return "no operands"
	default:
		return "unknown form"
	}
}

// ExtFeature names the architecture feature an extended instruction belongs
// to.  The field is metadata: the assembler offers every instruction it
// registers, and a feature check is the caller's decision, not the encoder's.
type ExtFeature string

// The features the arm64 layer covers.
const (
	ExtFeatureSVE    ExtFeature = "sve"
	ExtFeatureSVE2   ExtFeature = "sve2"
	ExtFeatureSVE2p1 ExtFeature = "sve2p1"
)

// ExtImm8Kind names the imm8-control layout an amd64 extended entry carries
// in its immediate operand.  The kind drives the validation at encode time:
// a value the manual reserves is an error, never a silent mis-encoding.
type ExtImm8Kind uint8

// The imm8-control layouts, ExtImm8None first as the zero value an entry
// without an immediate carries.
const (
	// ExtImm8None marks a form that takes no immediate operand.
	ExtImm8None ExtImm8Kind = iota
	// ExtImm8ScaleRound is the fraction-bits-plus-round-control layout of
	// VRNDSCALESH and VREDUCESH: imm8[7:4] carries the number of fraction
	// bits M, imm8[3] the precision-exception control, imm8[2] the rounding
	// mode source and imm8[1:0] the rounding mode.  Every byte encodes.
	ExtImm8ScaleRound
	// ExtImm8GetMant is the mantissa-extraction control of VGETMANTSH:
	// imm8[3:2] the sign control, imm8[1:0] the normalisation interval,
	// and imm8[7:4] reserved, which must encode as zero.
	ExtImm8GetMant
	// ExtImm8CmpPredicate is the comparison-predicate control of VCMPSH:
	// imm8[4:0] names one of the 32 predicates and the bits above are
	// masked away by the hardware, so every byte encodes.
	ExtImm8CmpPredicate
)

// String returns a short label for the imm8-control layout, for diagnostics.
func (k ExtImm8Kind) String() string {
	switch k {
	case ExtImm8ScaleRound:
		return "fraction bits and round control"
	case ExtImm8GetMant:
		return "mantissa extraction control"
	case ExtImm8CmpPredicate:
		return "comparison predicate"
	default:
		return "no immediate"
	}
}

// ExtInstr is one extended instruction: the metadata a lookup needs and the
// encoding as data.  Word holds the fixed bits of the 32-bit encoding with
// every operand field and the size field zero; the form says which fields the
// operands fill; the size field receives the arrangement's bits at encode
// time.  Ref names the manual entry the encoding is transcribed from, the
// golden source in place of a toolchain oracle.
type ExtInstr struct {
	Name    string     // upper-case mnemonic
	Summary string     // one line of hover documentation
	Word    uint32     // fixed encoding bits, operand fields zero
	Form    ExtForm    // operand shape
	Size    ExtField   // element-size field the arrangement fills
	Feature ExtFeature // sve, sve2 or sve2p1
	Ref     string     // the ARM ARM entry the encoding comes from
	// Bytes is the amd64 encoding template: the EVEX prefix, opcode and
	// ModR/M byte of one form, with every register-derived bit zero.  The
	// vector length and the general-register width an entry encodes are read
	// back out of it at encode time.
	Bytes []byte
	// Wig records that the entry ignores the W bit in its general-register
	// position, so both 32-bit and 64-bit registers encode.
	Wig bool
	// Imm8 names the imm8-control layout the amd64 entry's immediate
	// operand carries, ExtImm8None when the form takes none.  The arm64
	// entries all carry the zero value.
	Imm8 ExtImm8Kind
	// Mem names the 1-based operand position that may carry a memory
	// operand beside the register the position normally takes: 2 on the
	// arithmetic whose second source the manual spells xmm3/m16, 1 on the
	// narrow BF16 convert whose source it spells m256/m512.  Zero means
	// the form takes registers alone.  The load and store shapes are forms
	// of their own, ExtFormAmdMemVec and ExtFormAmdVecMem, and need no
	// flag.  The arm64 entries all carry the zero value.
	Mem int
	// Bcast records that the entry's memory position takes the {1toN}
	// broadcast beside the plain vector source, the SDM's m16bcst and
	// m32bcst spellings: one element the hardware splats across the lanes,
	// encoded as EVEX.b.  The packed arithmetic carries it; the scalar
	// forms and the full-width sources do not.  The arm64 entries all
	// carry the zero value.
	Bcast bool
	// Mask records that the entry's packed destination takes the write
	// mask, the SDM's {k1}{z} decorations: EVEX.aaa carries the masking
	// register and EVEX.z the zeroing bit.  The packed forms carry it; the
	// scalar forms, the compares without a vector destination, the
	// opmask-destination forms and the load and store shapes do not.  The
	// arm64 entries all carry the zero value.
	Mask bool
	// Er records that the entry's destination takes the embedded rounding
	// decoration, the {rn-sae} through {rz-sae} spellings the FP arithmetic
	// and the rounding conversions carry in their register forms: EVEX.b
	// selects the rounding context, EVEX.RC names the mode, and the memory
	// forms take none.  The arm64 entries all carry the zero value.
	Er bool
	// Sae records that the entry's destination takes the exception-suppression
	// decoration alone, the {sae} spelling the minima, maxima, compares and
	// exponent extracts carry: no mode is named and EVEX.RC stays zero.  The
	// arm64 entries all carry the zero value.
	Sae bool
	// PgQual names the qualifier the row's governing predicate requires,
	// where the form takes one: merging, zeroing or either (the MOVPRFX
	// classes spell both with one encoding).  Forms without such a
	// predicate ignore it.
	PgQual ExtQualifier
	// Arr fixes the one arrangement the row takes, where the class locks it
	// into the word (the .D-locked ZDUP and ZINSR general-register forms,
	// the .Q permutations).  ExtArrNone leaves the arrangement to the
	// operands and the size field.
	Arr ExtArrangement
	// The gather/scatter rows (ExtFormSveLoad and ExtFormSveStore) carry
	// their addressing mode as metadata: SveMode names the memory operand's
	// shape, SveShift the <<s scale the mode requires (for the
	// immediate-offset mode it is the access-size shift the displacement
	// divides by), and SveBase the element size the vector base must carry
	// (.S or .D where the mode takes a vector).  The list arrangement rides
	// Arr, locked per row: for the gathers it is part of the instruction's
	// identity, the offset index size.
	SveMode  uint8          // extMemNone or one of the extMem* modes below
	SveShift int            // the required <<s, or the access-size shift
	SveBase  ExtArrangement // the vector base's element size, where it has one
	// Vex records that the amd64 entry encodes through the two-byte VEX
	// prefix the AVX extensions carry, not through EVEX: a family with no
	// AVX-512 form, the AVX-VNNI-INT16 dot products, lays its C4 word over
	// five bytes, R/X/B inverted and the five-bit map in byte one, W and
	// vvvv complemented and L and pp in byte two.  A VEX row takes no mask,
	// broadcast or rounding decoration and no register above 15, and its
	// memory forms keep the classic displacement choices no VEX word
	// scales.  Every existing entry carries the zero value and encodes
	// through EVEX.
	Vex bool
}

// The arm64 gather/scatter addressing modes, the values SveMode carries.
const (
	extMemNone    uint8 = iota // the row takes no SVE memory operand
	extMemPair                 // (Rn{<<s})(Rm), two general registers
	extMemVecOff               // (Zn.T{<<s})(Rm), vector base, general offset
	extMemExt32                // (Zn.S.UXTW{<<s})(Rm), extended 32-bit offsets
	extMemImm                  // imm(Zn.T), vector base, immediate offset
	extMemVecBase              // (Zn.T), the vector base alone
)

// Encode assembles the operands into the 4 little-endian bytes of the
// instruction word.  The operand kinds, register ranges, arrangements and
// immediate ranges are validated against the form; an operand the class
// cannot carry is an error, never a silent mis-encoding.
func (in ExtInstr) Encode(ops []ExtOperand) ([]byte, error) {
	if len(ops) != in.Form.Arity() {
		return nil, fmt.Errorf("%s: the %s form takes %d operands, got %d",
			in.Name, in.Form, in.Form.Arity(), len(ops))
	}
	switch in.Form {
	case ExtFormVectors:
		return in.encodeVectors(ops)
	case ExtFormPredicated:
		return in.encodePredicated(ops)
	case ExtFormImmediate:
		return in.encodeImmediate(ops)
	case ExtFormSignedImmediate:
		return in.encodeSignedImmediate(ops)
	case ExtFormAmdVec3, ExtFormAmdVec2, ExtFormAmdVec2Half, ExtFormAmdMask2,
		ExtFormAmdVecGprVec, ExtFormAmdGprVec, ExtFormAmdVecGpr,
		ExtFormAmdVec3Imm, ExtFormAmdMask2Imm, ExtFormAmdMemVec, ExtFormAmdVecMem,
		ExtFormAmdVec2Wide, ExtFormAmdVec2Quarter, ExtFormAmdVec2ToQuarter,
		ExtFormAmdVec2Imm:
		return in.encodeAmd64(ops)
	case ExtFormPredicateLogical, ExtFormPredicateSelect:
		return in.encodePredicateLogical(ops)
	case ExtFormPredicateLogicalDest:
		return in.encodePredicateLogicalDest(ops)
	case ExtFormPredicateBreak, ExtFormPredicateBreakZero:
		return in.encodePredicateBreak(ops)
	case ExtFormPredicatePermute:
		return in.encodePredicatePermute(ops)
	case ExtFormPredicateFirst, ExtFormPredicateNext:
		return in.encodePredicateReadBack(ops)
	case ExtFormPredicateOne:
		return in.encodePredicateOne(ops)
	case ExtFormPredicateWrite:
		return in.encodePredicateWrite(ops)
	case ExtFormPredicateFFRRead:
		return in.encodePredicateFFRRead(ops)
	case ExtFormPredicateMove:
		return in.encodePredicateMove(ops)
	case ExtFormPredicateUnpack:
		return in.encodePredicateUnpack(ops)
	case ExtFormPredicateTest:
		return in.encodePredicateTest(ops)
	case ExtFormWhile:
		return in.encodeWhile(ops)
	case ExtFormPredicateCounter:
		return in.encodePredicateCounter(ops)
	case ExtFormZUnary:
		return in.encodeZUnary(ops)
	case ExtFormVectorsZm:
		return in.encodeVectorsZm(ops)
	case ExtFormZPredicatedSource:
		return in.encodeZPredicatedSource(ops)
	case ExtFormZImmediateSource:
		return in.encodeZImmediateSource(ops)
	case ExtFormZSelect:
		return in.encodeZSelect(ops)
	case ExtFormZGov:
		return in.encodeZGov(ops)
	case ExtFormZMove:
		return in.encodeZMove(ops)
	case ExtFormZMoveBare:
		return in.encodeZMoveBare(ops)
	case ExtFormZUnpack:
		return in.encodeZUnpack(ops)
	case ExtFormZFromGeneral:
		return in.encodeZFromGeneral(ops)
	case ExtFormZLastReg:
		return in.encodeZLastReg(ops)
	case ExtFormZReadBack:
		return in.encodeZReadBack(ops)
	case ExtFormZSameReg:
		return in.encodeZSameReg(ops)
	case ExtFormCTerm:
		return in.encodeCTerm(ops)
	case ExtFormCountP:
		return in.encodeCountP(ops)
	case ExtFormCountPn:
		return in.encodeCountPn(ops)
	case ExtFormCountPnVec:
		return in.encodeCountPnVec(ops)
	case ExtFormShiftImmPred:
		return in.encodeShiftImmPred(ops)
	case ExtFormShiftImmPredRight:
		return in.encodeShiftImmPredRight(ops)
	case ExtFormShiftImmNarrow:
		return in.encodeShiftImmNarrow(ops)
	case ExtFormShiftImmWide:
		return in.encodeShiftImmWide(ops)
	case ExtFormShiftImmSame:
		return in.encodeShiftImmSame(ops)
	case ExtFormShiftImmXar:
		return in.encodeShiftImmXar(ops)
	case ExtFormCountPnW:
		return in.encodeCountPnW(ops)
	case ExtFormReduce:
		return in.encodeReduce(ops)
	case ExtFormReduceReadBack:
		return in.encodeReduceReadBack(ops)
	case ExtFormSveLoad:
		return in.encodeSveLoad(ops)
	case ExtFormSveStore:
		return in.encodeSveStore(ops)
	case ExtFormNarrow:
		return in.encodeNarrow(ops)
	case ExtFormQuadReduce:
		return in.encodeQuadReduce(ops)
	case ExtFormShiftWide:
		return in.encodeShiftWide(ops)
	case ExtFormThreeSource:
		return in.encodeThreeSource(ops)
	case ExtFormConvert:
		return in.encodeConvert(ops)
	case ExtFormMulPred:
		return in.encodeMulPred(ops)
	case ExtFormLongMul:
		return in.encodeLongMul(ops)
	case ExtFormCompare:
		return in.encodeCompare(ops)
	case ExtFormCompareWide:
		return in.encodeCompare(ops)
	case ExtFormVLArith:
		return in.encodeVLArith(ops)
	case ExtFormVLRead:
		return in.encodeVLRead(ops)
	case ExtFormNone:
		if len(ops) != 0 {
			return nil, fmt.Errorf("%s: the %s form takes no operands, got %d",
				in.Name, in.Form, len(ops))
		}
		return extWordLE(in.Word), nil
	default:
		return nil, fmt.Errorf("%s: unknown form %d", in.Name, in.Form)
	}
}

// encodeVectors fills the unpredicated three-vector form: Zn, Zm, Zd, all
// under one required arrangement.
func (in ExtInstr) encodeVectors(ops []ExtOperand) ([]byte, error) {
	for i, op := range ops {
		if op.Kind != ExtZReg {
			return nil, fmt.Errorf("%s: operand %d wants a scalable vector register, got %s",
				in.Name, i+1, op.Kind)
		}
		if op.Reg < 0 || op.Reg > 31 {
			return nil, fmt.Errorf("%s: operand %d is Z%d, outside Z0-Z31", in.Name, i+1, op.Reg)
		}
	}
	arr, err := in.sharedArrangement(ops)
	if err != nil {
		return nil, err
	}
	size, ok := arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class", in.Name, arr)
	}
	word := in.Word
	word = extSet(word, extFieldRn, uint32(ops[0].Reg))
	word = extSet(word, extFieldRm, uint32(ops[1].Reg))
	word = extSet(word, extFieldRd, uint32(ops[2].Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodePredicated fills the governed destructive form: Zm, Pg/M, Zdn.  The
// predicate is a 3-bit field, the merging qualifier alone, and carries no
// arrangement suffix in this class.
func (in ExtInstr) encodePredicated(ops []ExtOperand) ([]byte, error) {
	zm, pg, zdn := ops[0], ops[1], ops[2]
	if zm.Kind != ExtZReg {
		return nil, fmt.Errorf("%s: operand 1 wants a scalable vector register, got %s",
			in.Name, zm.Kind)
	}
	if zm.Reg < 0 || zm.Reg > 31 {
		return nil, fmt.Errorf("%s: operand 1 is Z%d, outside Z0-Z31", in.Name, zm.Reg)
	}
	if pg.Kind != ExtPReg {
		return nil, fmt.Errorf("%s: operand 2 wants a predicate register, got %s",
			in.Name, pg.Kind)
	}
	if pg.Reg < 0 || pg.Reg > 7 {
		return nil, fmt.Errorf("%s: operand 2 is P%d, outside P0-P7 in this class", in.Name, pg.Reg)
	}
	if pg.Qual != ExtQualMerging {
		return nil, fmt.Errorf("%s: operand 2 wants the merging qualifier /M, got %q",
			in.Name, pg.Qual)
	}
	if pg.Arr != ExtArrNone {
		return nil, fmt.Errorf("%s: the governing predicate carries no arrangement suffix, got %s",
			in.Name, pg.Arr)
	}
	if zdn.Kind != ExtZReg {
		return nil, fmt.Errorf("%s: operand 3 wants a scalable vector register, got %s",
			in.Name, zdn.Kind)
	}
	if zdn.Reg < 0 || zdn.Reg > 31 {
		return nil, fmt.Errorf("%s: operand 3 is Z%d, outside Z0-Z31", in.Name, zdn.Reg)
	}
	if zm.Arr != zdn.Arr {
		return nil, fmt.Errorf("%s: operands 1 and 3 carry arrangements %s and %s, they must match",
			in.Name, zm.Arr, zdn.Arr)
	}
	size, ok := zdn.Arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class", in.Name, zdn.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldRn, uint32(zm.Reg))
	word = extSet(word, extFieldPg, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodeImmediate fills the add/subtract immediate form: imm{, LSL #8}, Zdn.
// The class encodes an unsigned imm8 with one shift bit, so a bare multiple
// of 256 derives the shift the way the GNU assembler canonicalises it.
func (in ExtInstr) encodeImmediate(ops []ExtOperand) ([]byte, error) {
	imm, zdn := ops[0], ops[1]
	imm8, sh, err := in.addSubImmediate(imm, zdn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldImm8, uint32(imm8))
	if sh != 0 {
		word = extSet(word, extFieldSh, 1)
	}
	word, err = in.setDestAndSize(word, zdn)
	if err != nil {
		return nil, err
	}
	return extWordLE(word), nil
}

// encodeSignedImmediate fills the multiply immediate form: simm8, Zdn, with
// no shift bit in the class.
func (in ExtInstr) encodeSignedImmediate(ops []ExtOperand) ([]byte, error) {
	imm, zdn := ops[0], ops[1]
	if imm.Kind != ExtImm {
		return nil, fmt.Errorf("%s: operand 1 wants an immediate, got %s", in.Name, imm.Kind)
	}
	if imm.HasShift {
		return nil, fmt.Errorf("%s: the signed immediate class takes no shift", in.Name)
	}
	if imm.Imm < -128 || imm.Imm > 127 {
		return nil, fmt.Errorf("%s: immediate %d is outside the signed 8-bit range -128..127",
			in.Name, imm.Imm)
	}
	word := in.Word
	word = extSet(word, extFieldImm8, uint32(imm.Imm))
	word, err := in.setDestAndSize(word, zdn)
	if err != nil {
		return nil, err
	}
	return extWordLE(word), nil
}

// addSubImmediate resolves the immediate operand of the add/subtract
// immediate class into its imm8 and shift bit: a spelled shift is validated
// as written, a bare multiple of 256 (on .H, .S or .D) derives one.
func (in ExtInstr) addSubImmediate(op ExtOperand, arr ExtArrangement) (imm8, sh int, err error) {
	if op.Kind != ExtImm {
		return 0, 0, fmt.Errorf("%s: operand 1 wants an immediate, got %s", in.Name, op.Kind)
	}
	switch {
	case op.HasShift:
		if op.Shift != 0 && op.Shift != 8 {
			return 0, 0, fmt.Errorf("%s: the shift amount must be 0 or 8, got %d", in.Name, op.Shift)
		}
		if arr == ExtArrB && op.Shift != 0 {
			return 0, 0, fmt.Errorf("%s: arrangement .B takes no shift", in.Name)
		}
		if op.Imm < 0 || op.Imm > 255 {
			return 0, 0, fmt.Errorf("%s: immediate %d is outside the unsigned 8-bit range 0..255",
				in.Name, op.Imm)
		}
		return int(op.Imm), op.Shift, nil
	case op.Imm >= 0 && op.Imm <= 255:
		return int(op.Imm), 0, nil
	case arr != ExtArrB && op.Imm >= 256 && op.Imm <= 255<<8 && op.Imm%256 == 0:
		// A bare multiple of 256 rides the shift bit, 65280 = 255<<8 included.
		return int(op.Imm / 256), 8, nil
	default:
		return 0, 0, fmt.Errorf("%s: immediate %d is not an unsigned imm8%s, nor a multiple of 256 the shift bit can carry",
			in.Name, op.Imm, arr.shiftNote())
	}
}

// shiftNote describes where a shifted constant is expressible, for the
// immediate range error.
func (arr ExtArrangement) shiftNote() string {
	if arr == ExtArrB {
		return " (and .B takes no shifted constant)"
	}
	return " (a multiple of 256 up to 65280 shifts)"
}

// predicateOperand validates one predicate operand: its kind, its register
// range and, when want is non-empty, the one arrangement the class takes.
func (in ExtInstr) predicateOperand(op ExtOperand, position int, lo, hi int, want ExtArrangement) error {
	if op.Kind != ExtPReg {
		return fmt.Errorf("%s: operand %d wants a predicate register, got %s",
			in.Name, position, op.Kind)
	}
	if op.Reg < lo || op.Reg > hi {
		return fmt.Errorf("%s: operand %d is P%d, outside P%d-P%d in this class",
			in.Name, position, op.Reg, lo, hi)
	}
	if want != ExtArrNone && op.Arr != want {
		return fmt.Errorf("%s: operand %d carries arrangement %s, want %s",
			in.Name, position, op.Arr, want)
	}
	return nil
}

// encodePredicateLogical fills the four-operand predicate logical form:
// Pm.B, Pn.B, Pg{qualifier}, Pd.B.  Pm takes P0-P7, Pn and Pd P0-P15; the
// governing predicate takes P0-P7 and its qualifier is zeroing for the
// logical operations and bare for PSEL, which the form distinguishes.
func (in ExtInstr) encodePredicateLogical(ops []ExtOperand) ([]byte, error) {
	pm, pn, pg, pd := ops[0], ops[1], ops[2], ops[3]
	if err := in.predicateOperand(pm, 1, 0, 7, ExtArrB); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pn, 2, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	// The governing predicate carries its qualifier in place of an
	// arrangement (P1.Z), so the form judges the qualifier below.
	if err := in.predicateOperand(pg, 3, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Arr != ExtArrNone {
		return nil, fmt.Errorf("%s: the governing predicate carries no arrangement suffix, got %s",
			in.Name, pg.Arr)
	}
	if err := in.predicateOperand(pd, 4, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	wantQual := ExtQualZeroing
	if in.Form == ExtFormPredicateSelect {
		wantQual = ExtQualNone
	}
	if pg.Qual != wantQual {
		if wantQual == ExtQualNone {
			return nil, fmt.Errorf("%s: operand 3 takes no qualifier, got %q",
				in.Name, pg.Qual)
		}
		return nil, fmt.Errorf("%s: operand 3 wants the zeroing qualifier, got %q",
			in.Name, pg.Qual)
	}
	word := in.Word
	word = extSet(word, extFieldPm, uint32(pm.Reg))
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	return extWordLE(word), nil
}

// encodePredicateLogicalDest fills the break form whose first operand is the
// destination read back: Pdm.B, Pn.B, Pg/Z, Pdm.B.  The encoding carries the
// register once, so operands 1 and 4 must name the same register.
func (in ExtInstr) encodePredicateLogicalDest(ops []ExtOperand) ([]byte, error) {
	pdm, pn, pg := ops[0], ops[1], ops[2]
	if err := in.predicateOperand(pdm, 1, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pn, 2, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pg, 3, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Arr != ExtArrNone {
		return nil, fmt.Errorf("%s: the governing predicate carries no arrangement suffix, got %s",
			in.Name, pg.Arr)
	}
	if err := in.predicateOperand(ops[3], 4, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	if pg.Qual != ExtQualZeroing {
		return nil, fmt.Errorf("%s: operand 3 wants the zeroing qualifier, got %q",
			in.Name, pg.Qual)
	}
	if ops[3].Reg != pdm.Reg {
		return nil, fmt.Errorf("%s: operands 1 and 4 are the same register Pdm, got P%d and P%d",
			in.Name, pdm.Reg, ops[3].Reg)
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldPd, uint32(pdm.Reg))
	return extWordLE(word), nil
}

// encodePredicateBreak fills the three-operand break form: Pn.B, Pg{qual},
// Pd.B.  The governing predicate is the wide four-bit field (P0-P15); the
// plain break accepts the merging or the zeroing qualifier, the S variant
// the zeroing alone.
func (in ExtInstr) encodePredicateBreak(ops []ExtOperand) ([]byte, error) {
	pn, pg, pd := ops[0], ops[1], ops[2]
	if err := in.predicateOperand(pn, 1, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pg, 2, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pd, 3, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	switch {
	case pg.Qual == ExtQualZeroing:
	case pg.Qual == ExtQualMerging && in.Form == ExtFormPredicateBreak:
	default:
		return nil, fmt.Errorf("%s: operand 2 wants the zeroing qualifier%s, got %q",
			in.Name, mergingNote(in.Form), pg.Qual)
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPgW, uint32(pg.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	return extWordLE(word), nil
}

// mergingNote describes the qualifier rule of a break form, for the error.
func mergingNote(f ExtForm) string {
	if f == ExtFormPredicateBreak {
		return " or the merging qualifier"
	}
	return ""
}

// encodePredicatePermute fills the predicate permutation form: Pm.T, Pn.T,
// Pd.T under one shared arrangement, which feeds the size field.
func (in ExtInstr) encodePredicatePermute(ops []ExtOperand) ([]byte, error) {
	pm, pn, pd := ops[0], ops[1], ops[2]
	if err := in.predicateOperand(pm, 1, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pn, 2, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pd, 3, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	size, err := in.sharedSize(pm.Arr, pn.Arr, pd.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPm, uint32(pm.Reg))
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodePredicateReadBack fills the destination-read-back forms of PFIRST
// and PNEXT: Pdn{.B or .T}, Pg or Pv (bare), Pdn.  Operands 1 and 3 name the
// same register; PNEXT carries the size field, PFIRST is .B alone.
func (in ExtInstr) encodePredicateReadBack(ops []ExtOperand) ([]byte, error) {
	pdn, pg := ops[0], ops[1]
	if err := in.predicateOperand(pdn, 1, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pg, 2, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(ops[2], 3, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Arr != ExtArrNone {
		return nil, fmt.Errorf("%s: operand 2 carries no arrangement suffix, got %s",
			in.Name, pg.Arr)
	}
	if pg.Qual != ExtQualNone {
		return nil, fmt.Errorf("%s: operand 2 takes no qualifier, got %q", in.Name, pg.Qual)
	}
	if ops[2].Reg != pdn.Reg || ops[2].Arr != pdn.Arr {
		return nil, fmt.Errorf("%s: operands 1 and 3 are the same register Pdn, got P%d and P%d",
			in.Name, pdn.Reg, ops[2].Reg)
	}
	var size uint32
	if in.Form == ExtFormPredicateNext {
		var ok bool
		size, ok = pdn.Arr.sizeBits()
		if !ok {
			return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
				in.Name, pdn.Arr)
		}
	} else if pdn.Arr != ExtArrB {
		return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .B",
			in.Name, pdn.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pg.Reg))
	word = extSet(word, extFieldPd, uint32(pdn.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodePredicateOne fills the single-predicate form: Pd.B, destination in
// the four-bit field.
func (in ExtInstr) encodePredicateOne(ops []ExtOperand) ([]byte, error) {
	if err := in.predicateOperand(ops[0], 1, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	word := extSet(in.Word, extFieldPd, uint32(ops[0].Reg))
	return extWordLE(word), nil
}

// encodePredicateWrite fills WRFFR's single-source form: Pn.B in the
// five-bit source slot.
func (in ExtInstr) encodePredicateWrite(ops []ExtOperand) ([]byte, error) {
	if err := in.predicateOperand(ops[0], 1, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	word := extSet(in.Word, extFieldPn, uint32(ops[0].Reg))
	return extWordLE(word), nil
}

// encodePredicateFFRRead fills the predicated first-fault read: Pg/Z, Pd.B.
// The first operand is the mask the read passes through, so it sits in the
// five-bit source slot, not in a governing-predicate field.
func (in ExtInstr) encodePredicateFFRRead(ops []ExtOperand) ([]byte, error) {
	pg, pd := ops[0], ops[1]
	if err := in.predicateOperand(pg, 1, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pd, 2, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	if pg.Qual != ExtQualZeroing {
		return nil, fmt.Errorf("%s: operand 1 wants the zeroing qualifier, got %q",
			in.Name, pg.Qual)
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pg.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	return extWordLE(word), nil
}

// encodePredicateMove fills the predicate reverse: Pn.T, Pd.T under one
// shared arrangement.
func (in ExtInstr) encodePredicateMove(ops []ExtOperand) ([]byte, error) {
	pn, pd := ops[0], ops[1]
	if err := in.predicateOperand(pn, 1, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pd, 2, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	size, err := in.sharedSize(pn.Arr, pd.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodePredicateUnpack fills the predicate unpack: Pn.B, Pd.H, both
// arrangements fixed by the class.
func (in ExtInstr) encodePredicateUnpack(ops []ExtOperand) ([]byte, error) {
	pn, pd := ops[0], ops[1]
	if err := in.predicateOperand(pn, 1, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pd, 2, 0, 15, ExtArrH); err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	return extWordLE(word), nil
}

// encodePredicateTest fills PTEST: Pn.B, Pg (bare), no destination.
func (in ExtInstr) encodePredicateTest(ops []ExtOperand) ([]byte, error) {
	pn, pg := ops[0], ops[1]
	if err := in.predicateOperand(pn, 1, 0, 15, ExtArrB); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pg, 2, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Qual != ExtQualNone {
		return nil, fmt.Errorf("%s: operand 2 takes no qualifier, got %q", in.Name, pg.Qual)
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPgW, uint32(pg.Reg))
	return extWordLE(word), nil
}

// encodeWhile fills the while-compare form: Rm, Rn, Pd.T, the arrangement
// feeding the size field.  The general registers run R0-R30; the class takes
// no stack pointer and no zero register spelling.
func (in ExtInstr) encodeWhile(ops []ExtOperand) ([]byte, error) {
	rm, rn, pd := ops[0], ops[1], ops[2]
	for i, op := range []ExtOperand{rm, rn} {
		if op.Kind != ExtGReg {
			return nil, fmt.Errorf("%s: operand %d wants a general register, got %s",
				in.Name, i+1, op.Kind)
		}
		if op.Reg < 0 || op.Reg > 30 {
			return nil, fmt.Errorf("%s: operand %d is R%d, outside R0-R30",
				in.Name, i+1, op.Reg)
		}
	}
	if err := in.predicateOperand(pd, 3, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	size, ok := pd.Arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, pd.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(rm.Reg))
	word = extSet(word, extFieldPn, uint32(rn.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodePredicateCounter fills PTRUE's counter form: PNd.T, the
// predicate-as-counter destination spelled PN8-PN15 and encoded as reg-8.
func (in ExtInstr) encodePredicateCounter(ops []ExtOperand) ([]byte, error) {
	pnd := ops[0]
	if pnd.Kind != ExtPNReg {
		return nil, fmt.Errorf("%s: operand 1 wants a predicate-as-counter register, got %s",
			in.Name, pnd.Kind)
	}
	if pnd.Reg < 8 || pnd.Reg > 15 {
		return nil, fmt.Errorf("%s: operand 1 is PN%d, outside PN8-PN15", in.Name, pnd.Reg)
	}
	size, ok := pnd.Arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, pnd.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldPnc, uint32(pnd.Reg-8))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// zVector validates one Z operand for the Z-alias classes: kind, range and
// the row's arrangement rule, shared when in.Arr is none, fixed otherwise.
func (in ExtInstr) zVector(op ExtOperand, position int) error {
	if op.Kind != ExtZReg {
		return fmt.Errorf("%s: operand %d wants a scalable vector register, got %s",
			in.Name, position, op.Kind)
	}
	if op.Reg < 0 || op.Reg > 31 {
		return fmt.Errorf("%s: operand %d is Z%d, outside Z0-Z31", in.Name, position, op.Reg)
	}
	if in.Arr != ExtArrNone {
		if op.Arr != in.Arr {
			return fmt.Errorf("%s: operand %d carries arrangement %s, want %s",
				in.Name, position, op.Arr, in.Arr)
		}
	} else if op.Arr == ExtArrNone {
		return fmt.Errorf("%s: operand %d carries no arrangement suffix", in.Name, position)
	}
	return nil
}

// zBare validates a Z operand that must carry no suffix at all (the bare
// MOVPRFX spelling).
func (in ExtInstr) zBare(op ExtOperand, position int) error {
	if op.Kind != ExtZReg {
		return fmt.Errorf("%s: operand %d wants a scalable vector register, got %s",
			in.Name, position, op.Kind)
	}
	if op.Reg < 0 || op.Reg > 31 {
		return fmt.Errorf("%s: operand %d is Z%d, outside Z0-Z31", in.Name, position, op.Reg)
	}
	if op.Arr != ExtArrNone {
		return fmt.Errorf("%s: operand %d takes no arrangement suffix, got %s",
			in.Name, position, op.Arr)
	}
	return nil
}

// zGov validates the bare governing predicate of the Z-alias forms: a
// wide four-bit predicate (P0-P15, the field at bits 13..10 that the
// ZSEL corpus line pins) with no suffix.
func (in ExtInstr) zGov(op ExtOperand, position int) error {
	if op.Kind != ExtPReg {
		return fmt.Errorf("%s: operand %d wants a predicate register, got %s",
			in.Name, position, op.Kind)
	}
	if op.Reg < 0 || op.Reg > 15 {
		return fmt.Errorf("%s: operand %d is P%d, outside P0-P15 in this class",
			in.Name, position, op.Reg)
	}
	if op.Arr != ExtArrNone || op.Qual != ExtQualNone {
		return fmt.Errorf("%s: operand %d takes no suffix, got %s%s",
			in.Name, position, op.Arr, op.Qual)
	}
	return nil
}

// zSize returns the size encoding for a Z-alias arrangement: the shared
// arrangement when the row locks none, else nothing (the fixed arrangement
// rides the word's own bits).
func (in ExtInstr) zSize(arrs ...ExtArrangement) (uint32, error) {
	if in.Arr != ExtArrNone {
		return 0, nil
	}
	return in.sharedSize(arrs...)
}

// encodeZUnary fills the Z-alias unary predicated form: Zn.T, Pg{qual},
// Zd.T.  The row's PgQual says which qualifier the governing predicate
// takes; the arrangement is shared, or fixed where the row locks one.
func (in ExtInstr) encodeZUnary(ops []ExtOperand) ([]byte, error) {
	pn, pg, pd := ops[0], ops[1], ops[2]
	if err := in.zVector(pn, 1); err != nil {
		return nil, err
	}
	if err := in.zVector(pd, 3); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pg, 2, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Arr != ExtArrNone {
		return nil, fmt.Errorf("%s: the governing predicate carries no arrangement suffix, got %s",
			in.Name, pg.Arr)
	}
	switch {
	case pg.Qual == in.PgQual:
	case in.PgQual == ExtQualAny && (pg.Qual == ExtQualMerging || pg.Qual == ExtQualZeroing):
	default:
		if in.PgQual == ExtQualAny {
			return nil, fmt.Errorf("%s: operand 2 wants the merging or zeroing qualifier, got %q",
				in.Name, pg.Qual)
		}
		return nil, fmt.Errorf("%s: operand 2 wants the %s qualifier, got %q",
			in.Name, in.PgQual, pg.Qual)
	}
	size, err := in.zSize(pn.Arr, pd.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(pd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZPredicatedSource fills the Z-alias binary predicated form: Zm.T,
// Zdn.T, Pg/M, Zdn.T, the source copy spelled and equal to the destination.
// Zm rides the first-source slot at bits 9..5 and Zdn the destination slot;
// bits 16..20 carry the class opcode and stay clear of operands.
func (in ExtInstr) encodeZPredicatedSource(ops []ExtOperand) ([]byte, error) {
	zm, zdn, pg := ops[0], ops[1], ops[2]
	if err := in.zVector(zm, 1); err != nil {
		return nil, err
	}
	if err := in.zVector(zdn, 2); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pg, 3, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Arr != ExtArrNone {
		return nil, fmt.Errorf("%s: the governing predicate carries no arrangement suffix, got %s",
			in.Name, pg.Arr)
	}
	if err := in.zVector(ops[3], 4); err != nil {
		return nil, err
	}
	if want := in.PgQual; pg.Qual != want {
		return nil, fmt.Errorf("%s: operand 3 wants the %s qualifier, got %q",
			in.Name, want.String(), pg.Qual)
	}
	if ops[3].Reg != zdn.Reg || ops[3].Arr != zdn.Arr {
		return nil, fmt.Errorf("%s: operands 2 and 4 are the same register Zdn, got Z%d and Z%d",
			in.Name, zdn.Reg, ops[3].Reg)
	}
	size, err := in.zSize(zm.Arr, zdn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldRn, uint32(zm.Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZImmediateSource fills the Z-alias immediate form: imm{, LSL #8},
// Zdn.T, Zdn.T, the register encoded once from the repeated spelling.
func (in ExtInstr) encodeZImmediateSource(ops []ExtOperand) ([]byte, error) {
	imm, zdn := ops[0], ops[1]
	if imm.Kind != ExtImm {
		return nil, fmt.Errorf("%s: operand 1 wants an immediate, got %s", in.Name, imm.Kind)
	}
	if err := in.zVector(zdn, 2); err != nil {
		return nil, err
	}
	if err := in.zVector(ops[2], 3); err != nil {
		return nil, err
	}
	if ops[2].Reg != zdn.Reg || ops[2].Arr != zdn.Arr {
		return nil, fmt.Errorf("%s: operands 2 and 3 are the same register Zdn, got Z%d and Z%d",
			in.Name, zdn.Reg, ops[2].Reg)
	}
	imm8, sh, err := in.addSubImmediate(imm, zdn.Arr)
	if err != nil {
		return nil, err
	}
	size, err := in.zSize(zdn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldImm8, uint32(imm8))
	if sh != 0 {
		word = extSet(word, extFieldSh, 1)
	}
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZSelect fills the vector select: Zm.T, Zn.T, Pv, Zd.T.
func (in ExtInstr) encodeZSelect(ops []ExtOperand) ([]byte, error) {
	zm, zn, pv, zd := ops[0], ops[1], ops[2], ops[3]
	if err := in.zVector(zm, 1); err != nil {
		return nil, err
	}
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if err := in.zVector(zd, 4); err != nil {
		return nil, err
	}
	if err := in.zGov(pv, 3); err != nil {
		return nil, err
	}
	size, err := in.zSize(zm.Arr, zn.Arr, zd.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(zm.Reg))
	word = extSet(word, extFieldPn, uint32(zn.Reg))
	word = extSet(word, extFieldPgW, uint32(pv.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZGov fills the governed compact/expand: Zn.T, Pg, Zd.T.
func (in ExtInstr) encodeZGov(ops []ExtOperand) ([]byte, error) {
	pn, pg, zd := ops[0], ops[1], ops[2]
	if err := in.zVector(pn, 1); err != nil {
		return nil, err
	}
	if err := in.zVector(zd, 3); err != nil {
		return nil, err
	}
	if err := in.zGov(pg, 2); err != nil {
		return nil, err
	}
	size, err := in.zSize(pn.Arr, zd.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPgW, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZMove fills the vector reverse: Zn.T, Zd.T, one shared arrangement.
func (in ExtInstr) encodeZMove(ops []ExtOperand) ([]byte, error) {
	pn, zd := ops[0], ops[1]
	if err := in.zVector(pn, 1); err != nil {
		return nil, err
	}
	if err := in.zVector(zd, 2); err != nil {
		return nil, err
	}
	size, err := in.zSize(pn.Arr, zd.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZMoveBare fills MOVPRFX's arrangement-less spelling: Zn, Zd.
func (in ExtInstr) encodeZMoveBare(ops []ExtOperand) ([]byte, error) {
	if err := in.zBare(ops[0], 1); err != nil {
		return nil, err
	}
	if err := in.zBare(ops[1], 2); err != nil {
		return nil, err
	}
	word := extSet(in.Word, extFieldPn, uint32(ops[0].Reg))
	word = extSet(word, extFieldRd, uint32(ops[1].Reg))
	return extWordLE(word), nil
}

// encodeVectorsZm fills the Z-alias three-vector form whose spelled order
// starts with Zm: ZADD Z7.D, Z23.D, Z13.D puts Zm in the second-source
// slot, Zn in the first-source slot and Zd in the destination.  Rows with
// a fixed arrangement validate it and leave the size bits to the word.
func (in ExtInstr) encodeVectorsZm(ops []ExtOperand) ([]byte, error) {
	for i, op := range ops {
		if err := in.zVector(op, i+1); err != nil {
			return nil, err
		}
	}
	var size uint32
	if in.Arr == ExtArrNone {
		var err error
		size, err = in.sharedSize(ops[0].Arr, ops[1].Arr, ops[2].Arr)
		if err != nil {
			return nil, err
		}
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(ops[0].Reg))
	word = extSet(word, extFieldRn, uint32(ops[1].Reg))
	word = extSet(word, extFieldRd, uint32(ops[2].Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZUnpack fills the vector unpack: Zn.B, Zd.T, the size field
// riding the destination's arrangement.
func (in ExtInstr) encodeZUnpack(ops []ExtOperand) ([]byte, error) {
	pn, zd := ops[0], ops[1]
	if pn.Kind != ExtZReg {
		return nil, fmt.Errorf("%s: operand 1 wants a scalable vector register, got %s",
			in.Name, pn.Kind)
	}
	if pn.Reg < 0 || pn.Reg > 31 {
		return nil, fmt.Errorf("%s: operand 1 is Z%d, outside Z0-Z31", in.Name, pn.Reg)
	}
	if pn.Arr != ExtArrB {
		return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .B", in.Name, pn.Arr)
	}
	if err := in.zVector(zd, 2); err != nil {
		return nil, err
	}
	size, err := in.zSize(zd.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZFromGeneral fills the general-into-vector forms, ZDUP and ZINSR:
// R, Zd.T with the arrangement locked by the row.
func (in ExtInstr) encodeZFromGeneral(ops []ExtOperand) ([]byte, error) {
	rn, zd := ops[0], ops[1]
	if rn.Kind != ExtGReg {
		return nil, fmt.Errorf("%s: operand 1 wants a general register, got %s", in.Name, rn.Kind)
	}
	if rn.Reg < 0 || rn.Reg > 30 {
		return nil, fmt.Errorf("%s: operand 1 is R%d, outside R0-R30", in.Name, rn.Reg)
	}
	if err := in.zVector(zd, 2); err != nil {
		return nil, err
	}
	word := extSet(in.Word, extFieldPn, uint32(rn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	return extWordLE(word), nil
}

// encodeZLastReg fills the last-active-element to register: Zn.T, Pg, R.
func (in ExtInstr) encodeZLastReg(ops []ExtOperand) ([]byte, error) {
	pn, pg, rd := ops[0], ops[1], ops[2]
	if err := in.zVector(pn, 1); err != nil {
		return nil, err
	}
	if err := in.zGov(pg, 2); err != nil {
		return nil, err
	}
	if rd.Kind != ExtGReg {
		return nil, fmt.Errorf("%s: operand 3 wants a general register, got %s", in.Name, rd.Kind)
	}
	if rd.Reg < 0 || rd.Reg > 30 {
		return nil, fmt.Errorf("%s: operand 3 is R%d, outside R0-R30", in.Name, rd.Reg)
	}
	size, err := in.zSize(pn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(pn.Reg))
	word = extSet(word, extFieldPgW, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(rd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeZReadBack fills the SVE2 crypto form whose written order spells the
// destination twice: Zn.T, Zd.T, Zd.T (SM4E, AESD, AESE).  The row's
// arrangement is locked into the word; operands 2 and 3 name the same
// register and the encoding carries it once.
func (in ExtInstr) encodeZReadBack(ops []ExtOperand) ([]byte, error) {
	zn := ops[0]
	if err := in.zVector(zn, 1); err != nil {
		return nil, err
	}
	if err := in.zVector(ops[1], 2); err != nil {
		return nil, err
	}
	if err := in.zVector(ops[2], 3); err != nil {
		return nil, err
	}
	if ops[2].Reg != ops[1].Reg || ops[2].Arr != ops[1].Arr {
		return nil, fmt.Errorf("%s: operands 2 and 3 are the same register Zd, got Z%d and Z%d",
			in.Name, ops[1].Reg, ops[2].Reg)
	}
	word := in.Word
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(ops[1].Reg))
	return extWordLE(word), nil
}

// encodeZSameReg fills the in-place SVE2 AES form: Zd.T, Zd.T (AESIMC,
// AESMC), the register encoded once in the destination slot.
func (in ExtInstr) encodeZSameReg(ops []ExtOperand) ([]byte, error) {
	if err := in.zVector(ops[0], 1); err != nil {
		return nil, err
	}
	if err := in.zVector(ops[1], 2); err != nil {
		return nil, err
	}
	if ops[1].Reg != ops[0].Reg || ops[1].Arr != ops[0].Arr {
		return nil, fmt.Errorf("%s: operands 1 and 2 are the same register Zd, got Z%d and Z%d",
			in.Name, ops[0].Reg, ops[1].Reg)
	}
	return extWordLE(extSet(in.Word, extFieldRd, uint32(ops[0].Reg))), nil
}

// reg31Name spells how the thirty-first general-register slot was written.
func reg31Name(r uint8) string {
	switch r {
	case 1:
		return "ZR"
	case 2:
		return "RSP"
	default:
		return ""
	}
}

// generalOperand validates a general-register operand: R0-R30, or ZR or RSP
// where allow31 names the one spelling of the thirty-first slot the class
// takes.  A register outside the range is an error, never a wrap.
func (in ExtInstr) generalOperand(op ExtOperand, position int, allow31 uint8) error {
	if op.Kind != ExtGReg {
		return fmt.Errorf("%s: operand %d wants a general register, got %s",
			in.Name, position, op.Kind)
	}
	if op.Reg31 == 0 {
		if op.Reg < 0 || op.Reg > 30 {
			return fmt.Errorf("%s: operand %d is R%d, outside R0-R30",
				in.Name, position, op.Reg)
		}
		return nil
	}
	if op.Reg31 != allow31 {
		return fmt.Errorf("%s: operand %d wants %s here, got %s",
			in.Name, position, reg31Name(allow31), reg31Name(op.Reg31))
	}
	return nil
}

// encodeCTerm fills the SVE2 loop terminator: Rm, Rn, both in the standard
// five-bit slots, the zero register allowed in either.
func (in ExtInstr) encodeCTerm(ops []ExtOperand) ([]byte, error) {
	for i, op := range ops {
		if err := in.generalOperand(op, i+1, 1); err != nil {
			return nil, err
		}
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(ops[0].Reg))
	word = extSet(word, extFieldRn, uint32(ops[1].Reg))
	return extWordLE(word), nil
}

// barePredicate validates a governing predicate of the counter and reduction
// classes: a plain P0-P15 with no suffix and no qualifier, the spelling the
// corpus writes between the source and the destination.
func (in ExtInstr) barePredicate(op ExtOperand, position, lo, hi int) error {
	if err := in.predicateOperand(op, position, lo, hi, ExtArrNone); err != nil {
		return err
	}
	if op.Arr != ExtArrNone {
		return fmt.Errorf("%s: operand %d carries no arrangement suffix, got %s",
			in.Name, position, op.Arr)
	}
	if op.Qual != ExtQualNone {
		return fmt.Errorf("%s: operand %d takes no qualifier, got %q",
			in.Name, position, op.Qual)
	}
	return nil
}

// encodeCountP fills the count form: Pn.T, Pg (bare), Rd.  The arrangement
// feeds the size field, Pg occupies the wide four-bit field and Pn the
// five-bit source slot.
func (in ExtInstr) encodeCountP(ops []ExtOperand) ([]byte, error) {
	pn, pg, rd := ops[0], ops[1], ops[2]
	if err := in.predicateOperand(pn, 1, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.barePredicate(pg, 2, 0, 15); err != nil {
		return nil, err
	}
	if err := in.generalOperand(rd, 3, 1); err != nil {
		return nil, err
	}
	size, ok := pn.Arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, pn.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldPgW, uint32(pg.Reg))
	word = extSet(word, extFieldRn, uint32(pn.Reg))
	word = extSet(word, extFieldRd, uint32(rd.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodeCountPn fills the predicate-counter step whose scalar result the
// class drops: Pn.T, ZR.  The predicate occupies the four-bit field at bits
// 8..5 and its arrangement feeds the size field; the second operand is the
// zero register, the spelling that discards the count.
func (in ExtInstr) encodeCountPn(ops []ExtOperand) ([]byte, error) {
	pn, rd := ops[0], ops[1]
	if err := in.predicateOperand(pn, 1, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	// The scalar result of this class is architecturally dropped, and the
	// spelling that says so is the zero register alone: a plain R0-R30 has
	// no meaning here.
	if rd.Kind != ExtGReg || rd.Reg31 != 1 {
		return nil, fmt.Errorf("%s: operand 2 is the dropped scalar result, spelled ZR, got a %s", in.Name, rd.Kind)
	}
	size, ok := pn.Arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, pn.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldPn4, uint32(pn.Reg))
	word = extSet(word, extFieldRd, uint32(rd.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodeCountPnVec fills the predicate-counter step on a vector: Pm.T,
// Zdn.T, the vector decremented in place by the predicate's active element
// count.  The predicate occupies the four-bit field at bits 8..5, the
// vector the destination slot, and the predicate's arrangement feeds the
// size field.
func (in ExtInstr) encodeCountPnVec(ops []ExtOperand) ([]byte, error) {
	pm, zdn := ops[0], ops[1]
	if err := in.predicateOperand(pm, 1, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.zVector(zdn, 2); err != nil {
		return nil, err
	}
	size, ok := pm.Arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, pm.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldPn4, uint32(pm.Reg))
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// shiftImmAmount validates the immediate shift operand against the closed
// range lo..hi and refuses the LSL spelling, which belongs to the
// immediate-constant classes and not to the shift-immediate ones.
func (in ExtInstr) shiftImmAmount(op ExtOperand, position, lo, hi int) (int, error) {
	if op.Kind != ExtImm {
		return 0, fmt.Errorf("%s: operand %d wants an immediate, got %s", in.Name, position, op.Kind)
	}
	if op.HasShift {
		return 0, fmt.Errorf("%s: the shift-immediate class takes no LSL shift", in.Name)
	}
	v := int(op.Imm)
	if v < lo || v > hi {
		return 0, fmt.Errorf("%s: shift amount %d is outside the range %d..%d in this class",
			in.Name, v, lo, hi)
	}
	return v, nil
}

// encodeShiftImmPred fills the predicated left shift by immediate: imm,
// Zdn.T, Pg/M, Zdn.T, the destination spelled twice and encoded once.
func (in ExtInstr) encodeShiftImmPred(ops []ExtOperand) ([]byte, error) {
	return in.encodeShiftImmPredC(ops, func(esize, v int) int { return esize + v })
}

// encodeShiftImmPredRight fills the predicated right shift by immediate,
// the right-shift counterpart of the predicated left shifts.
func (in ExtInstr) encodeShiftImmPredRight(ops []ExtOperand) ([]byte, error) {
	return in.encodeShiftImmPredC(ops, func(esize, v int) int { return 2*esize - v })
}

// encodeShiftImmPredC carries the predicated shift-by-immediate layout the
// left and right shifts share: the amount rides the class's tsz:imm3
// fields, C = dir(esize, amount), split imm3 into bits 7..5, the low tsz
// pair into bits 9..8 and the top tsz pair into bits 23..22, where the tsz
// bits spell the arrangement and stand in for the size field the class
// does not carry.
func (in ExtInstr) encodeShiftImmPredC(ops []ExtOperand, dir func(esize, v int) int) ([]byte, error) {
	imm, zdn, pg, zdn2 := ops[0], ops[1], ops[2], ops[3]
	if err := in.zVector(zdn, 2); err != nil {
		return nil, err
	}
	if _, ok := zdn.Arr.sizeBits(); !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, zdn.Arr)
	}
	esize := zdn.Arr.elemBits()
	v, err := in.shiftImmAmount(imm, 1, 1, esize-1)
	if err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pg, 3, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Qual != ExtQualMerging {
		return nil, fmt.Errorf("%s: operand 3 wants the merging qualifier /M, got %q",
			in.Name, pg.Qual)
	}
	if err := in.zVector(zdn2, 4); err != nil {
		return nil, err
	}
	if zdn2.Reg != zdn.Reg || zdn2.Arr != zdn.Arr {
		return nil, fmt.Errorf("%s: operands 2 and 4 are the same register Zdn, got Z%d and Z%d",
			in.Name, zdn.Reg, zdn2.Reg)
	}
	c := dir(esize, v)
	word := in.Word
	word = extSet(word, extFieldImm3T5, uint32(c))
	word = extSet(word, extFieldTszM8, uint32(c>>3))
	word = extSet(word, extFieldTszH22W, uint32(c>>5))
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	word = extSet(word, extFieldPgW, uint32(pg.Reg))
	return extWordLE(word), nil
}

// setShiftImmTsz16 ORs the three-vector tsz:imm3 chunks of c into the
// word: imm3 into bits 18..16, the low tsz pair into bits 20..19 and the
// top tsz pair into bits 23..22.
func setShiftImmTsz16(word uint32, c int) uint32 {
	word = extSet(word, extFieldImm3T16, uint32(c))
	word = extSet(word, extFieldTszM19, uint32(c>>3))
	word = extSet(word, extFieldTszH22W, uint32(c>>5))
	return word
}

// encodeShiftImmSame fills the same-size shift by immediate: imm, Zn.T,
// Zd.T, a right shift within one shared arrangement, the destination (or
// the read-modify-write accumulator) in the destination slot.  C = 2 x
// esize - amount over the shared element size.
func (in ExtInstr) encodeShiftImmSame(ops []ExtOperand) ([]byte, error) {
	imm, zn, zd := ops[0], ops[1], ops[2]
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if _, ok := zn.Arr.sizeBits(); !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, zn.Arr)
	}
	if err := in.zVector(zd, 3); err != nil {
		return nil, err
	}
	if zd.Arr != zn.Arr {
		return nil, fmt.Errorf("%s: operands 2 and 3 carry arrangements %s and %s, they must match",
			in.Name, zn.Arr, zd.Arr)
	}
	esize := zn.Arr.elemBits()
	v, err := in.shiftImmAmount(imm, 1, 1, esize-1)
	if err != nil {
		return nil, err
	}
	c := 2*esize - v
	word := setShiftImmTsz16(in.Word, c)
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	return extWordLE(word), nil
}

// encodeShiftImmXar fills the three-source extract and narrow: imm, Zm.T,
// Zdn.T, Zdn.T, the destination spelled twice and encoded once.  C = 2 x
// esize - amount over the shared element size.
func (in ExtInstr) encodeShiftImmXar(ops []ExtOperand) ([]byte, error) {
	imm, zm, zdn, zdn2 := ops[0], ops[1], ops[2], ops[3]
	if err := in.zVector(zm, 2); err != nil {
		return nil, err
	}
	if _, ok := zm.Arr.sizeBits(); !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, zm.Arr)
	}
	if err := in.zVector(zdn, 3); err != nil {
		return nil, err
	}
	if err := in.zVector(zdn2, 4); err != nil {
		return nil, err
	}
	if zdn2.Reg != zdn.Reg || zdn2.Arr != zdn.Arr {
		return nil, fmt.Errorf("%s: operands 3 and 4 are the same register Zdn, got Z%d and Z%d",
			in.Name, zdn.Reg, zdn2.Reg)
	}
	if zdn.Arr != zm.Arr {
		return nil, fmt.Errorf("%s: operands 2 and 3 carry arrangements %s and %s, they must match",
			in.Name, zm.Arr, zdn.Arr)
	}
	esize := zm.Arr.elemBits()
	v, err := in.shiftImmAmount(imm, 1, 1, esize-1)
	if err != nil {
		return nil, err
	}
	c := 2*esize - v
	word := setShiftImmTsz16(in.Word, c)
	word = extSet(word, extFieldRn, uint32(zm.Reg))
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	return extWordLE(word), nil
}

// encodeShiftImmNarrow fills the three-vector narrowing shift by immediate:
// imm, Zn.Tb, Zd.T, a right shift of the wide source whose result the
// destination one element step down keeps (.H+.B, .S+.H, .D+.S).  The
// amount runs 1..esize over the destination's element size and C = 2 x
// esize - amount, split imm3 into bits 18..16, the low tsz pair into bits
// 20..19 and the top tsz bit into bit 22.
func (in ExtInstr) encodeShiftImmNarrow(ops []ExtOperand) ([]byte, error) {
	imm, zn, zd := ops[0], ops[1], ops[2]
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if zn.Arr < ExtArrH || zn.Arr > ExtArrD {
		return nil, fmt.Errorf("%s: operand 2 carries arrangement %s, want .H, .S or .D", in.Name, zn.Arr)
	}
	if err := in.zVector(zd, 3); err != nil {
		return nil, err
	}
	if zd.Arr != zn.Arr-1 {
		return nil, fmt.Errorf("%s: operand 3 carries arrangement %s, want one element step below %s",
			in.Name, zd.Arr, zn.Arr)
	}
	esize := zd.Arr.elemBits()
	v, err := in.shiftImmAmount(imm, 1, 1, esize)
	if err != nil {
		return nil, err
	}
	c := 2*esize - v
	word := in.Word
	word = extSet(word, extFieldImm3T16, uint32(c))
	word = extSet(word, extFieldTszM19, uint32(c>>3))
	word = extSet(word, extFieldTszH22, uint32(c>>5))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	return extWordLE(word), nil
}

// encodeShiftImmWide fills the three-vector widening shift by immediate:
// imm, Zn.Tb, Zd.T, a left shift of the narrow source into a destination
// one element step up (.B+.H, .H+.S, .S+.D).  The amount runs
// 0..esize-1 over the source's element size and C = esize + amount, split
// like the narrowing class.
func (in ExtInstr) encodeShiftImmWide(ops []ExtOperand) ([]byte, error) {
	imm, zn, zd := ops[0], ops[1], ops[2]
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if zn.Arr < ExtArrB || zn.Arr > ExtArrS {
		return nil, fmt.Errorf("%s: operand 2 carries arrangement %s, want .B, .H or .S", in.Name, zn.Arr)
	}
	if err := in.zVector(zd, 3); err != nil {
		return nil, err
	}
	if zd.Arr != zn.Arr+1 {
		return nil, fmt.Errorf("%s: operand 3 carries arrangement %s, want one element step above %s",
			in.Name, zd.Arr, zn.Arr)
	}
	esize := zn.Arr.elemBits()
	v, err := in.shiftImmAmount(imm, 1, 0, esize-1)
	if err != nil {
		return nil, err
	}
	c := esize + v
	word := in.Word
	word = extSet(word, extFieldImm3T16, uint32(c))
	word = extSet(word, extFieldTszM19, uint32(c>>3))
	word = extSet(word, extFieldTszH22, uint32(c>>5))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	return extWordLE(word), nil
}

// encodeCountPnW fills the predicate-counter step with a scalar result:
// Rd, Pn.T, Rd, the destination spelled twice.  The predicate occupies the
// four-bit field at bits 8..5 and its arrangement feeds the size field.
func (in ExtInstr) encodeCountPnW(ops []ExtOperand) ([]byte, error) {
	rd, pn := ops[0], ops[1]
	if err := in.generalOperand(rd, 1, 1); err != nil {
		return nil, err
	}
	if err := in.predicateOperand(pn, 2, 0, 15, ExtArrNone); err != nil {
		return nil, err
	}
	if err := in.generalOperand(ops[2], 3, 1); err != nil {
		return nil, err
	}
	if ops[2].Reg != rd.Reg || ops[2].Reg31 != rd.Reg31 {
		return nil, fmt.Errorf("%s: operands 1 and 3 are the same register, got R%d and R%d",
			in.Name, rd.Reg, ops[2].Reg)
	}
	size, ok := pn.Arr.sizeBits()
	if !ok {
		return nil, fmt.Errorf("%s: arrangement %s has no size encoding in this class",
			in.Name, pn.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldPn4, uint32(pn.Reg))
	word = extSet(word, extFieldRd, uint32(rd.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// simdReg validates a 128-bit SIMD register operand of the reduction
// classes: V0-V31, written bare, no suffix and no qualifier.
func (in ExtInstr) simdReg(op ExtOperand, position int) error {
	if op.Kind != ExtVReg {
		return fmt.Errorf("%s: operand %d wants a SIMD register, got %s",
			in.Name, position, op.Kind)
	}
	if op.Reg < 0 || op.Reg > 31 {
		return fmt.Errorf("%s: operand %d is V%d, outside V0-V31", in.Name, position, op.Reg)
	}
	if op.Arr != ExtArrNone || op.Qual != ExtQualNone {
		return fmt.Errorf("%s: operand %d takes no suffix, got %s%s",
			in.Name, position, op.Arr, op.Qual)
	}
	return nil
}

// encodeReduce fills the SVE reduction into a SIMD scalar: Zn.T, Pg (bare),
// Vd.  The governing predicate is the narrow three-bit field; the size bits
// ride the row's word where the class locks the arrangement, and follow the
// source's arrangement where it does not.
func (in ExtInstr) encodeReduce(ops []ExtOperand) ([]byte, error) {
	zn, pg, vd := ops[0], ops[1], ops[2]
	if err := in.zVector(zn, 1); err != nil {
		return nil, err
	}
	if err := in.barePredicate(pg, 2, 0, 7); err != nil {
		return nil, err
	}
	if err := in.simdReg(vd, 3); err != nil {
		return nil, err
	}
	size, err := in.zSize(zn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(vd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeReduceReadBack fills the strict-accumulation reduction: Zn.T, Vd,
// Pg (bare), Vd, the SIMD destination spelled twice.
func (in ExtInstr) encodeReduceReadBack(ops []ExtOperand) ([]byte, error) {
	zn, vd, pg := ops[0], ops[1], ops[2]
	if err := in.zVector(zn, 1); err != nil {
		return nil, err
	}
	if err := in.simdReg(vd, 2); err != nil {
		return nil, err
	}
	if err := in.barePredicate(pg, 3, 0, 7); err != nil {
		return nil, err
	}
	if err := in.simdReg(ops[3], 4); err != nil {
		return nil, err
	}
	if ops[3].Reg != vd.Reg {
		return nil, fmt.Errorf("%s: operands 2 and 4 are the same register Vd, got V%d and V%d",
			in.Name, vd.Reg, ops[3].Reg)
	}
	size, err := in.zSize(zn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(vd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// sveMemFill validates one gather/scatter memory operand against the row's
// addressing mode and fills the register slots: the first parenthesised
// register or the scaled immediate goes to the second-source slot, the
// second parenthesis or the immediate-mode base to the first-source slot.
func (in ExtInstr) sveMemFill(word uint32, op ExtOperand, position int) (uint32, error) {
	if op.Kind != ExtSveMem {
		return 0, fmt.Errorf("%s: operand %d wants an SVE memory operand, got %s",
			in.Name, position, op.Kind)
	}
	switch in.SveMode {
	case extMemPair:
		if op.BaseVec || op.Extend != 0 || op.Arr != ExtArrNone {
			return 0, fmt.Errorf("%s: operand %d wants two general registers, (Rn{<<%d})(Rm)",
				in.Name, position, in.SveShift)
		}
		if op.Shift != in.SveShift {
			return 0, fmt.Errorf("%s: operand %d wants the base scaled by <<%d, got <<%d",
				in.Name, position, in.SveShift, op.Shift)
		}
		if op.Reg < 0 || op.Reg > 30 {
			return 0, fmt.Errorf("%s: operand %d's base is R%d, outside R0-R30", in.Name, position, op.Reg)
		}
		word = extSet(word, extFieldRm, uint32(op.Reg))
		word, err := in.sveMemOff(word, op, position)
		if err != nil {
			return 0, err
		}
		return word, nil
	case extMemVecOff, extMemExt32:
		if !op.BaseVec {
			return 0, fmt.Errorf("%s: operand %d wants a vector base, (Zn.%s{<<%d})(Rm)",
				in.Name, position, in.SveBase, in.SveShift)
		}
		if op.Arr != in.SveBase {
			return 0, fmt.Errorf("%s: operand %d's base carries arrangement %s, want %s",
				in.Name, position, op.Arr, in.SveBase)
		}
		if in.SveMode == extMemExt32 && op.Extend != 1 {
			return 0, fmt.Errorf("%s: operand %d wants the UXTW extension on the base", in.Name, position)
		}
		if in.SveMode == extMemVecOff && op.Extend != 0 {
			return 0, fmt.Errorf("%s: operand %d takes no extension on the base", in.Name, position)
		}
		if op.Shift != in.SveShift {
			return 0, fmt.Errorf("%s: operand %d wants the base scaled by <<%d, got <<%d",
				in.Name, position, in.SveShift, op.Shift)
		}
		if op.Reg < 0 || op.Reg > 31 {
			return 0, fmt.Errorf("%s: operand %d's base is Z%d, outside Z0-Z31", in.Name, position, op.Reg)
		}
		word = extSet(word, extFieldRm, uint32(op.Reg))
		word, err := in.sveMemOff(word, op, position)
		if err != nil {
			return 0, err
		}
		return word, nil
	case extMemImm:
		if !op.BaseVec || op.Extend != 0 || op.Shift != 0 || op.Off != -1 {
			return 0, fmt.Errorf("%s: operand %d wants an immediate offset on a vector base, imm(Zn.%s)",
				in.Name, position, in.SveBase)
		}
		if op.Arr != in.SveBase {
			return 0, fmt.Errorf("%s: operand %d's base carries arrangement %s, want %s",
				in.Name, position, op.Arr, in.SveBase)
		}
		if op.Reg < 0 || op.Reg > 31 {
			return 0, fmt.Errorf("%s: operand %d's base is Z%d, outside Z0-Z31", in.Name, position, op.Reg)
		}
		esize := int64(1) << uint(in.SveShift)
		if op.Imm < 0 || op.Imm%esize != 0 || op.Imm/esize > 31 {
			return 0, fmt.Errorf("%s: operand %d's displacement %d is not a multiple of %d up to %d",
				in.Name, position, op.Imm, esize, 31*esize)
		}
		word = extSet(word, extFieldRm, uint32(op.Imm/esize))
		word = extSet(word, extFieldRn, uint32(op.Reg))
		return word, nil
	case extMemVecBase:
		if !op.BaseVec || op.Extend != 0 || op.Shift != 0 || op.Off != -1 {
			return 0, fmt.Errorf("%s: operand %d wants the vector base alone, (Zn.%s)",
				in.Name, position, in.SveBase)
		}
		if op.Arr != in.SveBase {
			return 0, fmt.Errorf("%s: operand %d's base carries arrangement %s, want %s",
				in.Name, position, op.Arr, in.SveBase)
		}
		if op.Reg < 0 || op.Reg > 31 {
			return 0, fmt.Errorf("%s: operand %d's base is Z%d, outside Z0-Z31", in.Name, position, op.Reg)
		}
		return extSet(word, extFieldRn, uint32(op.Reg)), nil
	default:
		return 0, fmt.Errorf("%s: the row names no addressing mode", in.Name)
	}
}

// sveMemOff validates the offset register of the parenthesised memory modes
// and fills the first-source slot: a plain R0-R30, or the stack-pointer
// spelling of the thirty-first slot.
func (in ExtInstr) sveMemOff(word uint32, op ExtOperand, position int) (uint32, error) {
	if op.Off < 0 {
		return 0, fmt.Errorf("%s: operand %d wants a second register in the memory operand",
			in.Name, position)
	}
	if op.Reg31 == 2 && op.Off == 31 {
		return extSet(word, extFieldRn, 31), nil
	}
	if op.Reg31 != 0 || op.Off < 0 || op.Off > 30 {
		return 0, fmt.Errorf("%s: operand %d's offset register is outside R0-R30, with RSP allowed",
			in.Name, position)
	}
	return extSet(word, extFieldRn, uint32(op.Off)), nil
}

// svePredicate validates the governing predicate of a gather or scatter: the
// narrow three-bit field, no arrangement suffix, zeroing on the loads and
// bare on the stores.
func (in ExtInstr) svePredicate(op ExtOperand, position int, zeroing bool) (uint32, error) {
	if err := in.predicateOperand(op, position, 0, 7, ExtArrNone); err != nil {
		return 0, err
	}
	if op.Arr != ExtArrNone {
		return 0, fmt.Errorf("%s: operand %d carries no arrangement suffix, got %s",
			in.Name, position, op.Arr)
	}
	if zeroing && op.Qual != ExtQualZeroing {
		return 0, fmt.Errorf("%s: operand %d wants the zeroing qualifier, got %q",
			in.Name, position, op.Qual)
	}
	if !zeroing && op.Qual != ExtQualNone {
		return 0, fmt.Errorf("%s: operand %d takes no qualifier, got %q",
			in.Name, position, op.Qual)
	}
	return uint32(op.Reg), nil
}

// sveList validates the destination or source vector of a gather or scatter
// against the row's locked list arrangement.
func (in ExtInstr) sveList(op ExtOperand, position int) (uint32, error) {
	if op.Kind != ExtZReg {
		return 0, fmt.Errorf("%s: operand %d wants a scalable vector register, got %s",
			in.Name, position, op.Kind)
	}
	if op.Reg < 0 || op.Reg > 31 {
		return 0, fmt.Errorf("%s: operand %d is Z%d, outside Z0-Z31", in.Name, position, op.Reg)
	}
	if op.Arr != in.Arr {
		return 0, fmt.Errorf("%s: operand %d carries arrangement %s, want %s",
			in.Name, position, op.Arr, in.Arr)
	}
	return uint32(op.Reg), nil
}

// encodeSveLoad fills the gather load: mem, Pg/Z, Zt.T.  The addressing mode
// is the row's own, its fixed word carrying the mode and list-size bits, and
// the operands fill the register slots the mode names.
func (in ExtInstr) encodeSveLoad(ops []ExtOperand) ([]byte, error) {
	word, err := in.sveMemFill(in.Word, ops[0], 1)
	if err != nil {
		return nil, err
	}
	pg, err := in.svePredicate(ops[1], 2, true)
	if err != nil {
		return nil, err
	}
	zt, err := in.sveList(ops[2], 3)
	if err != nil {
		return nil, err
	}
	word = extSet(word, extFieldPgN, pg)
	word = extSet(word, extFieldRd, zt)
	return extWordLE(word), nil
}

// encodeSveStore fills the scatter store: Zt.T, Pg, mem, mirroring the load
// with the list first and a bare governing predicate.
func (in ExtInstr) encodeSveStore(ops []ExtOperand) ([]byte, error) {
	zt, err := in.sveList(ops[0], 1)
	if err != nil {
		return nil, err
	}
	pg, err := in.svePredicate(ops[1], 2, false)
	if err != nil {
		return nil, err
	}
	word, err := in.sveMemFill(in.Word, ops[2], 3)
	if err != nil {
		return nil, err
	}
	word = extSet(word, extFieldPgN, pg)
	word = extSet(word, extFieldRd, zt)
	return extWordLE(word), nil
}

// encodeNarrow fills the two-to-one narrowing form: Zm.T2, Zn.T2, Zd.T,
// where T is one step below T2.  The wide sources combine and the
// destination keeps the high half of each result; the single size field
// serves both widths, the wide ladder on the sources and the narrow ladder
// on the destination carrying the same value, so the arrangement pair is
// validated as a whole.
func (in ExtInstr) encodeNarrow(ops []ExtOperand) ([]byte, error) {
	zm, zn, zd := ops[0], ops[1], ops[2]
	for i, op := range []ExtOperand{zm, zn, zd} {
		if err := in.zVector(op, i+1); err != nil {
			return nil, err
		}
	}
	if zm.Arr != zn.Arr {
		return nil, fmt.Errorf("%s: operands 1 and 2 carry arrangements %s and %s, they must match",
			in.Name, zm.Arr, zn.Arr)
	}
	if zm.Arr < ExtArrH || zm.Arr > ExtArrD {
		return nil, fmt.Errorf("%s: the wide sources carry arrangement %s, want .H, .S or .D",
			in.Name, zm.Arr)
	}
	if zd.Arr != zm.Arr-1 {
		return nil, fmt.Errorf("%s: the destination carries arrangement %s, want %s",
			in.Name, zd.Arr, zm.Arr-1)
	}
	size, _ := zm.Arr.sizeBits()
	word := in.Word
	word = extSet(word, extFieldRm, uint32(zm.Reg))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	word = extSet(word, in.Size, size)
	return extWordLE(word), nil
}

// encodeQuadReduce fills the SVE2.1 quadword reduction, the accumulator
// first: Zdn.T, Pg (bare), Vn.T2.  The scalable vector register accumulates
// the reduction of the quadword vector, whose counted spelling (.B16, .H8,
// .S4, .D2) names the lane width the class reduces over and must match the
// accumulator's arrangement; the encoding carries the accumulator's own
// size field.  The fields mirror the reduction class: Zdn in the
// first-source slot, the predicate in the narrow governing field, the
// vector in the destination slot.
func (in ExtInstr) encodeQuadReduce(ops []ExtOperand) ([]byte, error) {
	zdn, pg, vn := ops[0], ops[1], ops[2]
	if err := in.zVector(zdn, 1); err != nil {
		return nil, err
	}
	if err := in.barePredicate(pg, 2, 0, 7); err != nil {
		return nil, err
	}
	if vn.Kind != ExtVReg {
		return nil, fmt.Errorf("%s: operand 3 wants a SIMD register, got %s",
			in.Name, vn.Kind)
	}
	if vn.Reg < 0 || vn.Reg > 31 {
		return nil, fmt.Errorf("%s: operand 3 is V%d, outside V0-V31", in.Name, vn.Reg)
	}
	if vn.Qual != ExtQualNone {
		return nil, fmt.Errorf("%s: operand 3 takes no qualifier, got %q", in.Name, vn.Qual)
	}
	if vn.Arr == ExtArrNone {
		return nil, fmt.Errorf("%s: operand 3 carries no quadword suffix, want .B16, .H8, .S4 or .D2",
			in.Name)
	}
	if vn.Arr != zdn.Arr {
		return nil, fmt.Errorf("%s: operand 3 carries arrangement %s, want %s",
			in.Name, vn.Arr, zdn.Arr)
	}
	size, err := in.zSize(zdn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldRn, uint32(zdn.Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(vn.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeShiftWide fills the wide-vector shift: Zm.D, Zn.T, Zd.T.  The shift
// amounts ride a double-width vector locked to .D while the shifted data
// carries one shared narrower arrangement, which feeds the size field.
func (in ExtInstr) encodeShiftWide(ops []ExtOperand) ([]byte, error) {
	zm, zn, zd := ops[0], ops[1], ops[2]
	if err := in.zVector(zm, 1); err != nil {
		return nil, err
	}
	if zm.Arr != ExtArrD {
		return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .D",
			in.Name, zm.Arr)
	}
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if err := in.zVector(zd, 3); err != nil {
		return nil, err
	}
	if zn.Arr != zd.Arr {
		return nil, fmt.Errorf("%s: operands 2 and 3 carry arrangements %s and %s, they must match",
			in.Name, zn.Arr, zd.Arr)
	}
	size, err := in.zSize(zn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(zm.Reg))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(zd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

// encodeThreeSource fills the SVE2 three-source bitwise form: Za.D, Zm.D,
// Zdn.D, Zdn.D, the destination read back, the whole class locked to
// quadwords.  Operands 3 and 4 name the same register and the encoding
// carries it once, in the destination slot.
func (in ExtInstr) encodeThreeSource(ops []ExtOperand) ([]byte, error) {
	za, zm, zdn := ops[0], ops[1], ops[2]
	if err := in.zVector(za, 1); err != nil {
		return nil, err
	}
	if err := in.zVector(zm, 2); err != nil {
		return nil, err
	}
	if err := in.zVector(zdn, 3); err != nil {
		return nil, err
	}
	if err := in.zVector(ops[3], 4); err != nil {
		return nil, err
	}
	if ops[3].Reg != zdn.Reg || ops[3].Arr != zdn.Arr {
		return nil, fmt.Errorf("%s: operands 3 and 4 are the same register Zdn, got Z%d and Z%d",
			in.Name, zdn.Reg, ops[3].Reg)
	}
	word := in.Word
	word = extSet(word, extFieldRn, uint32(za.Reg))
	word = extSet(word, extFieldRm, uint32(zm.Reg))
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	return extWordLE(word), nil
}

// encodeConvert fills the SVE2 BFloat16 convert with a governing
// predicate: Zn.S, Pg{M or Z}, Zd.H, the source locked to .S and the
// destination to .H, the qualifier the row's PgQual names.
func (in ExtInstr) encodeConvert(ops []ExtOperand) ([]byte, error) {
	if err := in.zVector(ops[0], 1); err != nil {
		return nil, err
	}
	if ops[0].Arr != ExtArrS {
		return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .S", in.Name, ops[0].Arr)
	}
	pg := ops[1]
	if err := in.predicateOperand(pg, 2, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	pg.Arr = ExtArrNone
	want := in.PgQual
	if want != ExtQualMerging && want != ExtQualZeroing {
		want = ExtQualMerging
	}
	if pg.Qual != want {
		return nil, fmt.Errorf("%s: operand 2 wants the %s qualifier, got %q", in.Name, want.String(), pg.Qual)
	}
	if err := in.zVector(ops[2], 3); err != nil {
		return nil, err
	}
	if ops[2].Arr != ExtArrH {
		return nil, fmt.Errorf("%s: operand 3 carries arrangement %s, want .H", in.Name, ops[2].Arr)
	}
	word := in.Word
	word = extSet(word, extFieldPn, uint32(ops[0].Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(ops[2].Reg))
	return extWordLE(word), nil
}

// encodeMulPred fills the SVE2 BFloat16 multiply-accumulate with an
// independent destination: Zm.H, Zn.H, Pg/M, Zda.H.
func (in ExtInstr) encodeMulPred(ops []ExtOperand) ([]byte, error) {
	zm, zn, pg, zda := ops[0], ops[1], ops[2], ops[3]
	if err := in.zVector(zm, 1); err != nil {
		return nil, err
	}
	if zm.Arr != ExtArrH {
		return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .H", in.Name, zm.Arr)
	}
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if zn.Arr != ExtArrH {
		return nil, fmt.Errorf("%s: operand 2 carries arrangement %s, want .H", in.Name, zn.Arr)
	}
	if err := in.predicateOperand(pg, 3, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Qual != ExtQualMerging {
		return nil, fmt.Errorf("%s: operand 3 wants the merging qualifier, got %q", in.Name, pg.Qual)
	}
	if err := in.zVector(zda, 4); err != nil {
		return nil, err
	}
	if zda.Arr != ExtArrH {
		return nil, fmt.Errorf("%s: operand 4 carries arrangement %s, want .H", in.Name, zda.Arr)
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(zm.Reg))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldRd, uint32(zda.Reg))
	return extWordLE(word), nil
}

// encodeLongMul fills the SVE2 BFloat16 lengthened multiply: Za.H, Zn.H,
// Zm.S, the two halfword vectors under the row's Arr and the wide source
// one step above it.
// encodeVLArith fills the vector-length arithmetic: imm, Rn|SP, Rd|SP.
// The signed imm6 counts multiples of the vector length; the register
// slots spell RSP, never a plain R31.
func (in ExtInstr) encodeVLArith(ops []ExtOperand) ([]byte, error) {
	imm, rn, rd := ops[0], ops[1], ops[2]
	if imm.Kind != ExtImm {
		return nil, fmt.Errorf("%s: operand 1 wants an immediate, got %s", in.Name, imm.Kind)
	}
	if imm.Imm < -32 || imm.Imm > 31 {
		return nil, fmt.Errorf("%s: immediate %d is outside the signed 6-bit range -32..31", in.Name, imm.Imm)
	}
	if err := in.generalOperand(rn, 2, 2); err != nil {
		return nil, err
	}
	if err := in.generalOperand(rd, 3, 2); err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldImm6, uint32(imm.Imm))
	word = extSet(word, extFieldRm, uint32(rn.Reg))
	word = extSet(word, extFieldRd, uint32(rd.Reg))
	return extWordLE(word), nil
}

// encodeVLRead fills the vector-length read: imm, Rd (R0-R30).
func (in ExtInstr) encodeVLRead(ops []ExtOperand) ([]byte, error) {
	imm, rd := ops[0], ops[1]
	if imm.Kind != ExtImm {
		return nil, fmt.Errorf("%s: operand 1 wants an immediate, got %s", in.Name, imm.Kind)
	}
	if imm.Imm < -32 || imm.Imm > 31 {
		return nil, fmt.Errorf("%s: immediate %d is outside the signed 6-bit range -32..31", in.Name, imm.Imm)
	}
	if err := in.generalOperand(rd, 2, 0); err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldImm6, uint32(imm.Imm))
	word = extSet(word, extFieldRd, uint32(rd.Reg))
	return extWordLE(word), nil
}

// encodeCompare fills the SVE2 compare forms, the shared-arrangement and
// the wide shape alike: Zm, Zn, Pg/Z, Pd.  The comparison writes the
// zeroing predicate P0-P7; under the wide shape the magnitudes ride the
// double-width vector locked to .D.  Fields: Zm at bits 16..20, Zn in the
// first-source slot, Pg narrow, Pd in the four-bit destination slot.
func (in ExtInstr) encodeCompare(ops []ExtOperand) ([]byte, error) {
	zm, zn, pg, pd := ops[0], ops[1], ops[2], ops[3]
	if err := in.zVector(zm, 1); err != nil {
		return nil, err
	}
	if in.Form == ExtFormCompareWide {
		if zm.Arr != ExtArrD {
			return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .D", in.Name, zm.Arr)
		}
	}
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if in.Form == ExtFormCompare && zn.Arr != zm.Arr {
		return nil, fmt.Errorf("%s: operands 1 and 2 carry arrangements %s and %s, they must match", in.Name, zm.Arr, zn.Arr)
	}
	if in.Form == ExtFormCompareWide {
		if zn.Arr == ExtArrD {
			return nil, fmt.Errorf("%s: operand 2 carries arrangement .D, want .B, .H or .S", in.Name)
		}
	}
	if err := in.predicateOperand(pg, 3, 0, 7, ExtArrNone); err != nil {
		return nil, err
	}
	if pg.Qual != ExtQualZeroing {
		return nil, fmt.Errorf("%s: operand 3 wants the zeroing qualifier, got %q", in.Name, pg.Qual)
	}
	if pd.Kind != ExtPReg {
		return nil, fmt.Errorf("%s: operand 4 wants a predicate register, got %s", in.Name, pd.Kind)
	}
	if pd.Reg < 0 || pd.Reg > 15 {
		return nil, fmt.Errorf("%s: operand 4 is P%d, outside P0-P15", in.Name, pd.Reg)
	}
	if in.Form == ExtFormCompare && pd.Arr != zn.Arr {
		return nil, fmt.Errorf("%s: operand 4 carries arrangement %s, want %s", in.Name, pd.Arr, zn.Arr)
	}
	size, err := in.zSize(zn.Arr)
	if err != nil {
		return nil, err
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(zm.Reg))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldPgN, uint32(pg.Reg))
	word = extSet(word, extFieldPd, uint32(pd.Reg))
	if size != 0 {
		word = extSet(word, in.Size, size)
	}
	return extWordLE(word), nil
}

func (in ExtInstr) encodeLongMul(ops []ExtOperand) ([]byte, error) {
	za, zn, zm := ops[0], ops[1], ops[2]
	if err := in.zVector(za, 1); err != nil {
		return nil, err
	}
	if in.Arr != ExtArrNone && za.Arr != in.Arr {
		return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want %s", in.Name, za.Arr, in.Arr)
	}
	if err := in.zVector(zn, 2); err != nil {
		return nil, err
	}
	if zn.Arr != za.Arr {
		return nil, fmt.Errorf("%s: operands 1 and 2 carry arrangements %s and %s, they must match", in.Name, za.Arr, zn.Arr)
	}
	if zm.Kind != ExtZReg {
		return nil, fmt.Errorf("%s: operand 3 wants a scalable vector register, got %s", in.Name, zm.Kind)
	}
	if zm.Reg < 0 || zm.Reg > 31 {
		return nil, fmt.Errorf("%s: operand 3 is Z%d, outside Z0-Z31", in.Name, zm.Reg)
	}
	if zm.Arr != za.Arr+1 {
		return nil, fmt.Errorf("%s: operand 3 carries arrangement %s, want %s", in.Name, zm.Arr, za.Arr+1)
	}
	word := in.Word
	word = extSet(word, extFieldRm, uint32(za.Reg))
	word = extSet(word, extFieldRn, uint32(zn.Reg))
	word = extSet(word, extFieldRd, uint32(zm.Reg))
	return extWordLE(word), nil
}

// sharedSize returns the one element-size encoding the given arrangements
// agree on, or an error when any operand is bare, they disagree, or the
// arrangement has no size field.
func (in ExtInstr) sharedSize(arrs ...ExtArrangement) (uint32, error) {
	arr := arrs[0]
	for i, a := range arrs {
		if a == ExtArrNone {
			return 0, fmt.Errorf("%s: operand %d carries no arrangement suffix", in.Name, i+1)
		}
		if a != arr {
			return 0, fmt.Errorf("%s: operand %d carries arrangement %s, want %s",
				in.Name, i+1, a, arr)
		}
	}
	size, ok := arr.sizeBits()
	if !ok {
		return 0, fmt.Errorf("%s: arrangement %s has no size encoding in this class", in.Name, arr)
	}
	return size, nil
}

// setDestAndSize fills the destructive destination register and the size
// field from the arrangement the vector carries.
func (in ExtInstr) setDestAndSize(word uint32, zdn ExtOperand) (uint32, error) {
	if zdn.Kind != ExtZReg {
		return 0, fmt.Errorf("%s: operand 2 wants a scalable vector register, got %s",
			in.Name, zdn.Kind)
	}
	if zdn.Reg < 0 || zdn.Reg > 31 {
		return 0, fmt.Errorf("%s: operand 2 is Z%d, outside Z0-Z31", in.Name, zdn.Reg)
	}
	size, ok := zdn.Arr.sizeBits()
	if !ok {
		return 0, fmt.Errorf("%s: arrangement %s has no size encoding in this class", in.Name, zdn.Arr)
	}
	word = extSet(word, extFieldRd, uint32(zdn.Reg))
	word = extSet(word, in.Size, size)
	return word, nil
}

// sharedArrangement returns the one arrangement all vector operands carry, or
// an error when any operand is bare or they disagree.
func (in ExtInstr) sharedArrangement(ops []ExtOperand) (ExtArrangement, error) {
	arr := ops[0].Arr
	for i, op := range ops {
		if op.Arr == ExtArrNone {
			return 0, fmt.Errorf("%s: operand %d carries no arrangement suffix", in.Name, i+1)
		}
		if op.Arr != arr {
			return 0, fmt.Errorf("%s: operand %d carries arrangement %s, want %s",
				in.Name, i+1, op.Arr, arr)
		}
	}
	return arr, nil
}

// extWordLE returns a 32-bit encoding word as 4 little-endian bytes.
func extWordLE(w uint32) []byte {
	return []byte{byte(w), byte(w >> 8), byte(w >> 16), byte(w >> 24)}
}

// --- the arm64 SVE/SVE2 table ------------------------------------------------

// arm64Extensions is the extended instruction layer of arm64: the SVE and
// SVE2 integer add/subtract/multiply family.  The Go toolchain knows none of
// these; the encodings are transcribed from the ARM Architecture Reference
// Manual (DDI 0487J, Part C, Chapter C8, the alphabetical list of SVE
// instructions) and cross-checked against the GNU assembler's and LLVM's
// published encodings.
var arm64Extensions = []ExtInstr{
	// Unpredicated three-vector forms: ADD Z0.S, Z1.S, Z2.S.
	{Name: "ADD", Summary: "Add scalable vector elements, unpredicated",
		Word: 0x04200000, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: ADD (vectors, unpredicated)"},
	{Name: "SUB", Summary: "Subtract scalable vector elements, unpredicated",
		Word: 0x04200400, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SUB (vectors, unpredicated)"},
	{Name: "SQADD", Summary: "Add signed saturating scalable vector elements, unpredicated",
		Word: 0x04201000, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SQADD (vectors, unpredicated)"},
	{Name: "UQADD", Summary: "Add unsigned saturating scalable vector elements, unpredicated",
		Word: 0x04201400, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: UQADD (vectors, unpredicated)"},
	{Name: "SQSUB", Summary: "Subtract signed saturating scalable vector elements, unpredicated",
		Word: 0x04201800, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SQSUB (vectors, unpredicated)"},
	{Name: "UQSUB", Summary: "Subtract unsigned saturating scalable vector elements, unpredicated",
		Word: 0x04201c00, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: UQSUB (vectors, unpredicated)"},
	{Name: "MUL", Summary: "Multiply scalable vector elements, unpredicated",
		Word: 0x04206000, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: MUL (vectors, unpredicated)"},
	{Name: "SMULH", Summary: "Multiply signed scalable vector elements, keeping the high half, unpredicated",
		Word: 0x04206800, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SMULH (vectors, unpredicated)"},
	{Name: "UMULH", Summary: "Multiply unsigned scalable vector elements, keeping the high half, unpredicated",
		Word: 0x04206c00, Form: ExtFormVectors, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: UMULH (vectors, unpredicated)"},

	// Governed destructive forms, merging: ADD Z1.S, P0/M, Z0.S.
	{Name: "ADD", Summary: "Add scalable vector elements under a governing predicate, merging",
		Word: 0x04000000, Form: ExtFormPredicated, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: ADD (vectors, predicated)"},
	{Name: "SUB", Summary: "Subtract scalable vector elements under a governing predicate, merging",
		Word: 0x04010000, Form: ExtFormPredicated, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SUB (vectors, predicated)"},
	{Name: "SUBR", Summary: "Reverse-subtract scalable vector elements under a governing predicate, merging",
		Word: 0x04030000, Form: ExtFormPredicated, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SUBR (vectors, predicated)"},
	{Name: "MUL", Summary: "Multiply scalable vector elements under a governing predicate, merging",
		Word: 0x04100000, Form: ExtFormPredicated, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: MUL (vectors, predicated)"},
	{Name: "SMULH", Summary: "Multiply signed scalable vector elements, keeping the high half, under a governing predicate, merging",
		Word: 0x04120000, Form: ExtFormPredicated, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SMULH (vectors, predicated)"},
	{Name: "UMULH", Summary: "Multiply unsigned scalable vector elements, keeping the high half, under a governing predicate, merging",
		Word: 0x04130000, Form: ExtFormPredicated, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: UMULH (vectors, predicated)"},

	// Immediate forms: ADD $255, Z0.S.
	{Name: "ADD", Summary: "Add an unsigned immediate to scalable vector elements",
		Word: 0x2520c000, Form: ExtFormImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: ADD (vectors, immediate)"},
	{Name: "SUB", Summary: "Subtract an unsigned immediate from scalable vector elements",
		Word: 0x2521c000, Form: ExtFormImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SUB (vectors, immediate)"},
	{Name: "SUBR", Summary: "Subtract scalable vector elements from an unsigned immediate",
		Word: 0x2523c000, Form: ExtFormImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SUBR (vectors, immediate)"},
	{Name: "SQADD", Summary: "Add a signed saturating unsigned immediate to scalable vector elements",
		Word: 0x2524c000, Form: ExtFormImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SQADD (vectors, immediate)"},
	{Name: "UQADD", Summary: "Add an unsigned saturating immediate to scalable vector elements",
		Word: 0x2525c000, Form: ExtFormImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: UQADD (vectors, immediate)"},
	{Name: "SQSUB", Summary: "Subtract an unsigned immediate from scalable vector elements with signed saturation",
		Word: 0x2526c000, Form: ExtFormImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: SQSUB (vectors, immediate)"},
	{Name: "UQSUB", Summary: "Subtract an unsigned immediate from scalable vector elements with unsigned saturation",
		Word: 0x2527c000, Form: ExtFormImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: UQSUB (vectors, immediate)"},

	// The signed immediate of the multiply class: MUL $-128, Z0.B.
	{Name: "MUL", Summary: "Multiply scalable vector elements by a signed immediate",
		Word: 0x2530c000, Form: ExtFormSignedImmediate, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J, C8.2 SVE instruction descriptions: MUL (vectors, immediate)"},

	// --- the SVE and SVE2.1 predicate family ---------------------------------
	//
	// The classes below operate on predicates and predicate-as-counter
	// registers.  Their encodings follow the field layouts the ARM
	// Architecture Reference Manual's SVE2.1 predicate classes give, as laid
	// out in the toolchain's generated encoding table
	// (cmd/internal/obj/arm64/inst_gen.go, itself generated by
	// x/arch/arm64/instgen from Arm's official ISA description) and in its
	// generated corpus file arm64sveenc.s: the golden test pins every
	// corpus line of each class byte for byte, so no class rests on
	// transcription alone.  The toolchain's spellings are kept, including
	// its P prefix on the predicate-register instructions (PRDFFR for
	// RDFFR, PPTRUE for PTRUE, PREV for the predicate REV), because those
	// are the names the corpus assembles under.

	// Predicate logical operations, SVE2.1: PAND P4.B, P2.B, P1.Z, P14.B.
	{Name: "PAND", Summary: "And predicates over a governing predicate's active lanes",
		Word: 0x25004000, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PAND (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PANDS", Summary: "And predicates, setting the condition flags",
		Word: 0x25404000, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PANDS (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PBIC", Summary: "And-complement predicates over a governing predicate's active lanes",
		Word: 0x25004010, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBIC (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PBICS", Summary: "And-complement predicates, setting the condition flags",
		Word: 0x25404010, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBICS (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PEOR", Summary: "Exclusive-or predicates over a governing predicate's active lanes",
		Word: 0x25004200, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PEOR (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PEORS", Summary: "Exclusive-or predicates, setting the condition flags",
		Word: 0x25404200, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PEORS (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PNAND", Summary: "And-complement two predicates into one",
		Word: 0x25804210, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PNAND (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PNANDS", Summary: "And-complement two predicates, setting the condition flags",
		Word: 0x25c04210, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PNANDS (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PNOR", Summary: "Or-complement two predicates into one",
		Word: 0x25804200, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PNOR (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PNORS", Summary: "Or-complement two predicates, setting the condition flags",
		Word: 0x25c04200, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PNORS (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PORN", Summary: "Or-complement two predicates into one, complement reversed",
		Word: 0x25804010, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PORN (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PORNS", Summary: "Or-complement two predicates, complement reversed, setting the flags",
		Word: 0x25c04010, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PORNS (predicates); inst_gen.go + arm64sveenc.s"},
	{Name: "PORR", Summary: "Or two predicates into one",
		Word: 0x25804000, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: POR (predicates) as PORR; inst_gen.go + arm64sveenc.s"},
	{Name: "PORRS", Summary: "Or two predicates, setting the condition flags",
		Word: 0x25c04000, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PORS (predicates) as PORR; inst_gen.go + arm64sveenc.s"},
	{Name: "PSEL", Summary: "Select predicate elements by a governing predicate",
		Word: 0x25004210, Form: ExtFormPredicateSelect, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PSEL (predicates); inst_gen.go + arm64sveenc.s"},

	// Break operations, SVE2.1 generalised breaks.
	{Name: "PBRKA", Summary: "Break after the first true of the governing predicate",
		Word: 0x25104000, Form: ExtFormPredicateBreak, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKA (break after first true); inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKAS", Summary: "Break after the first false, setting the condition flags",
		Word: 0x25504000, Form: ExtFormPredicateBreakZero, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKAS (break after first false); inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKB", Summary: "Break before the first true of the governing predicate",
		Word: 0x25904000, Form: ExtFormPredicateBreak, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKB (break before first true); inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKBS", Summary: "Break before the first false, setting the condition flags",
		Word: 0x25d04000, Form: ExtFormPredicateBreakZero, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKBS (break before first false); inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKN", Summary: "Break after the first true of the second source",
		Word: 0x25184000, Form: ExtFormPredicateLogicalDest, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKN (break after first true); inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKNS", Summary: "Break after the first true of the second source, setting the flags",
		Word: 0x25584000, Form: ExtFormPredicateLogicalDest, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKNS; inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKPA", Summary: "Break after the first true, preserving the first source's leading lanes",
		Word: 0x2500c000, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKPA (break propagating after); inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKPAS", Summary: "Break propagating after the first false, setting the flags",
		Word: 0x2540c000, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKPAS; inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKPB", Summary: "Break propagating before the first true",
		Word: 0x2500c010, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKPB (break propagating before); inst_gen.go + arm64sveenc.s"},
	{Name: "PBRKPBS", Summary: "Break propagating before the first false, setting the flags",
		Word: 0x2540c010, Form: ExtFormPredicateLogical, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PBRKPBS; inst_gen.go + arm64sveenc.s"},

	// Predicate permutations, SVE2.1.
	{Name: "PTRN1", Summary: "Transpose odd predicate elements",
		Word: 0x05205000, Form: ExtFormPredicatePermute, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: TRN1 (predicates) as PTRN1; inst_gen.go + arm64sveenc.s"},
	{Name: "PTRN2", Summary: "Transpose even predicate elements",
		Word: 0x05205400, Form: ExtFormPredicatePermute, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: TRN2 (predicates) as PTRN2; inst_gen.go + arm64sveenc.s"},
	{Name: "PUZP1", Summary: "Unzip odd predicate elements",
		Word: 0x05204800, Form: ExtFormPredicatePermute, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: UZP1 (predicates) as PUZP1; inst_gen.go + arm64sveenc.s"},
	{Name: "PUZP2", Summary: "Unzip even predicate elements",
		Word: 0x05204c00, Form: ExtFormPredicatePermute, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: UZP2 (predicates) as PUZP2; inst_gen.go + arm64sveenc.s"},
	{Name: "PZIP1", Summary: "Zip odd predicate elements",
		Word: 0x05204000, Form: ExtFormPredicatePermute, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZIP1 (predicates) as PZIP1; inst_gen.go + arm64sveenc.s"},
	{Name: "PZIP2", Summary: "Zip even predicate elements",
		Word: 0x05204400, Form: ExtFormPredicatePermute, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZIP2 (predicates) as PZIP2; inst_gen.go + arm64sveenc.s"},

	// Predicate initialise, test and permute singles.
	{Name: "PPFALSE", Summary: "Initialise a predicate to false",
		Word: 0x2518e400, Form: ExtFormPredicateOne, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PFALSE as PPFALSE; inst_gen.go + arm64sveenc.s"},
	{Name: "PPFIRST", Summary: "Set the first active element of a predicate",
		Word: 0x2558c000, Form: ExtFormPredicateFirst, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PFIRST as PPFIRST; inst_gen.go + arm64sveenc.s"},
	{Name: "PPNEXT", Summary: "Set the next active element of a predicate",
		Word: 0x2519c400, Form: ExtFormPredicateNext, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PNEXT as PPNEXT; inst_gen.go + arm64sveenc.s"},
	{Name: "PPTEST", Summary: "Test a predicate against a governing predicate, setting the flags",
		Word: 0x2550c000, Form: ExtFormPredicateTest, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PTEST as PPTEST; inst_gen.go + arm64sveenc.s"},
	{Name: "PPTRUE", Summary: "Initialise a predicate-as-counter register from a pattern",
		Word: 0x25207810, Form: ExtFormPredicateCounter, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PTRUE (counter form) as PPTRUE; inst_gen.go + arm64sveenc.s"},
	{Name: "PPUNPKHI", Summary: "Unpack the even elements of a half-word predicate",
		Word: 0x05314000, Form: ExtFormPredicateUnpack, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PUNPKHI as PPUNPKHI; inst_gen.go + arm64sveenc.s"},
	{Name: "PPUNPKLO", Summary: "Unpack the odd elements of a half-word predicate",
		Word: 0x05304000, Form: ExtFormPredicateUnpack, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PUNPKLO as PPUNPKLO; inst_gen.go + arm64sveenc.s"},

	// First-fault register and predicate reverse.
	{Name: "PRDFFR", Summary: "Read the first-fault register to a predicate, zeroing",
		Word: 0x2518f000, Form: ExtFormPredicateFFRRead, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: RDFFR (predicated) as PRDFFR; inst_gen.go + arm64sveenc.s"},
	{Name: "PRDFFR", Summary: "Read the first-fault register to a predicate whole",
		Word: 0x2519f000, Form: ExtFormPredicateOne, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: RDFFR (unpredicated) as PRDFFR; inst_gen.go + arm64sveenc.s"},
	{Name: "PRDFFRS", Summary: "Read the first-fault register to a predicate, zeroing, setting the flags",
		Word: 0x2558f000, Form: ExtFormPredicateFFRRead, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: RDFFRS as PRDFFRS; inst_gen.go + arm64sveenc.s"},
	{Name: "PWRFFR", Summary: "Write the first-fault register from a predicate",
		Word: 0x25289000, Form: ExtFormPredicateWrite, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WRFFR as PWRFFR; inst_gen.go + arm64sveenc.s"},
	{Name: "PREV", Summary: "Reverse the elements of a predicate",
		Word: 0x05344000, Form: ExtFormPredicateMove, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: REV (predicate) as PREV; inst_gen.go + arm64sveenc.s"},
	{Name: "SETFFR", Summary: "Set the first-fault register to all true",
		Word: 0x252c9000, Form: ExtFormNone, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SETFFR; inst_gen.go + arm64sveenc.s"},

	// While compares: build a predicate from a scalar loop condition.
	{Name: "PWHILEGE", Summary: "Build a predicate while the signed greater-or-equal comparison holds",
		Word: 0x25201000, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEGE as PWHILEGE; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEGT", Summary: "Build a predicate while the signed greater comparison holds",
		Word: 0x25201010, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEGT as PWHILEGT; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEHI", Summary: "Build a predicate while the unsigned higher comparison holds",
		Word: 0x25201810, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEHI as PWHILEHI; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEHS", Summary: "Build a predicate while the unsigned higher-or-same comparison holds",
		Word: 0x25201800, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEHS as PWHILEHS; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELE", Summary: "Build a predicate while the signed less-or-equal comparison holds",
		Word: 0x25201410, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELE as PWHILELE; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELO", Summary: "Build a predicate while the unsigned lower comparison holds",
		Word: 0x25201c00, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELO as PWHILELO; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELS", Summary: "Build a predicate while the unsigned lower-or-same comparison holds",
		Word: 0x25201c10, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELS as PWHILELS; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELT", Summary: "Build a predicate while the signed less comparison holds",
		Word: 0x25201400, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELT as PWHILELT; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILERW", Summary: "Build a predicate over a read-write region",
		Word: 0x25203010, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PWHILERW (SVE2.1); inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEWR", Summary: "Build a predicate over a write region",
		Word: 0x25203000, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: PWHILEWR (SVE2.1); inst_gen.go + arm64sveenc.s"},

	// --- the SVE2.1 Z-alias permutations, copies and unary forms -------------
	//
	// The Z-prefixed names are the toolchain corpus spellings of the SVE2.1
	// alias families: the unary and binary predicated forms, the immediate
	// aliases, the vector permutations and selects, and the register-copy
	// forms.  Provenance as above: the toolchain encoding table and its
	// generated corpus agree with the manual layouts, and the golden test
	// pins every corpus line of each covered class.
	{Name: "ZABS", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0416a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZABS; inst_gen.go + arm64sveenc.s"}, {Name: "ZREVB", Summary: "Reverse byte order within elements, predicated",
		Word: 0x05248000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZREVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVB", Summary: "Reverse byte order within elements, zeroing",
		Word: 0x0524a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZREVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVH", Summary: "Reverse halfword order within elements, predicated",
		Word: 0x05a58000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZREVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVH", Summary: "Reverse halfword order within elements, zeroing",
		Word: 0x05a5a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZREVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSXTB", Summary: "Sign-extend bytes to the element width, predicated",
		Word: 0x0410a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSXTB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSXTB", Summary: "Sign-extend bytes to the element width, zeroing",
		Word: 0x0400a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSXTB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSXTH", Summary: "Sign-extend halfwords to the element width, predicated",
		Word: 0x0492a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSXTH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSXTH", Summary: "Sign-extend halfwords to the element width, zeroing",
		Word: 0x0482a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSXTH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUXTB", Summary: "Zero-extend bytes to the element width, predicated",
		Word: 0x0411a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZUXTB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUXTB", Summary: "Zero-extend bytes to the element width, zeroing",
		Word: 0x0401a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZUXTB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUXTH", Summary: "Zero-extend halfwords to the element width, predicated",
		Word: 0x0493a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZUXTH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUXTH", Summary: "Zero-extend halfwords to the element width, zeroing",
		Word: 0x0483a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZUXTH; inst_gen.go + arm64sveenc.s"},

	{Name: "ZABS", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0406a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZABS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADD", Summary: "Z-alias of the predicated binary form, source copy spelled",
		Word: 0x04000000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZADD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADD", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x04200000, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZADD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADD", Summary: "Z-alias of the immediate form, destination copy spelled",
		Word: 0x2520c000, Form: ExtFormZImmediateSource, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZADD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZAND", Summary: "Z-alias of the unpredicated three-vector form, locked to .D",
		Word: 0x04203000, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZAND; inst_gen.go + arm64sveenc.s"},
	{Name: "ZAND", Summary: "Z-alias of the predicated binary form, source copy spelled",
		Word: 0x041a0000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZAND; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBIC", Summary: "Z-alias of the unpredicated three-vector form, locked to .D",
		Word: 0x04e03000, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZBIC; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBIC", Summary: "Z-alias of the predicated binary form, source copy spelled",
		Word: 0x041b0000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZBIC; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCLS", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0418a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCLS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCLS", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0408a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCLS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCLZ", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0419a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCLZ; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCLZ", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0409a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCLZ; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCNOT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x041ba000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCNOT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCNOT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x040ba000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCNOT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCNT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x041aa000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCNT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCNT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x040aa000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCNT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCOMPACT", Summary: "Compact or expand over a governing predicate",
		Word: 0x05218000, Form: ExtFormZGov, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZCOMPACT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZDECP", Summary: "Decrement a vector by a predicate's active elements",
		Word: 0x252d8000, Form: ExtFormCountPnVec, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: DECP (vector) as ZDECP; inst_gen.go + arm64sveenc.s"},
	{Name: "ZDUP", Summary: "Copy or insert a general register, .D locked",
		Word: 0x05e03800, Form: ExtFormZFromGeneral, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZDUP; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEOR", Summary: "Z-alias of the unpredicated three-vector form, locked to .D",
		Word: 0x04a03000, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZEOR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEOR", Summary: "Z-alias of the predicated binary form, source copy spelled",
		Word: 0x04190000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZEOR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEXPAND", Summary: "Compact or expand over a governing predicate",
		Word: 0x05318000, Form: ExtFormZGov, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZEXPAND; inst_gen.go + arm64sveenc.s"},
	{Name: "ZINSR", Summary: "Copy or insert a general register, .D locked",
		Word: 0x05e43800, Form: ExtFormZFromGeneral, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZINSR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLASTA", Summary: "Last active element into a register, .D locked",
		Word: 0x05e0a000, Form: ExtFormZLastReg, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZLASTA; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLASTB", Summary: "Last active element into a register, .D locked",
		Word: 0x05e1a000, Form: ExtFormZLastReg, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZLASTB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZMOVPRFX", Summary: "Z-alias of the predicated form, either qualifier, one encoding",
		Word: 0x04102000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualAny, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZMOVPRFX; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVD", Summary: "Reverse the order of quadwords, zeroing",
		Word: 0x052ea000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZREVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVW", Summary: "Reverse word order within doublewords, zeroing",
		Word: 0x05e6a000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZREVW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSXTW", Summary: "Sign-extend words to doublewords, zeroing",
		Word: 0x04c4a000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSXTW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUXTW", Summary: "Zero-extend words to doublewords, zeroing",
		Word: 0x04c5a000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUXTW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZMOVPRFX", Summary: "MOVPRFX prefix spelling without arrangements",
		Word: 0x0420bc00, Form: ExtFormZMoveBare, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZMOVPRFX; inst_gen.go + arm64sveenc.s"},
	{Name: "ZNEG", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0417a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZNEG; inst_gen.go + arm64sveenc.s"},
	{Name: "ZNEG", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0407a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZNEG; inst_gen.go + arm64sveenc.s"},
	{Name: "ZNOT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x041ea000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZNOT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZNOT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x040ea000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZNOT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZORR", Summary: "Z-alias of the unpredicated three-vector form, locked to .D",
		Word: 0x04603000, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZORR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZORR", Summary: "Z-alias of the predicated binary form, source copy spelled",
		Word: 0x04180000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZORR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZRBIT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x05278000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZRBIT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZRBIT", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x0527a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZRBIT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREV", Summary: "Reverse the elements of a vector",
		Word: 0x05383800, Form: ExtFormZMove, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZREV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVD", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x052e8000, Form: ExtFormZUnary, PgQual: ExtQualMerging, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZREVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVD", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x052ea000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZREVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVW", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x05e68000, Form: ExtFormZUnary, PgQual: ExtQualMerging, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZREVW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZREVW", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x05e6a000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZREVW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSEL", Summary: "Select vector elements by a predicate",
		Word: 0x0520c000, Form: ExtFormZSelect, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSEL; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQABS", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x4408a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSQABS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQABS", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x440aa000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSQABS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQNEG", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x4409a000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSQNEG; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQNEG", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x440ba000, Form: ExtFormZUnary, Size: extSizeBHSD, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSQNEG; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUB", Summary: "Z-alias of the predicated binary form, source copy spelled",
		Word: 0x04010000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSUB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUB", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x04200400, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSUB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUB", Summary: "Z-alias of the immediate form, destination copy spelled",
		Word: 0x2521c000, Form: ExtFormZImmediateSource, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSUB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUBR", Summary: "Z-alias of the predicated binary form, source copy spelled",
		Word: 0x04030000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSUBR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUBR", Summary: "Z-alias of the immediate form, destination copy spelled",
		Word: 0x2523c000, Form: ExtFormZImmediateSource, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSUBR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUNPKHI", Summary: "Unpack a byte vector into a wider one",
		Word: 0x05313800, Form: ExtFormZUnpack, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSUNPKHI; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUNPKLO", Summary: "Unpack a byte vector into a wider one",
		Word: 0x05303800, Form: ExtFormZUnpack, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSUNPKLO; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSXTW", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x04d4a000, Form: ExtFormZUnary, PgQual: ExtQualMerging, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSXTW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSXTW", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x04c4a000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZSXTW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZTBX", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05202c00, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZTBX; inst_gen.go + arm64sveenc.s"},
	{Name: "ZTBXQ", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05203400, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZTBXQ; inst_gen.go + arm64sveenc.s"},
	{Name: "ZTRN1", Summary: "Z-alias of the unpredicated three-vector form, locked to .Q",
		Word: 0x05a01800, Form: ExtFormVectorsZm, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZTRN1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZTRN1", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05207000, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZTRN1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZTRN2", Summary: "Z-alias of the unpredicated three-vector form, locked to .Q",
		Word: 0x05a01c00, Form: ExtFormVectorsZm, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZTRN2; inst_gen.go + arm64sveenc.s"},
	{Name: "ZTRN2", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05207400, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZTRN2; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUUNPKHI", Summary: "Unpack a byte vector into a wider one",
		Word: 0x05333800, Form: ExtFormZUnpack, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUUNPKHI; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUUNPKLO", Summary: "Unpack a byte vector into a wider one",
		Word: 0x05323800, Form: ExtFormZUnpack, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUUNPKLO; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUXTW", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x04d5a000, Form: ExtFormZUnary, PgQual: ExtQualMerging, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUXTW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUXTW", Summary: "Z-alias of the predicated form, over a governing predicate",
		Word: 0x04c5a000, Form: ExtFormZUnary, PgQual: ExtQualZeroing, Arr: ExtArrD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUXTW; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUZP1", Summary: "Z-alias of the unpredicated three-vector form, locked to .Q",
		Word: 0x05a00800, Form: ExtFormVectorsZm, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUZP1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUZP1", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05206800, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUZP1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUZP2", Summary: "Z-alias of the unpredicated three-vector form, locked to .Q",
		Word: 0x05a00c00, Form: ExtFormVectorsZm, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUZP2; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUZP2", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05206c00, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUZP2; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUZPQ1", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x4400e800, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUZPQ1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUZPQ2", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x4400ec00, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZUZPQ2; inst_gen.go + arm64sveenc.s"},
	{Name: "ZZIP1", Summary: "Z-alias of the unpredicated three-vector form, locked to .Q",
		Word: 0x05a00000, Form: ExtFormVectorsZm, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZZIP1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZZIP1", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05206000, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZZIP1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZZIP2", Summary: "Z-alias of the unpredicated three-vector form, locked to .Q",
		Word: 0x05a00400, Form: ExtFormVectorsZm, Arr: ExtArrQ, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZZIP2; inst_gen.go + arm64sveenc.s"},
	{Name: "ZZIP2", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x05206400, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZZIP2; inst_gen.go + arm64sveenc.s"},
	{Name: "ZZIPQ1", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x4400e000, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZZIPQ1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZZIPQ2", Summary: "Z-alias of the unpredicated three-vector form",
		Word: 0x4400e400, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1, Ref: "ARM DDI 0487J SVE2.1: ZZIPQ2; inst_gen.go + arm64sveenc.s"},

	// --- the SVE2.1 narrowing two-to-one family ------------------------------
	//
	// The add, rounding add, subtract and rounding subtract narrow steps:
	// two wide vectors combine and the destination keeps the high half of
	// each result, bottom or top.  The sources carry .H, .S or .D and the
	// destination the arrangement one step below; one size field serves
	// both.  Provenance as above: the toolchain encoding table and its
	// generated corpus, both produced from Arm's official ISA description,
	// and the golden test pins every corpus line of the family.
	{Name: "ZADDHNB", Summary: "Add narrow high, bottom half destination",
		Word: 0x45206000, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZADDHNB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADDHNT", Summary: "Add narrow high, top half destination",
		Word: 0x45206400, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZADDHNT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZRADDHNB", Summary: "Add narrow high with rounding, bottom half destination",
		Word: 0x45206800, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZRADDHNB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZRADDHNT", Summary: "Add narrow high with rounding, top half destination",
		Word: 0x45206c00, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZRADDHNT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZRSUBHNB", Summary: "Subtract narrow high with rounding, bottom half destination",
		Word: 0x45207800, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZRSUBHNB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZRSUBHNT", Summary: "Subtract narrow high with rounding, top half destination",
		Word: 0x45207c00, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZRSUBHNT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUBHNB", Summary: "Subtract narrow high, bottom half destination",
		Word: 0x45207000, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSUBHNB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSUBHNT", Summary: "Subtract narrow high, top half destination",
		Word: 0x45207400, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSUBHNT; inst_gen.go + arm64sveenc.s"},

	// --- the SVE2.1 pairwise and quadword-reduction families ------------------
	//
	// ADDP sums the halves of two vectors pairwise under a governing
	// predicate, ADDPT the top halves of 128-bit pairs (predicated and
	// unpredicated), and the QV class reduces a quadword vector into a
	// scalable accumulator.  The QV vector operand carries the counted
	// quadword spelling the corpus writes, V5.S4 and friends.  Provenance
	// as above: the toolchain encoding table and its generated corpus, both
	// produced from Arm's official ISA description, and the golden test
	// pins every corpus line of each class.
	{Name: "ZADDP", Summary: "Add vector halves pairwise, merging",
		Word: 0x4411a000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZADDP; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADDPT", Summary: "Add the top halves of 128-bit pairs, merging",
		Word: 0x04c40000, Form: ExtFormZPredicatedSource, Arr: ExtArrD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZADDPT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADDPT", Summary: "Add the top halves of 128-bit pairs, unpredicated",
		Word: 0x04e00800, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZADDPT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADDQV", Summary: "Add a quadword vector into a scalable accumulator",
		Word: 0x04052000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZADDQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZANDQV", Summary: "And a quadword vector into a scalable accumulator",
		Word: 0x041e2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZANDQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEORQV", Summary: "Exclusive-or a quadword vector into a scalable accumulator",
		Word: 0x041d2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZEORQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFADDQV", Summary: "Add floating-point a quadword vector into a scalable accumulator",
		Word: 0x6410a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZFADDQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXNMQV", Summary: "Maximum number of a quadword vector into a scalable accumulator",
		Word: 0x6414a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZFMAXNMQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXQV", Summary: "Maximum of a quadword vector into a scalable accumulator",
		Word: 0x6416a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZFMAXQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINNMQV", Summary: "Minimum number of a quadword vector into a scalable accumulator",
		Word: 0x6415a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZFMINNMQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINQV", Summary: "Minimum of a quadword vector into a scalable accumulator",
		Word: 0x6417a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZFMINQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZORQV", Summary: "Or a quadword vector into a scalable accumulator",
		Word: 0x041c2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZORQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMAXQV", Summary: "Signed maximum of a quadword vector into a scalable accumulator",
		Word: 0x040c2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSMAXQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMINQV", Summary: "Signed minimum of a quadword vector into a scalable accumulator",
		Word: 0x040e2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZSMINQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMAXQV", Summary: "Unsigned maximum of a quadword vector into a scalable accumulator",
		Word: 0x040d2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZUMAXQV; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMINQV", Summary: "Unsigned minimum of a quadword vector into a scalable accumulator",
		Word: 0x040f2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: ZUMINQV; inst_gen.go + arm64sveenc.s"},

	// --- the SVE2 shift-by-vector family --------------------------------------
	//
	// The arithmetic, logical and rounding shift steps over a vector of
	// shift amounts: the predicated-source shapes share one arrangement,
	// and the wide three-vector shape takes its amounts from a double-width
	// vector locked to .D.  The shift-by-immediate shapes of the same
	// mnemonics (the tsz:imm3 class) are not wired yet.  Provenance as
	// above: the toolchain encoding table and its generated corpus, both
	// produced from Arm's official ISA description, and the golden test
	// pins every corpus line of the covered shapes.
	{Name: "ZASR", Summary: "Shift right arithmetic by a vector, merging",
		Word: 0x04108000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZASR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZASR", Summary: "Shift right arithmetic by a wide vector, unpredicated",
		Word: 0x04208000, Form: ExtFormShiftWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZASR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZASRR", Summary: "Shift right arithmetic by a vector with rounding, merging",
		Word: 0x04148000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZASRR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLSL", Summary: "Shift left by a vector, merging",
		Word: 0x04138000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZLSL; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLSL", Summary: "Shift left by a wide vector, unpredicated",
		Word: 0x04208c00, Form: ExtFormShiftWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZLSL; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLSLR", Summary: "Shift left by a vector with rounding, merging",
		Word: 0x04178000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZLSLR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLSR", Summary: "Shift right logical by a vector, merging",
		Word: 0x04118000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZLSR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLSR", Summary: "Shift right logical by a wide vector, unpredicated",
		Word: 0x04208400, Form: ExtFormShiftWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZLSR; inst_gen.go + arm64sveenc.s"},
	{Name: "ZLSRR", Summary: "Shift right logical by a vector with rounding, merging",
		Word: 0x04158000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZLSRR; inst_gen.go + arm64sveenc.s"},

	// --- the SVE2 three-source and bitwise combine families -------------------
	//
	// The three-source bitwise operations (EOR3, BCAX, BSL and its
	// complements, NBSL) locked to quadwords, and the two-vector combines
	// over a free arrangement (BDEP, BEXT, BGRP, EORBT, EORTB).  Provenance
	// as above: the toolchain encoding table and its generated corpus, both
	// produced from Arm's official ISA description, and the golden test
	// pins every corpus line of the family.  The XAR rotate rides the
	// tsz:imm3 immediate class, unwired with the other shift immediates.
	{Name: "ZBCAX", Summary: "Broadcast-complement and exclusive-or three sources, .D locked",
		Word: 0x04603800, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBCAX; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBDEP", Summary: "Deposite bit particles from adjacent pairs",
		Word: 0x4500b400, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBDEP; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBEXT", Summary: "Extract bit particles from adjacent pairs",
		Word: 0x4500b000, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBEXT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBGRP", Summary: "Group bit particles from adjacent pairs",
		Word: 0x4500b800, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBGRP; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBSL", Summary: "Bitwise select three sources, .D locked",
		Word: 0x04203c00, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBSL; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBSL1N", Summary: "Bitwise select with first source inverted, .D locked",
		Word: 0x04603c00, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBSL1N; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBSL2N", Summary: "Bitwise select with second source inverted, .D locked",
		Word: 0x04a03c00, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBSL2N; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEOR3", Summary: "Exclusive-or three sources, .D locked",
		Word: 0x04203800, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZEOR3; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEORBT", Summary: "Exclusive-or bottom of one source with top of the other",
		Word: 0x45009000, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZEORBT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEORTB", Summary: "Exclusive-or top of one source with bottom of the other",
		Word: 0x45009400, Form: ExtFormVectorsZm, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZEORTB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZNBSL", Summary: "Bitwise select with negated result, .D locked",
		Word: 0x04e03c00, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZNBSL; inst_gen.go + arm64sveenc.s"},

	// --- the SVE2 BFloat16 arithmetic core ------------------------------------
	//
	// The two-shape arithmetic (ADD, MAX, MAXNM, MIN, MINNM, MUL, SUB)
	// over halfwords only: the predicated-source and unpredicated
	// three-vector spellings, the clamp over the unpredicated shape, and
	// the B-to-H conversions of the F1CVT and F2CVT pairs.  The remaining
	// BFloat16 shapes (dot products, lengthened multiplies, converts with
	// a governing predicate) stay unwired.  Provenance as above: the
	// toolchain encoding table and its generated corpus, both produced
	// from Arm's official ISA description, and the golden test pins every
	// corpus line of the covered classes.
	{Name: "ZBF1CVT", Summary: "Convert BFloat16 pairs from bytes to halfwords, bottom",
		Word: 0x65083800, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBF1CVT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBF1CVTLT", Summary: "Convert BFloat16 pairs from bytes to halfwords, bottom, no rounding",
		Word: 0x65093800, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBF1CVTLT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBF2CVT", Summary: "Convert BFloat16 pairs from bytes to halfwords, top",
		Word: 0x65083c00, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBF2CVT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBF2CVTLT", Summary: "Convert BFloat16 pairs from bytes to halfwords, top, no rounding",
		Word: 0x65093c00, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBF2CVTLT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZF1CVT", Summary: "Convert FP8 byte pairs to halfwords, bottom",
		Word: 0x65083000, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: F1CVT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZF1CVTLT", Summary: "Convert FP8 byte pairs to halfwords, bottom, no rounding",
		Word: 0x65093000, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: F1CVTLT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZF2CVT", Summary: "Convert FP8 byte pairs to halfwords, top",
		Word: 0x65083400, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: F2CVT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZF2CVTLT", Summary: "Convert FP8 byte pairs to halfwords, top, no rounding",
		Word: 0x65093400, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: F2CVTLT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFADD", Summary: "Add BFloat16 halfwords, merging",
		Word: 0x65008000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFADD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFADD", Summary: "Add BFloat16 halfwords, unpredicated",
		Word: 0x65000000, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFADD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFCLAMP", Summary: "Clamp BFloat16 halfwords between bounds, unpredicated",
		Word: 0x64202400, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFCLAMP; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMAX", Summary: "Maximum of BFloat16 halfwords, merging",
		Word: 0x65068000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMAX; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMAXNM", Summary: "Maximum number of BFloat16 halfwords, merging",
		Word: 0x65048000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMAXNM; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMIN", Summary: "Minimum of BFloat16 halfwords, merging",
		Word: 0x65078000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMIN; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMINNM", Summary: "Minimum number of BFloat16 halfwords, merging",
		Word: 0x65058000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMINNM; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMUL", Summary: "Multiply BFloat16 halfwords, merging",
		Word: 0x65028000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMUL; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMUL", Summary: "Multiply BFloat16 halfwords, unpredicated",
		Word: 0x65000800, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMUL; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFSUB", Summary: "Subtract BFloat16 halfwords, merging",
		Word: 0x65018000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFSUB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFSUB", Summary: "Subtract BFloat16 halfwords, unpredicated",
		Word: 0x65000400, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFSUB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFCVT", Summary: "Convert BFloat16 halfwords to words from a source, merging",
		Word: 0x658aa000, Form: ExtFormConvert, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFCVT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFCVT", Summary: "Convert BFloat16 halfwords to words from a source, zeroing",
		Word: 0x649ac000, Form: ExtFormConvert, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFCVT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFCVTNT", Summary: "Convert BFloat16 halfwords to words from a source, merging, no rounding",
		Word: 0x648aa000, Form: ExtFormConvert, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFCVTNT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFCVTNT", Summary: "Convert BFloat16 halfwords to words from a source, zeroing, no rounding",
		Word: 0x6482a000, Form: ExtFormConvert, PgQual: ExtQualZeroing, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFCVTNT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFDOT", Summary: "Dot product of BFloat16 pairs into words",
		Word: 0x64608000, Form: ExtFormLongMul, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFDOT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMLA", Summary: "Multiply-accumulate BFloat16 halfwords, merging",
		Word: 0x65200000, Form: ExtFormMulPred, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMLA; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMLALB", Summary: "Lengthened multiply-accumulate of BFloat16 halfwords, bottom",
		Word: 0x64e08000, Form: ExtFormLongMul, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMLALB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMLALT", Summary: "Lengthened multiply-accumulate of BFloat16 halfwords, top",
		Word: 0x64e08400, Form: ExtFormLongMul, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMLALT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMLS", Summary: "Multiply-subtract BFloat16 halfwords, merging",
		Word: 0x65202000, Form: ExtFormMulPred, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMLS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMLSLB", Summary: "Lengthened multiply-subtract of BFloat16 halfwords, bottom",
		Word: 0x64e0a000, Form: ExtFormLongMul, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMLSLB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMLSLT", Summary: "Lengthened multiply-subtract of BFloat16 halfwords, top",
		Word: 0x64e0a400, Form: ExtFormLongMul, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMLSLT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFMMLA", Summary: "Matrix multiply-accumulate of BFloat16 halfwords",
		Word: 0x6460e400, Form: ExtFormLongMul, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFMMLA; inst_gen.go + arm64sveenc.s"},
	{Name: "ZBFSCALE", Summary: "Scale BFloat16 halfwords by a power of two, merging",
		Word: 0x65098000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZBFSCALE; inst_gen.go + arm64sveenc.s"},

	// --- the SVE2.1 last-active and compare families --------------------------
	//
	// The conditionally-extract-last-active-element vector shape and the
	// compares to a predicate destination, in their shared-arrangement and
	// wide spellings.  The register-destination shapes of CLASTA and
	// CLASTB, and the immediate compares, stay unwired.  Provenance as
	// above: the toolchain encoding table and its generated corpus, both
	// produced from Arm's official ISA description, and the golden test
	// pins every corpus line of the covered classes.
	{Name: "ZCLASTA", Summary: "Conditionally extract the last active element, vector to vector",
		Word: 0x05288000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualNone, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCLASTA; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCLASTB", Summary: "Conditionally extract the last active element from the bottom, vector to vector",
		Word: 0x05298000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualNone, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCLASTB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPEQ", Summary: "Compare equal, writing a zeroing predicate",
		Word: 0x2400a000, Form: ExtFormCompare, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPEQ; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPEQ", Summary: "Compare equal against wide magnitudes, writing a zeroing predicate",
		Word: 0x24002000, Form: ExtFormCompareWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPEQ; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPGE", Summary: "Compare greater or equal signed, writing a zeroing predicate",
		Word: 0x24008000, Form: ExtFormCompare, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPGE; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPGE", Summary: "Compare greater or equal signed against wide magnitudes, writing a zeroing predicate",
		Word: 0x24004000, Form: ExtFormCompareWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPGE; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPGT", Summary: "Compare greater signed, writing a zeroing predicate",
		Word: 0x24008010, Form: ExtFormCompare, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPGT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPGT", Summary: "Compare greater signed against wide magnitudes, writing a zeroing predicate",
		Word: 0x24004010, Form: ExtFormCompareWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPGT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPHI", Summary: "Compare higher unsigned, writing a zeroing predicate",
		Word: 0x24000010, Form: ExtFormCompare, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPHI; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPHI", Summary: "Compare higher unsigned against wide magnitudes, writing a zeroing predicate",
		Word: 0x2400c010, Form: ExtFormCompareWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPHI; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPHS", Summary: "Compare higher or same unsigned, writing a zeroing predicate",
		Word: 0x24000000, Form: ExtFormCompare, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPHS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPHS", Summary: "Compare higher or same unsigned against wide magnitudes, writing a zeroing predicate",
		Word: 0x2400c000, Form: ExtFormCompareWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPHS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPNE", Summary: "Compare not equal, writing a zeroing predicate",
		Word: 0x2400a010, Form: ExtFormCompare, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPNE; inst_gen.go + arm64sveenc.s"},
	{Name: "ZCMPNE", Summary: "Compare not equal against wide magnitudes, writing a zeroing predicate",
		Word: 0x24002010, Form: ExtFormCompareWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ZCMPNE; inst_gen.go + arm64sveenc.s"},

	// --- the vector-length arithmetic pseudo group ----------------------------
	//
	// ADDVL, ADDPL and RDVL over the signed imm6 multiple of the vector
	// length or the parameter register.  Provenance as above: the toolchain
	// encoding table and its generated corpus, both produced from Arm's
	// official ISA description, and the golden test pins every corpus line
	// of the family.
	{Name: "ADDPL", Summary: "Add a signed multiple of the parameter register count to a register",
		Word: 0x04605000, Form: ExtFormVLArith, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ADDPL; inst_gen.go + arm64sveenc.s"},
	{Name: "ADDVL", Summary: "Add a signed multiple of the vector length to a register",
		Word: 0x04205000, Form: ExtFormVLArith, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ADDVL; inst_gen.go + arm64sveenc.s"},
	{Name: "RDVL", Summary: "Read the vector length multiplied by a signed immediate",
		Word: 0x04bf5000, Form: ExtFormVLRead, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: RDVL; inst_gen.go + arm64sveenc.s"},
	// --- the SVE multiple-structure loads and stores --------------------------
	//
	// The two-, three- and four-register list loads and stores over the
	// two-general-register addressing mode, the shift scaling the base by
	// the list element size.  The list operand carries consecutive
	// registers under one arrangement; the encoding takes the first alone
	// and the conversion validates the rest against the instruction's own
	// digit.  The MUL VL immediate-offset variant of the same shapes stays
	// unwired.  Provenance as above: the toolchain encoding table and its
	// generated corpus, both produced from Arm's official ISA description.
	{Name: "ZLD2B", Summary: "Load 2 scalable vector registers, .B list",
		Word: 0xa420c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD2B (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD2D", Summary: "Load 2 scalable vector registers, .D list",
		Word: 0xa5a0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD2D (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD2H", Summary: "Load 2 scalable vector registers, .H list",
		Word: 0xa4a0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD2H (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD2Q", Summary: "Load 2 scalable vector registers, .Q list",
		Word: 0xa4a08000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD2Q (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD2W", Summary: "Load 2 scalable vector registers, .W list",
		Word: 0xa520c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD2W (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD3B", Summary: "Load 3 scalable vector registers, .B list",
		Word: 0xa440c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD3B (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD3D", Summary: "Load 3 scalable vector registers, .D list",
		Word: 0xa5c0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD3D (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD3H", Summary: "Load 3 scalable vector registers, .H list",
		Word: 0xa4c0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD3H (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD3Q", Summary: "Load 3 scalable vector registers, .Q list",
		Word: 0xa5208000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD3Q (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD3W", Summary: "Load 3 scalable vector registers, .W list",
		Word: 0xa540c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD3W (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD4B", Summary: "Load 4 scalable vector registers, .B list",
		Word: 0xa460c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD4B (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD4D", Summary: "Load 4 scalable vector registers, .D list",
		Word: 0xa5e0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD4D (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD4H", Summary: "Load 4 scalable vector registers, .H list",
		Word: 0xa4e0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD4H (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD4Q", Summary: "Load 4 scalable vector registers, .Q list",
		Word: 0xa5a08000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD4Q (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD4W", Summary: "Load 4 scalable vector registers, .W list",
		Word: 0xa560c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZLD4W (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST2B", Summary: "Store 2 scalable vector registers, .B list",
		Word: 0xe4206000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST2B (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST2D", Summary: "Store 2 scalable vector registers, .D list",
		Word: 0xe5a06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST2D (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST2H", Summary: "Store 2 scalable vector registers, .H list",
		Word: 0xe4a06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST2H (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST2Q", Summary: "Store 2 scalable vector registers, .Q list",
		Word: 0xe4600000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST2Q (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST2W", Summary: "Store 2 scalable vector registers, .W list",
		Word: 0xe5206000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST2W (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST3B", Summary: "Store 3 scalable vector registers, .B list",
		Word: 0xe4406000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST3B (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST3D", Summary: "Store 3 scalable vector registers, .D list",
		Word: 0xe5c06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST3D (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST3H", Summary: "Store 3 scalable vector registers, .H list",
		Word: 0xe4c06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST3H (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST3Q", Summary: "Store 3 scalable vector registers, .Q list",
		Word: 0xe4a00000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST3Q (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST3W", Summary: "Store 3 scalable vector registers, .W list",
		Word: 0xe5406000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST3W (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST4B", Summary: "Store 4 scalable vector registers, .B list",
		Word: 0xe4606000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST4B (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST4D", Summary: "Store 4 scalable vector registers, .D list",
		Word: 0xe5e06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST4D (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST4H", Summary: "Store 4 scalable vector registers, .H list",
		Word: 0xe4e06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST4H (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST4Q", Summary: "Store 4 scalable vector registers, .Q list",
		Word: 0xe4e00000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST4Q (multiple structures); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST4W", Summary: "Store 4 scalable vector registers, .W list",
		Word: 0xe5606000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: ZST4W (multiple structures); inst_gen.go + arm64sveenc.s"},

	// --- the SVE2 crypto family ----------------------------------------------
	//
	// The multi-precision carry steps (ADCLB, ADCLT, SBCLB, SBCLT), the SHA3
	// rotate (RAX1), the SM4 round and key (SM4E, SM4EKEY) and the AES round
	// and mix columns (AESD, AESE, AESIMC, AESMC).  Every arrangement is
	// locked into the word: .D for the carry steps and RAX1, .S for SM4, .B
	// for AES.  Provenance as above: the toolchain encoding table and its
	// generated corpus, both produced from Arm's official ISA description,
	// and the golden test pins every corpus line of the family.
	{Name: "ZADCLB", Summary: "Add vectors with carry, borrowing from a scalar, low half",
		Word: 0x4540d000, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ADCLB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZADCLT", Summary: "Add vectors with carry, borrowing from a scalar, top half",
		Word: 0x4540d400, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ADCLT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSBCLB", Summary: "Subtract vectors with borrow, propagating a scalar, low half",
		Word: 0x45c0d000, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SBCLOB/SBCLB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSBCLT", Summary: "Subtract vectors with borrow, propagating a scalar, top half",
		Word: 0x45c0d400, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SBCLOT/SBCLT; inst_gen.go + arm64sveenc.s"},
	{Name: "ZRAX1", Summary: "SHA3 rotate and exclusive-or one quadword",
		Word: 0x4520f400, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: RAX1; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSM4EKEY", Summary: "SM4 key expansion round over vector elements",
		Word: 0x4520f000, Form: ExtFormVectorsZm, Arr: ExtArrS, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SM4EKEY; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSM4E", Summary: "SM4 encryption round over vector elements",
		Word: 0x4523e000, Form: ExtFormZReadBack, Arr: ExtArrS, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SM4E; inst_gen.go + arm64sveenc.s"},
	{Name: "ZAESD", Summary: "AES decryption round over vector elements",
		Word: 0x4522e400, Form: ExtFormZReadBack, Arr: ExtArrB, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: AESD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZAESE", Summary: "AES encryption round over vector elements",
		Word: 0x4522e000, Form: ExtFormZReadBack, Arr: ExtArrB, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: AESE; inst_gen.go + arm64sveenc.s"},
	{Name: "ZAESIMC", Summary: "AES inverse mix columns over vector elements",
		Word: 0x4520e400, Form: ExtFormZSameReg, Arr: ExtArrB, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: AESIMC; inst_gen.go + arm64sveenc.s"},
	{Name: "ZAESMC", Summary: "AES mix columns over vector elements",
		Word: 0x4520e000, Form: ExtFormZSameReg, Arr: ExtArrB, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: AESMC; inst_gen.go + arm64sveenc.s"},

	// --- the SVE predicate counters and loop terminators -----------------------
	//
	// The count of active elements into a scalar (CNTP, PFIRSTP, PLASTP), the
	// predicate-counter steps whose scalar result the class drops (DECP, INCP
	// and the saturating variants) or writes back (the W spellings), and the
	// while-terminators CTERMEQ and CTERMNE that close SVE2 while-loops.  The
	// 32-bit while compares carry a W suffix and one bit of their own; the
	// pattern-immediate forms of CNTP and WHILE (SVE2.1) are not yet in the
	// layer.  Provenance as above, pinned by the golden test.
	{Name: "CTERMEQ", Summary: "Terminate a while-loop when the counters are equal",
		Word: 0x25e02000, Form: ExtFormCTerm, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: CTERMEQ; inst_gen.go + arm64sveenc.s"},
	{Name: "CTERMEQW", Summary: "Terminate a while-loop when the 32-bit counters are equal",
		Word: 0x25a02000, Form: ExtFormCTerm, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: CTERMEQ (32-bit); inst_gen.go + arm64sveenc.s"},
	{Name: "CTERMNE", Summary: "Terminate a while-loop when the counters differ",
		Word: 0x25e02030, Form: ExtFormCTerm, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: CTERMNE; inst_gen.go + arm64sveenc.s"},
	{Name: "CTERMNEW", Summary: "Terminate a while-loop when the 32-bit counters differ",
		Word: 0x25a02030, Form: ExtFormCTerm, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: CTERMNE (32-bit); inst_gen.go + arm64sveenc.s"},
	{Name: "PCNTP", Summary: "Count the active elements of a predicate into a register",
		Word: 0x25208000, Form: ExtFormCountP, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: CNTP as PCNTP; inst_gen.go + arm64sveenc.s"},
	{Name: "PFIRSTP", Summary: "Write one when the first element of a predicate is active",
		Word: 0x25218000, Form: ExtFormCountP, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PFIRSTP; inst_gen.go + arm64sveenc.s"},
	{Name: "PLASTP", Summary: "Write one when the last element of a predicate is active",
		Word: 0x25228000, Form: ExtFormCountP, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: PLASTP; inst_gen.go + arm64sveenc.s"},
	{Name: "PDECP", Summary: "Decrement a predicate counter by its active elements",
		Word: 0x252d8800, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: DECP (predicate) as PDECP; inst_gen.go + arm64sveenc.s"},
	{Name: "PINCP", Summary: "Increment a predicate counter by its active elements",
		Word: 0x252c8800, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J SVE2.1: INCP (predicate) as PINCP; inst_gen.go + arm64sveenc.s"},
	{Name: "PSQDECP", Summary: "Decrement a predicate counter, saturating signed",
		Word: 0x252a8c00, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J: SQDECP (predicate) as PSQDECP; inst_gen.go + arm64sveenc.s"},
	{Name: "PSQINCP", Summary: "Increment a predicate counter, saturating signed",
		Word: 0x25288c00, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J: SQINCP (predicate) as PSQINCP; inst_gen.go + arm64sveenc.s"},
	{Name: "PUQDECP", Summary: "Decrement a predicate counter, saturating unsigned",
		Word: 0x252b8c00, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J: UQDECP (predicate) as PUQDECP; inst_gen.go + arm64sveenc.s"},
	{Name: "PUQINCP", Summary: "Increment a predicate counter, saturating unsigned",
		Word: 0x25298c00, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J: UQINCP (predicate) as PUQINCP; inst_gen.go + arm64sveenc.s"},
	{Name: "PUQDECPW", Summary: "Decrement a predicate counter, saturating unsigned, 32-bit",
		Word: 0x252b8800, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J: UQDECP (predicate, 32-bit) as PUQDECPW; inst_gen.go + arm64sveenc.s"},
	{Name: "PUQINCPW", Summary: "Increment a predicate counter, saturating unsigned, 32-bit",
		Word: 0x25298800, Form: ExtFormCountPn, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
		Ref: "ARM DDI 0487J: UQINCP (predicate, 32-bit) as PUQINCPW; inst_gen.go + arm64sveenc.s"},
	{Name: "PSQDECPW", Summary: "Decrement a register by a predicate's active elements, saturating signed",
		Word: 0x252a8800, Form: ExtFormCountPnW, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SQDECP (scalar, 32-bit) as PSQDECPW; inst_gen.go + arm64sveenc.s"},
	{Name: "PSQINCPW", Summary: "Increment a register by a predicate's active elements, saturating signed",
		Word: 0x25288800, Form: ExtFormCountPnW, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SQINCP (scalar, 32-bit) as PSQINCPW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEGEW", Summary: "Build a predicate while the signed 32-bit comparison holds",
		Word: 0x25200000, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEGE (32-bit) as PWHILEGEW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEGTW", Summary: "Build a predicate while the signed 32-bit comparison holds",
		Word: 0x25200010, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEGT (32-bit) as PWHILEGTW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEHIW", Summary: "Build a predicate while the unsigned 32-bit comparison holds",
		Word: 0x25200810, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEHI (32-bit) as PWHILEHIW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILEHSW", Summary: "Build a predicate while the unsigned 32-bit comparison holds",
		Word: 0x25200800, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILEHS (32-bit) as PWHILEHSW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELEW", Summary: "Build a predicate while the signed 32-bit comparison holds",
		Word: 0x25200410, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELE (32-bit) as PWHILELEW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELOW", Summary: "Build a predicate while the unsigned 32-bit comparison holds",
		Word: 0x25200c00, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELO (32-bit) as PWHILELOW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELSW", Summary: "Build a predicate while the unsigned 32-bit comparison holds",
		Word: 0x25200c10, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELS (32-bit) as PWHILELSW; inst_gen.go + arm64sveenc.s"},
	{Name: "PWHILELTW", Summary: "Build a predicate while the signed 32-bit comparison holds",
		Word: 0x25200400, Form: ExtFormWhile, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: WHILELT (32-bit) as PWHILELTW; inst_gen.go + arm64sveenc.s"},

	// --- the SVE reductions ----------------------------------------------------
	//
	// The integer, bitwise and floating-point reductions into the low lanes
	// of a SIMD register: ANDV, EORV and ORV (SVE2), SADDV and UADDV with
	// their D-sized accumulator, the maxima and minima, and the FP sums,
	// maxima and minima including FADDA's strict accumulation.  The size is
	// baked into the mnemonic and the word for every family but SADDV and
	// UADDV, where the source's arrangement carries it.
	{Name: "ZSADDVD", Summary: "Signed sum of the active elements into a SIMD register",
		Word: 0x04002000, Form: ExtFormReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SADDV as ZSADDVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUADDVD", Summary: "Unsigned sum of the active elements into a SIMD register",
		Word: 0x04012000, Form: ExtFormReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UADDV as ZUADDVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZANDVB", Summary: "Bitwise and of the active elements",
		Word: 0x041a2000, Form: ExtFormReduce, Arr: ExtArrB, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ANDV as ZANDVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZANDVH", Summary: "Bitwise and of the active elements",
		Word: 0x045a2000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ANDV as ZANDVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZANDVS", Summary: "Bitwise and of the active elements",
		Word: 0x049a2000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ANDV as ZANDVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZANDVD", Summary: "Bitwise and of the active elements",
		Word: 0x04da2000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ANDV as ZANDVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEORVB", Summary: "Bitwise exclusive-or of the active elements",
		Word: 0x04192000, Form: ExtFormReduce, Arr: ExtArrB, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: EORV as ZEORVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEORVH", Summary: "Bitwise exclusive-or of the active elements",
		Word: 0x04592000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: EORV as ZEORVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEORVS", Summary: "Bitwise exclusive-or of the active elements",
		Word: 0x04992000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: EORV as ZEORVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZEORVD", Summary: "Bitwise exclusive-or of the active elements",
		Word: 0x04d92000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: EORV as ZEORVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZORVB", Summary: "Bitwise or of the active elements",
		Word: 0x04182000, Form: ExtFormReduce, Arr: ExtArrB, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ORV as ZORVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZORVH", Summary: "Bitwise or of the active elements",
		Word: 0x04582000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ORV as ZORVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZORVS", Summary: "Bitwise or of the active elements",
		Word: 0x04982000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ORV as ZORVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZORVD", Summary: "Bitwise or of the active elements",
		Word: 0x04d82000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ORV as ZORVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMAXVB", Summary: "Signed maximum of the active byte elements",
		Word: 0x04082000, Form: ExtFormReduce, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMAXV as ZSMAXVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMAXVH", Summary: "Signed maximum of the active halfword elements",
		Word: 0x04482000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMAXV as ZSMAXVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMAXVS", Summary: "Signed maximum of the active word elements",
		Word: 0x04882000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMAXV as ZSMAXVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMAXVD", Summary: "Signed maximum of the active doubleword elements",
		Word: 0x04c82000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMAXV as ZSMAXVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMINVB", Summary: "Signed minimum of the active byte elements",
		Word: 0x040a2000, Form: ExtFormReduce, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMINV as ZSMINVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMINVH", Summary: "Signed minimum of the active halfword elements",
		Word: 0x044a2000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMINV as ZSMINVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMINVS", Summary: "Signed minimum of the active word elements",
		Word: 0x048a2000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMINV as ZSMINVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZSMINVD", Summary: "Signed minimum of the active doubleword elements",
		Word: 0x04ca2000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: SMINV as ZSMINVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMAXVB", Summary: "Unsigned maximum of the active byte elements",
		Word: 0x04092000, Form: ExtFormReduce, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMAXV as ZUMAXVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMAXVH", Summary: "Unsigned maximum of the active halfword elements",
		Word: 0x04492000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMAXV as ZUMAXVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMAXVS", Summary: "Unsigned maximum of the active word elements",
		Word: 0x04892000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMAXV as ZUMAXVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMAXVD", Summary: "Unsigned maximum of the active doubleword elements",
		Word: 0x04c92000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMAXV as ZUMAXVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMINVB", Summary: "Unsigned minimum of the active byte elements",
		Word: 0x040b2000, Form: ExtFormReduce, Arr: ExtArrB, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMINV as ZUMINVB; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMINVH", Summary: "Unsigned minimum of the active halfword elements",
		Word: 0x044b2000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMINV as ZUMINVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMINVS", Summary: "Unsigned minimum of the active word elements",
		Word: 0x048b2000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMINV as ZUMINVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZUMINVD", Summary: "Unsigned minimum of the active doubleword elements",
		Word: 0x04cb2000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: UMINV as ZUMINVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFADDVH", Summary: "Floating-point sum of the active halfword elements",
		Word: 0x65402000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FADDV as ZFADDVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFADDVS", Summary: "Floating-point sum of the active word elements",
		Word: 0x65802000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FADDV as ZFADDVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFADDVD", Summary: "Floating-point sum of the active doubleword elements",
		Word: 0x65c02000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FADDV as ZFADDVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXNMVH", Summary: "Floating-point maximum of the active halfword elements, quiet NaN",
		Word: 0x65442000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMAXNMV as ZFMAXNMVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXNMVS", Summary: "Floating-point maximum of the active word elements, quiet NaN",
		Word: 0x65842000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMAXNMV as ZFMAXNMVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXNMVD", Summary: "Floating-point maximum of the active doubleword elements, quiet NaN",
		Word: 0x65c42000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMAXNMV as ZFMAXNMVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXVH", Summary: "Floating-point maximum of the active halfword elements",
		Word: 0x65462000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMAXV as ZFMAXVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXVS", Summary: "Floating-point maximum of the active word elements",
		Word: 0x65862000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMAXV as ZFMAXVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMAXVD", Summary: "Floating-point maximum of the active doubleword elements",
		Word: 0x65c62000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMAXV as ZFMAXVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINNMVH", Summary: "Floating-point minimum of the active halfword elements, quiet NaN",
		Word: 0x65452000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMINNMV as ZFMINNMVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINNMVS", Summary: "Floating-point minimum of the active word elements, quiet NaN",
		Word: 0x65852000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMINNMV as ZFMINNMVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINNMVD", Summary: "Floating-point minimum of the active doubleword elements, quiet NaN",
		Word: 0x65c52000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMINNMV as ZFMINNMVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINVH", Summary: "Floating-point minimum of the active halfword elements",
		Word: 0x65472000, Form: ExtFormReduce, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMINV as ZFMINVH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINVS", Summary: "Floating-point minimum of the active word elements",
		Word: 0x65872000, Form: ExtFormReduce, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMINV as ZFMINVS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFMINVD", Summary: "Floating-point minimum of the active doubleword elements",
		Word: 0x65c72000, Form: ExtFormReduce, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FMINV as ZFMINVD; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFADDAH", Summary: "Strict floating-point accumulation of the active halfword elements",
		Word: 0x65582000, Form: ExtFormReduceReadBack, Arr: ExtArrH, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FADDA as ZFADDAH; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFADDAS", Summary: "Strict floating-point accumulation of the active word elements",
		Word: 0x65982000, Form: ExtFormReduceReadBack, Arr: ExtArrS, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FADDA as ZFADDAS; inst_gen.go + arm64sveenc.s"},
	{Name: "ZFADDAD", Summary: "Strict floating-point accumulation of the active doubleword elements",
		Word: 0x65d82000, Form: ExtFormReduceReadBack, Arr: ExtArrD, Feature: ExtFeatureSVE,
		Ref: "ARM DDI 0487J: FADDA as ZFADDAD; inst_gen.go + arm64sveenc.s"},

	// --- the SVE gather loads and scatter stores --------------------------------
	//
	// The core addressing modes of the gather/scatter family over the plain,
	// sign-extended and first-fault loads and the stores: the two-general-
	// register pair (Rn{<<s})(Rm), the vector base with a general offset
	// (Zn.T{<<s})(Rm), the extended 32-bit offsets (Zn.S.UXTW{<<s})(Rm), the
	// immediate offset imm(Zn.T) whose displacement the encoder scales by the
	// access size into imm5, and the lone vector base (Zn.T) of the stores.
	// Every row is one corpus line with its operand fields masked out; the
	// list arrangement is part of the gather's identity (the offset index
	// size) and rides Arr locked.  The multi-register lists, the
	// non-temporal and replicate forms, the prefetches, the VL-scaled
	// offsets and the predicate-destination forms stay outside this stage.
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0xa4004000, Form: ExtFormSveLoad, Arr: ExtArrB, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0xa4204000, Form: ExtFormSveLoad, Arr: ExtArrH, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0xa4404000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0xa4604000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0xc440c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0x84004000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1D", Summary: "Gather-load doublewords to the active lanes",
		Word: 0xa5e04000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 3, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1D", Summary: "Gather-load doublewords to the active lanes",
		Word: 0xa5808000, Form: ExtFormSveLoad, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 3, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1D", Summary: "Gather-load doublewords to the active lanes",
		Word: 0xc5e0c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 3, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1D", Summary: "Gather-load doublewords to the active lanes",
		Word: 0xc5c0c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0xa4a04000, Form: ExtFormSveLoad, Arr: ExtArrH, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0xa4c04000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0xa4e04000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0x84a04000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0xc4e0c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0xc4c0c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0x84804000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SB", Summary: "Gather-load sign-extended bytes to the active lanes",
		Word: 0xa5c04000, Form: ExtFormSveLoad, Arr: ExtArrH, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SB", Summary: "Gather-load sign-extended bytes to the active lanes",
		Word: 0xa5a04000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SB", Summary: "Gather-load sign-extended bytes to the active lanes",
		Word: 0xa5804000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SB", Summary: "Gather-load sign-extended bytes to the active lanes",
		Word: 0xc4408000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SB", Summary: "Gather-load sign-extended bytes to the active lanes",
		Word: 0x84000000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0xa5204000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0xa5004000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0x84a00000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0xc4e08000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0xc4c08000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0x84800000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SW", Summary: "Gather-load sign-extended words to the active lanes",
		Word: 0xa4804000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SW", Summary: "Gather-load sign-extended words to the active lanes",
		Word: 0xc5608000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SW", Summary: "Gather-load sign-extended words to the active lanes",
		Word: 0xc5408000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0xa5404000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0xa5604000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0xa5008000, Form: ExtFormSveLoad, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0x85204000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 2, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0xc560c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0xc540c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0x85004000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0xa4006000, Form: ExtFormSveLoad, Arr: ExtArrB, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0xa4206000, Form: ExtFormSveLoad, Arr: ExtArrH, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0xa4406000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0xa4606000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0xc440e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0x84006000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1D", Summary: "First-fault gather-load doublewords to the active lanes",
		Word: 0xa5e06000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 3, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1D", Summary: "First-fault gather-load doublewords to the active lanes",
		Word: 0xc5e0e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 3, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1D", Summary: "First-fault gather-load doublewords to the active lanes",
		Word: 0xc5c0e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0xa4a06000, Form: ExtFormSveLoad, Arr: ExtArrH, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0xa4c06000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0xa4e06000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0x84a06000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0xc4e0e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0xc4c0e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0x84806000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SB", Summary: "First-fault gather-load sign-extended bytes",
		Word: 0xa5c06000, Form: ExtFormSveLoad, Arr: ExtArrH, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SB", Summary: "First-fault gather-load sign-extended bytes",
		Word: 0xa5a06000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SB", Summary: "First-fault gather-load sign-extended bytes",
		Word: 0xa5806000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SB", Summary: "First-fault gather-load sign-extended bytes",
		Word: 0xc440a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SB", Summary: "First-fault gather-load sign-extended bytes",
		Word: 0x84002000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0xa5206000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0xa5006000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0x84a02000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0xc4e0a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0xc4c0a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0x84802000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SW", Summary: "First-fault gather-load sign-extended words",
		Word: 0xa4806000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SW", Summary: "First-fault gather-load sign-extended words",
		Word: 0xc560a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SW", Summary: "First-fault gather-load sign-extended words",
		Word: 0xc540a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0xa5406000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0xa5606000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0x85206000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 2, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0xc560e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0xc540e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0x85006000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1B", Summary: "Scatter-store bytes from the active lanes",
		Word: 0xe4604000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 0, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1B", Summary: "Scatter-store bytes from the active lanes",
		Word: 0xe4008000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1B", Summary: "Scatter-store bytes from the active lanes",
		Word: 0xe4408000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1B", Summary: "Scatter-store bytes from the active lanes",
		Word: 0xe400a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1D", Summary: "Scatter-store doublewords from the active lanes",
		Word: 0xe5e04000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 3, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1D", Summary: "Scatter-store doublewords from the active lanes",
		Word: 0xe5c04000, Form: ExtFormSveStore, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 3, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1D", Summary: "Scatter-store doublewords from the active lanes",
		Word: 0xe5a08000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 3, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1D", Summary: "Scatter-store doublewords from the active lanes",
		Word: 0xe5808000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1D", Summary: "Scatter-store doublewords from the active lanes",
		Word: 0xe5a0a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 3, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1D", Summary: "Scatter-store doublewords from the active lanes",
		Word: 0xe580a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4e04000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 1, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4e08000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4a08000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4808000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4c08000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4a0a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe480a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe5604000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe5004000, Form: ExtFormSveStore, Arr: ExtArrQ, Feature: ExtFeatureSVE,
		SveMode: extMemPair, SveShift: 2, SveBase: ExtArrNone,
		Ref: "ARM DDI 0487J: gather/scatter (two general registers); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe5608000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 2, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe5208000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe5008000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe5408000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemExt32, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (extended 32-bit offsets); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe520a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe500a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecOff, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0x8420c000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1B", Summary: "Gather-load bytes to the active lanes",
		Word: 0xc420c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1D", Summary: "Gather-load doublewords to the active lanes",
		Word: 0xc5a0c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 3, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0x84a0c000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1H", Summary: "Gather-load halfwords to the active lanes",
		Word: 0xc4a0c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SB", Summary: "Gather-load sign-extended bytes to the active lanes",
		Word: 0x84208000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SB", Summary: "Gather-load sign-extended bytes to the active lanes",
		Word: 0xc4208000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0x84a08000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SH", Summary: "Gather-load sign-extended halfwords to the active lanes",
		Word: 0xc4a08000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1SW", Summary: "Gather-load sign-extended words to the active lanes",
		Word: 0xc5208000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0x8520c000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 2, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLD1W", Summary: "Gather-load words to the active lanes",
		Word: 0xc520c000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0x8420e000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1B", Summary: "First-fault gather-load bytes to the active lanes",
		Word: 0xc420e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1D", Summary: "First-fault gather-load doublewords to the active lanes",
		Word: 0xc5a0e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 3, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0x84a0e000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1H", Summary: "First-fault gather-load halfwords to the active lanes",
		Word: 0xc4a0e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SB", Summary: "First-fault gather-load sign-extended bytes",
		Word: 0x8420a000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SB", Summary: "First-fault gather-load sign-extended bytes",
		Word: 0xc420a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0x84a0a000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SH", Summary: "First-fault gather-load sign-extended halfwords",
		Word: 0xc4a0a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1SW", Summary: "First-fault gather-load sign-extended words",
		Word: 0xc520a000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0x8520e000, Form: ExtFormSveLoad, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 2, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZLDFF1W", Summary: "First-fault gather-load words to the active lanes",
		Word: 0xc520e000, Form: ExtFormSveLoad, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 2, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1B", Summary: "Scatter-store bytes from the active lanes",
		Word: 0xe460a000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1B", Summary: "Scatter-store bytes from the active lanes",
		Word: 0xe440a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1D", Summary: "Scatter-store doublewords from the active lanes",
		Word: 0xe5c0a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecBase, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base alone); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4e0a000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1H", Summary: "Scatter-store halfwords from the active lanes",
		Word: 0xe4c0a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemImm, SveShift: 1, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (immediate offset); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe560a000, Form: ExtFormSveStore, Arr: ExtArrS, Feature: ExtFeatureSVE,
		SveMode: extMemVecBase, SveShift: 0, SveBase: ExtArrS,
		Ref: "ARM DDI 0487J: gather/scatter (vector base alone); inst_gen.go + arm64sveenc.s"},
	{Name: "ZST1W", Summary: "Scatter-store words from the active lanes",
		Word: 0xe540a000, Form: ExtFormSveStore, Arr: ExtArrD, Feature: ExtFeatureSVE,
		SveMode: extMemVecBase, SveShift: 0, SveBase: ExtArrD,
		Ref: "ARM DDI 0487J: gather/scatter (vector base alone); inst_gen.go + arm64sveenc.s"},
	// The shift-immediate classes: the SVE2 narrowing and widening
	// three-vector shifts and the predicated saturating left shifts.  The
	// amount rides the class's tsz:imm3 fields, whose tsz bits double as
	// the arrangement spelling: right shifts take C = 2 x esize - amount
	// over the destination's element size, left shifts C = esize + amount
	// over the source's (or the destination's own, in the predicated
	// class), and C splits imm3, a two-bit tsz chunk and a one- or
	// two-bit tsz top.  Provenance as above: the toolchain encoding table
	// and its generated corpus, both produced from Arm's official ISA
	// description, and the golden test pins every corpus line of the
	// covered classes.
	{Name: "ZSQSHRUNB", Summary: "Shift right narrowing, unsigned results from signed, bottom",
		Word: 0x45200000, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQSHRUN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQSHRUNT", Summary: "Shift right narrowing, unsigned results from signed, top",
		Word: 0x45200400, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQSHRUN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSHRNB", Summary: "Shift right narrowing by immediate, bottom",
		Word: 0x45201000, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSHRNT", Summary: "Shift right narrowing by immediate, top",
		Word: 0x45201400, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZRSHRNB", Summary: "Rounding shift right narrowing by immediate, bottom",
		Word: 0x45201800, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: RSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZRSHRNT", Summary: "Rounding shift right narrowing by immediate, top",
		Word: 0x45201c00, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: RSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQSHRNB", Summary: "Saturating signed shift right narrowing by immediate, bottom",
		Word: 0x45202000, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQSHRNT", Summary: "Saturating signed shift right narrowing by immediate, top",
		Word: 0x45202400, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQRSHRNB", Summary: "Saturating rounding signed shift right narrowing by immediate, bottom",
		Word: 0x45202800, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQRSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQRSHRNT", Summary: "Saturating rounding signed shift right narrowing by immediate, top",
		Word: 0x45202c00, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQRSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUQSHRNB", Summary: "Saturating unsigned shift right narrowing by immediate, bottom",
		Word: 0x45203000, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: UQSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUQSHRNT", Summary: "Saturating unsigned shift right narrowing by immediate, top",
		Word: 0x45203400, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: UQSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUQRSHRNB", Summary: "Saturating rounding unsigned shift right narrowing by immediate, bottom",
		Word: 0x45203800, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: UQRSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUQRSHRNT", Summary: "Saturating rounding unsigned shift right narrowing by immediate, top",
		Word: 0x45203c00, Form: ExtFormShiftImmNarrow, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: UQRSHRN (narrowing, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSSHLLB", Summary: "Signed shift left widening by immediate, bottom",
		Word: 0x4500a000, Form: ExtFormShiftImmWide, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SSHLL (widening, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSSHLLT", Summary: "Signed shift left widening by immediate, top",
		Word: 0x4500a400, Form: ExtFormShiftImmWide, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SSHLL (widening, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUSHLLB", Summary: "Unsigned shift left widening by immediate, bottom",
		Word: 0x4500a800, Form: ExtFormShiftImmWide, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: USHLL (widening, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUSHLLT", Summary: "Unsigned shift left widening by immediate, top",
		Word: 0x4500ac00, Form: ExtFormShiftImmWide, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: USHLL (widening, immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQSHL", Summary: "Saturating signed shift left by immediate, over a governing predicate",
		Word: 0x04068000, Form: ExtFormShiftImmPred, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQSHL (immediate, predicated); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSQSHLU", Summary: "Saturating signed shift left by immediate, unsigned bases, over a governing predicate",
		Word: 0x040f8000, Form: ExtFormShiftImmPred, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SQSHLU (immediate, predicated); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUQSHL", Summary: "Saturating unsigned shift left by immediate, over a governing predicate",
		Word: 0x04078000, Form: ExtFormShiftImmPred, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: UQSHL (immediate, predicated); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSRI", Summary: "Shift right and insert by immediate",
		Word: 0x4500f000, Form: ExtFormShiftImmSame, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SRI (immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZASR", Summary: "Arithmetic shift right by immediate",
		Word: 0x04209000, Form: ExtFormShiftImmSame, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ASR (immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSSRA", Summary: "Signed shift right and accumulate by immediate",
		Word: 0x4500e000, Form: ExtFormShiftImmSame, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SSRA (immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZUSRA", Summary: "Unsigned shift right and accumulate by immediate",
		Word: 0x4500e400, Form: ExtFormShiftImmSame, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: USRA (immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZSRSRA", Summary: "Signed rounding shift right and accumulate by immediate",
		Word: 0x4500e800, Form: ExtFormShiftImmSame, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: SRSRA (immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZURSRA", Summary: "Unsigned rounding shift right and accumulate by immediate",
		Word: 0x4500ec00, Form: ExtFormShiftImmSame, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: URSRA (immediate); inst_gen.go + arm64sveenc.s"},
	{Name: "ZASR", Summary: "Arithmetic shift right by immediate, over a governing predicate",
		Word: 0x04008000, Form: ExtFormShiftImmPredRight, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ASR (immediate, predicated); inst_gen.go + arm64sveenc.s"},
	{Name: "ZASRD", Summary: "Arithmetic shift right by immediate, rounding, over a governing predicate",
		Word: 0x04048000, Form: ExtFormShiftImmPredRight, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: ASRD (immediate, predicated); inst_gen.go + arm64sveenc.s"},
	{Name: "ZXAR", Summary: "Extract and narrow by immediate from three sources",
		Word: 0x04203400, Form: ExtFormShiftImmXar, Feature: ExtFeatureSVE2,
		Ref: "ARM DDI 0487J SVE2: XAR; inst_gen.go + arm64sveenc.s"},
}

// Extensions returns the extended-instruction layer registered for a, outside
// the generated tables.  An architecture whose extended layer is not built
// yet returns nothing: the mechanism is ordinary code, not a build tag, and
// it simply offers no instruction where none is registered.
func Extensions(a Arch) []ExtInstr {
	switch a {
	case AMD64:
		return amd64Extensions
	case ARM64:
		return arm64Extensions
	default:
		return nil
	}
}