// Copyright (c) 2026 Petr Balvín (https://petrbalvin.org) // SPDX-License-Identifier: BSD-3-Clause package asm import ( "os" "path/filepath" "testing" ) // TestRISCVScalarFP_Differential proves the scalar single- and // double-precision families against the toolchain: sections 21.6 through // 22.7 of the "F" and "D" specifications' computational, conversion, move, // sign-injection, compare and classify instructions in the toolchain's own // testdata wording, assembled by gasm and by go tool asm must agree word // for word. func TestRISCVScalarFP_Differential(t *testing.T) { src := `#include "textflag.h" TEXT ·fp(SB), NOSPLIT, $0 // 21.6: Single-Precision Floating-Point Computational Instructions FADDS F1, F0, F2 // 53011000 FSUBS F1, F0, F2 // 53011008 FMULS F1, F0, F2 // 53011010 FDIVS F1, F0, F2 // 53011018 FMINS F1, F0, F2 // 53011028 FMAXS F1, F0, F2 // 53111028 FSQRTS F0, F1 // d3000058 // 21.7: Single-Precision Floating-Point Conversion and Move Instructions FCVTWS F0, X5 // d31200c0 FCVTWS.RNE F0, X5 // d30200c0 FCVTWS.RTZ F0, X5 // d31200c0 FCVTWS.RDN F0, X5 // d32200c0 FCVTWS.RUP F0, X5 // d33200c0 FCVTWS.RMM F0, X5 // d34200c0 FCVTLS F0, X5 // d31220c0 FCVTLS.RNE F0, X5 // d30220c0 FCVTLS.RTZ F0, X5 // d31220c0 FCVTLS.RDN F0, X5 // d32220c0 FCVTLS.RUP F0, X5 // d33220c0 FCVTLS.RMM F0, X5 // d34220c0 FCVTSW X5, F0 // 538002d0 FCVTSL X5, F0 // 538022d0 FCVTWUS F0, X5 // d31210c0 FCVTWUS.RNE F0, X5 // d30210c0 FCVTWUS.RTZ F0, X5 // d31210c0 FCVTWUS.RDN F0, X5 // d32210c0 FCVTWUS.RUP F0, X5 // d33210c0 FCVTWUS.RMM F0, X5 // d34210c0 FCVTLUS F0, X5 // d31230c0 FCVTLUS.RNE F0, X5 // d30230c0 FCVTLUS.RTZ F0, X5 // d31230c0 FCVTLUS.RDN F0, X5 // d32230c0 FCVTLUS.RUP F0, X5 // d33230c0 FCVTLUS.RMM F0, X5 // d34230c0 FCVTSWU X5, F0 // 538012d0 FCVTSLU X5, F0 // 538032d0 FSGNJS F1, F0, F2 // 53011020 FSGNJNS F1, F0, F2 // 53111020 FSGNJXS F1, F0, F2 // 53211020 FMVXS F0, X5 // d30200e0 FMVSX X5, F0 // 538002f0 FMVXW F0, X5 // d30200e0 FMVWX X5, F0 // 538002f0 FMADDS F1, F2, F3, F4 // 43822018 FMSUBS F1, F2, F3, F4 // 47822018 FNMSUBS F1, F2, F3, F4 // 4b822018 FNMADDS F1, F2, F3, F4 // 4f822018 // 21.8: Single-Precision Floating-Point Compare Instructions FEQS F0, F1, X7 // d3a300a0 FLTS F0, F1, X7 // d39300a0 FLES F0, F1, X7 // d38300a0 // 21.9: Single-Precision Floating-Point Classify Instruction FCLASSS F0, X5 // d31200e0 // 22.3: Double-Precision Load and Store Instructions FLD (X5), F0 // 07b00200 FLD 4(X5), F0 // 07b04200 FSD F0, (X5) // 27b00200 FSD F0, 4(X5) // 27b20200 // 22.4: Double-Precision Floating-Point Computational Instructions FADDD F1, F0, F2 // 53011002 FSUBD F1, F0, F2 // 5301100a FMULD F1, F0, F2 // 53011012 FDIVD F1, F0, F2 // 5301101a FMIND F1, F0, F2 // 5301102a FMAXD F1, F0, F2 // 5311102a FSQRTD F0, F1 // d300005a // 22.5: Double-Precision Floating-Point Conversion and Move Instructions FCVTWD F0, X5 // d31200c2 FCVTWD.RNE F0, X5 // d30200c2 FCVTWD.RTZ F0, X5 // d31200c2 FCVTWD.RDN F0, X5 // d32200c2 FCVTWD.RUP F0, X5 // d33200c2 FCVTWD.RMM F0, X5 // d34200c2 FCVTLD F0, X5 // d31220c2 FCVTLD.RNE F0, X5 // d30220c2 FCVTLD.RTZ F0, X5 // d31220c2 FCVTLD.RDN F0, X5 // d32220c2 FCVTLD.RUP F0, X5 // d33220c2 FCVTLD.RMM F0, X5 // d34220c2 FCVTDW X5, F0 // 538002d2 FCVTDL X5, F0 // 538022d2 FCVTWUD F0, X5 // d31210c2 FCVTWUD.RNE F0, X5 // d30210c2 FCVTWUD.RTZ F0, X5 // d31210c2 FCVTWUD.RDN F0, X5 // d32210c2 FCVTWUD.RUP F0, X5 // d33210c2 FCVTWUD.RMM F0, X5 // d34210c2 FCVTLUD F0, X5 // d31230c2 FCVTLUD.RNE F0, X5 // d30230c2 FCVTLUD.RTZ F0, X5 // d31230c2 FCVTLUD.RDN F0, X5 // d32230c2 FCVTLUD.RUP F0, X5 // d33230c2 FCVTLUD.RMM F0, X5 // d34230c2 FCVTDWU X5, F0 // 538012d2 FCVTDLU X5, F0 // 538032d2 FCVTSD F0, F1 // d3001040 FCVTDS F0, F1 // d3000042 FSGNJD F1, F0, F2 // 53011022 FSGNJND F1, F0, F2 // 53111022 FSGNJXD F1, F0, F2 // 53211022 FMVXD F0, X5 // d30200e2 FMVDX X5, F0 // 538002f2 FMADDD F1, F2, F3, F4 // 4382201a FMSUBD F1, F2, F3, F4 // 4782201a FNMSUBD F1, F2, F3, F4 // 4b82201a FNMADDD F1, F2, F3, F4 // 4f82201a // 22.6: Double-Precision Floating-Point Compare Instructions FEQD F0, F1, X7 // d3a300a2 FLTD F0, F1, X7 // d39300a2 FLED F0, F1, X7 // d38300a2 // 22.7: Double-Precision Floating-Point Classify Instruction FCLASSD F0, X5 // d31200e2 RET ` dir := t.TempDir() path := filepath.Join(dir, "fp_riscv64.s") if err := os.WriteFile(path, []byte(src), 0o644); err != nil { t.Fatal(err) } assertRISCVDifferential(t, path, src, "fp") }