// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause

// Seed corpus for FuzzAssembleLOONG64: the branches over their offset range,
// the jumps, the bit-field pair at the msb/lsb boundaries, the ALSL shift
// window, RDTIME, the system instructions, the constant materialisation
// chain and the register-class moves.

#include "textflag.h"

TEXT ·branches(SB), NOSPLIT, $0
	BEQ  R4, R5, b1
	BNE  R4, R5, b2
	BLT  R4, R5, b1
	BGE  R4, R5, b2
	BLTU R4, R5, b1
	BGEU R4, R5, b2
	BEQZ R6, b1
	BNEZ R7, b2
	BLTZ R8, b1
	BGEZ R9, b2
	BLEZ R10, b1
	BGTZ R11, b2
	BFPT b1
	BFPF b2

b1:
	MOVV R1, R2

b2:
	MOVV R2, R1
	BEQ  R4, R5, b1
	RET

TEXT ·jumps(SB), NOSPLIT, $0
	JMP  j1
	JAL  (R30)
	JIRL R0, R4, 8
	JIRL R1, R5, 0
	CALL runtime·morestack_noctxt(SB)

j1:
	JMP  -3(PC)
	RET

TEXT ·bitfield(SB), NOSPLIT, $0
	BSTRINSW  $3, R4, $0, R5
	BSTRINSV  $7, R4, $0, R5
	BSTRINSV  $31, R6, $0, R7
	BSTRINSV  $63, R6, $32, R7
	BSTRPICKW $3, R4, $0, R5
	BSTRPICKV $6, R7, $0, R8
	BSTRPICKV $63, R6, $32, R7
	ALSLW     $1, R4, R5, R6
	ALSLW     $4, R7, R8, R9
	ALSLWU    $3, R4, R5, R6
	ALSLV     $2, R8, R9, R10
	ALSLV     $3, R8, R9, R10
	RET

TEXT ·system(SB), NOSPLIT, $0
	SYSCALL
	DBAR
	DBAR     $0
	BREAK    $0
	BREAK    $32767
	PRELD    0(R4), $0
	PRELD    2047(R4), $31
	RDTIMELW R7, R8
	RDTIMEHW R7, R8
	RDTIMED  R20, R21
	RET

TEXT ·consts(SB), NOSPLIT, $0
	LU12IW    R4, $0x12345
	LU12IW    R5, $-524288
	LU12IW    R6, $1048575
	LU32ID    R7, $-524288
	LU52ID    $-4096, R8, R9
	LU52ID    $4095, R8, R9
	PCALAU12I R10, $0x12345
	PCADDU12I R11, $-524288
	ADDV16    $65536, R11, R12
	ADDV16    $-65536, R11, R12
	MOVV      $0x123456789ABCDEF0, R13
	MOVV      $-1, R14
	RET

TEXT ·regClasses(SB), NOSPLIT, $0
	MOVV R4, F5
	MOVV F6, R7
	MOVW R8, F9
	MOVW F10, R11
	MOVV R12, FCC0
	MOVV FCC1, R13
	MOVV R14, FCSR0
	MOVV FCSR3, R15
	FSEL FCC0, F3, F4, F3
	FSEL FCC1, F1, F2
	RET

TEXT ·memOffsets(SB), NOSPLIT, $0
	MOVB  2047(R4), R5
	MOVB  -2048(R4), R5
	MOVH  2047(R4), R5
	MOVW  2047(R4), R5
	MOVV  2047(R4), R5
	MOVW  2048(R4), R5
	MOVW  -2048(R4), R5
	MOVW  4095(R4), R5
	MOVW  -4096(R4), R5
	MOVW  65536(R4), R5
	MOVW  $4(R4), R5
	MOVV  $4(R4), R5
	MOVBU -1(R4), R5
	MOVHU 2(R4), R5
	MOVWU -3(R4), R5
	MOVF  8(R4), F5
	MOVD  -8(R4), F5
	MOVV  (R4)(R5), R6
	RET