// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause

// Seed corpus for FuzzAssembleRISCV64: the RVC-compressible shapes.  Every
// instruction here has a compressed 16-bit encoding the compression pass may
// pick: the two-operand ALU forms over x8-x15, the stack-pointer loads and
// stores at the scaled offset boundaries, C.ADDI16SP and C.ADDI4SPN ranges,
// the compressed branches and the uncompressible spellings beside them.

#include "textflag.h"

TEXT ·primeALU(SB), NOSPLIT, $0
	ADD  X9, X8, X8
	ADD  X15, X8, X8
	ADDI $1, X8, X8
	ADDI $31, X15, X15
	ADDI $-32, X8, X8
	AND  X9, X8, X8
	ANDI $3, X8, X8
	OR   X10, X9, X9
	XOR  X11, X10, X10
	SUB  X13, X12, X12
	SLLI $2, X8, X8
	SRLI $5, X9, X9
	SRAI $7, X10, X10
	MOV  X9, X8
	MOV  X1, X8
	MOV  X8, X1
	RET

TEXT ·stackOffsets(SB), NOSPLIT, $0
	LW  0(X2), X8
	LW  4(X2), X8
	LW  124(X2), X9
	LW  2044(X2), X10
	LD  0(X2), X8
	LD  8(X2), X8
	LD  504(X2), X9
	SW  X8, 0(X2)
	SW  X8, 124(X2)
	SW  X8, 2044(X2)
	SD  X8, 0(X2)
	SD  X8, 504(X2)
	FLW 0(X2), F8
	FLD 504(X2), F8
	FSW F8, 0(X2)
	FSD F8, 504(X2)
	RET

TEXT ·frameAdj(SB), NOSPLIT, $0
	ADDI $16, X2, X2
	ADDI $-16, X2, X2
	ADDI $496, X2, X2
	ADDI $-512, X2, X2
	ADDI $1024, X2, X2
	ADDI $2048, X2, X2
	ADDI $1, X2, X2
	RET

TEXT ·primeMem(SB), NOSPLIT, $0
	LW  0(X8), X9
	LW  4(X8), X10
	LW  124(X8), X11
	LD  0(X8), X9
	LD  8(X8), X10
	LD  120(X8), X11
	SW  X9, 0(X8)
	SW  X9, 124(X8)
	SD  X9, 0(X8)
	SD  X9, 120(X8)
	RET

TEXT ·cBranches(SB), NOSPLIT, $0
	BEQ  X8, X0, cb1
	BNE  X9, X0, cb2
	BLT  X10, X0, cb1
	BGE  X11, X0, cb2
	BLTU X12, X0, cb1
	BGEU X13, X0, cb2

cb1:
	MOV  X8, X9

cb2:
	MOV  X9, X8
	RET

TEXT ·uncompressible(SB), NOSPLIT, $0
	ADD  X17, X16, X16
	ADDI $2048, X8, X8
	LW   2048(X2), X10
	LD   512(X2), X10
	SW   X8, 2048(X2)
	ADDI $2049, X2, X2
	RET