107 lines
2.3 KiB
ArmAsm
107 lines
2.3 KiB
ArmAsm
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleRISCV64: the immediate-range ladder of the
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// I-type arithmetic and the U-type pair, the family GOROOT's riscv64
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// assembler corpus walks (cmd/asm/internal/asm/testdata/riscv64.s). Every
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// boundary sits on an encoder gate: the 12-bit signed window, the
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// one-instruction and two-instruction decompositions, the shamt widths and
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// the wide MOV immediate that goes through the literal pool.
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#include "textflag.h"
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TEXT ·immIType(SB), NOSPLIT, $0
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ADDI $2047, X5, X6
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ADDI $-2048, X5, X6
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ADDI $2048, X5, X6
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ADDI $-2049, X5, X6
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ADDI $4094, X5, X6
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ADDI $-4096, X5, X6
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ADDI $4095, X5, X6
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ADDI $-4097, X5, X6
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ADDI $0, X5, X6
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SLTI $2047, X5, X7
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SLTI $-2048, X5, X7
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SLTIU $2047, X5, X7
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SLTIU $-2048, X5, X7
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ANDI $-2048, X5, X6
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ANDI $2047, X5, X6
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ORI $-1, X5, X6
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XORI $2047, X5, X6
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XORI $-2048, X5, X6
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RET
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TEXT ·immAlias(SB), NOSPLIT, $0
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ADD $2047, X5, X6
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ADD $2048, X5, X6
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SUB $1, X5, X6
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SUB $2049, X5, X6
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AND $-1, X5, X6
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OR $2047, X5, X6
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XOR $-2048, X5, X6
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SLT $55, X5, X7
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SLTU $55, X5, X7
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ADDW $2047, X5, X6
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RET
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TEXT ·immUType(SB), NOSPLIT, $0
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LUI $0x7FFFF, X6
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LUI $-0x80000, X6
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LUI $1, X6
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AUIPC $0x7FFFF, X7
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AUIPC $-0x80000, X7
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RET
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TEXT ·immShift(SB), NOSPLIT, $0
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SLLI $0, X5, X6
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SLLI $31, X5, X6
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SLLI $63, X5, X6
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SRLI $31, X5, X6
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SRLI $63, X5, X6
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SRAI $1, X5, X6
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SRAI $63, X5, X6
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SLLIW $31, X5, X6
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SRLIW $31, X5, X6
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SRAIW $31, X5, X6
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SLLIUW $31, X5, X6
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RET
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TEXT ·immWide(SB), NOSPLIT, $0
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MOV $0, X10
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MOV $2047, X10
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MOV $2048, X10
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MOV $-2048, X10
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MOV $4095, X10
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MOV $-4097, X10
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MOV $0x12345678, X10
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MOV $0x123456789, X10
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MOV $0x123456789ABCDEF0, X10
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MOV $-1, X11
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MOV $-0x8000000000000000, X11
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MOV $0x7FFFFFFFFFFFFFFF, X12
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RET
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TEXT ·memOffsets(SB), NOSPLIT, $0
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LD 0(X10), X11
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LD 2047(X10), X11
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LD -2048(X10), X11
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LD 2048(X10), X11
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LD 4095(X10), X11
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LD -4096(X10), X11
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LW 0(X10), X12
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LBU -1(X10), X12
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LHU 2(X10), X12
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LWU -3(X10), X12
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SD X11, 0(X10)
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SD X11, 2047(X10)
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SD X11,-2048(X10)
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SD X11, 4095(X10)
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SW X12,-4096(X10)
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SH X12, 6(X10)
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SB X12, 7(X10)
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FLW 8(X10), F8
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FLD -8(X10), F8
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FSW F8, 16(X10)
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FSD F8,-16(X10)
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RET
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