226 lines
10 KiB
Go
226 lines
10 KiB
Go
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import (
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"os"
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"strings"
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"testing"
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"golang.org/x/arch/x86/x86asm"
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"sourcedock.dev/petrbalvin/gasm-devkit/parser"
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)
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// TestEvexGroundTruth checks the EVEX (AVX-512) encodings byte for byte
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// against machine code extracted from the Go toolchain's assembly of the
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// same instructions, covering every operand shape the go-flac AVX-512
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// kernels use: NDS arithmetic, immediate and variable shifts, shuffles with
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// an immediate, lane extracts, narrowing stores, broadcasts from a GPR or
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// memory, mask destinations, mask moves, disp8×N compression and the 5-bit
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// register fields (X/Y 16–31, Z 0–31).
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func TestEvexGroundTruth(t *testing.T) {
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cases := []struct {
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name string
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mnem string
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ops []Operand
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want string
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}{
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// NDS integer arithmetic / logic.
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{"VPXORD Z12,Z12,Z12", "VPXORD", []Operand{vreg(t, "Z12"), vreg(t, "Z12"), vreg(t, "Z12")}, "62511d48efe4"},
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{"VPXORQ Z8,Z9,Z10", "VPXORQ", []Operand{vreg(t, "Z8"), vreg(t, "Z9"), vreg(t, "Z10")}, "6251b548efd0"},
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{"VPADDD Z1,Z0,Z0", "VPADDD", []Operand{vreg(t, "Z1"), vreg(t, "Z0"), vreg(t, "Z0")}, "62f17d48fec1"},
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{"VPSUBQ Z8,Z11,Z11", "VPSUBQ", []Operand{vreg(t, "Z8"), vreg(t, "Z11"), vreg(t, "Z11")}, "6251a548fbd8"},
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{"VPUNPCKLDQ Z5,Z3,Z6", "VPUNPCKLDQ", []Operand{vreg(t, "Z5"), vreg(t, "Z3"), vreg(t, "Z6")}, "62f1654862f5"},
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{"VPUNPCKHDQ Z5,Z3,Z7", "VPUNPCKHDQ", []Operand{vreg(t, "Z5"), vreg(t, "Z3"), vreg(t, "Z7")}, "62f165486afd"},
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{"VPMULLQ Z9,Z10,Z10", "VPMULLQ", []Operand{vreg(t, "Z9"), vreg(t, "Z10"), vreg(t, "Z10")}, "6252ad4840d1"},
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{"VPMULLD Z13,Z11,Z2", "VPMULLD", []Operand{vreg(t, "Z13"), vreg(t, "Z11"), vreg(t, "Z2")}, "62d2254840d5"},
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{"VPERMD Z0,Z15,Z8", "VPERMD", []Operand{vreg(t, "Z0"), vreg(t, "Z15"), vreg(t, "Z8")}, "6272054836c0"},
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// Packed-double arithmetic (EVEX forms carry W=1).
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{"VADDPD Z11,Z10,Z10", "VADDPD", []Operand{vreg(t, "Z11"), vreg(t, "Z10"), vreg(t, "Z10")}, "6251ad4858d3"},
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{"VMULPD Z13,Z12,Z12", "VMULPD", []Operand{vreg(t, "Z13"), vreg(t, "Z12"), vreg(t, "Z12")}, "62519d4859e5"},
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{"VFMADD231PD Z14,Z12,Z10", "VFMADD231PD", []Operand{vreg(t, "Z14"), vreg(t, "Z12"), vreg(t, "Z10")}, "62529d48b8d6"},
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// Align (NDS + imm8).
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{"VALIGND $12,Z12,Z0,Z1", "VALIGND", []Operand{Imm(12), vreg(t, "Z12"), vreg(t, "Z0"), vreg(t, "Z1")}, "62d37d4803cc0c"},
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{"VALIGND $15,Z9,Z0,Z1", "VALIGND", []Operand{Imm(15), vreg(t, "Z9"), vreg(t, "Z0"), vreg(t, "Z1")}, "62d37d4803c90f"},
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// Shifts: immediate (/digit) and variable (XMM count).
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{"VPSRAD $31,Z3,Z5", "VPSRAD", []Operand{Imm(31), vreg(t, "Z3"), vreg(t, "Z5")}, "62f1554872e31f"},
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{"VPSLLD $1,Z3,Z4", "VPSLLD", []Operand{Imm(1), vreg(t, "Z3"), vreg(t, "Z4")}, "62f15d4872f301"},
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{"VPSRAQ X31,Z8,Z8", "VPSRAQ", []Operand{vreg(t, "X31"), vreg(t, "Z8"), vreg(t, "Z8")}, "6211bd48e2c7"},
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// Mask destinations (the K register occupies the reg field).
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{"VPCMPEQD Z0,Z3,K1", "VPCMPEQD", []Operand{vreg(t, "Z0"), vreg(t, "Z3"), vreg(t, "K1")}, "62f1654876c8"},
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{"VPCMPEQD Y30,Y11,K1", "VPCMPEQD", []Operand{vreg(t, "Y30"), vreg(t, "Y11"), vreg(t, "K1")}, "6291252876ce"},
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// Mask moves and test (VEX-encoded).
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{"KMOVW K1,CX", "KMOVW", []Operand{vreg(t, "K1"), CX}, "c5f893c9"},
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{"KMOVW K1,R12", "KMOVW", []Operand{vreg(t, "K1"), vreg(t, "R12")}, "c57893e1"},
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{"KTESTW K1,K1", "KTESTW", []Operand{vreg(t, "K1"), vreg(t, "K1")}, "c5f899c9"},
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// Moves, incl. disp8×N (64 for a 512-bit operand).
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{"VMOVDQU32 (SI)(R15*4),Z3", "VMOVDQU32", []Operand{Idx(SI, vreg(t, "R15"), 4, 0, 64), vreg(t, "Z3")}, "62b17e486f1cbe"},
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{"VMOVDQU32 4(SI)(AX*1),Z4", "VMOVDQU32", []Operand{Idx(SI, AX, 1, 4, 64), vreg(t, "Z4")}, "62f17e486fa40604000000"},
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{"VMOVDQU32 16(SI)(R15*4),Z4", "VMOVDQU32", []Operand{Idx(SI, vreg(t, "R15"), 4, 16, 64), vreg(t, "Z4")}, "62b17e486fa4be10000000"},
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{"VMOVDQU32 Z0,4(SI)(AX*1)", "VMOVDQU32", []Operand{vreg(t, "Z0"), Idx(SI, AX, 1, 4, 64)}, "62f17e487f840604000000"},
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{"VMOVDQU32 Z3,(DI)(R15*4)", "VMOVDQU32", []Operand{vreg(t, "Z3"), Idx(DI, vreg(t, "R15"), 4, 0, 64)}, "62b17e487f1cbf"},
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// VMOVDQU64 — the W1 qword variant.
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{"VMOVDQU64 (SI)(R15*4),Z3", "VMOVDQU64", []Operand{Idx(SI, vreg(t, "R15"), 4, 0, 64), vreg(t, "Z3")}, "62b1fe486f1cbe"},
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{"VMOVDQU64 Z0,4(SI)(AX*1)", "VMOVDQU64", []Operand{vreg(t, "Z0"), Idx(SI, AX, 1, 4, 64)}, "62f1fe487f840604000000"},
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{"VMOVDQU64 Z1,Z2", "VMOVDQU64", []Operand{vreg(t, "Z1"), vreg(t, "Z2")}, "62f1fe487fca"},
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{"VMOVUPD (DI),Z14", "VMOVUPD", []Operand{Ptr(DI, 0, 64), vreg(t, "Z14")}, "6271fd481037"},
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{"VMOVUPD 64(DI),Z14", "VMOVUPD", []Operand{Ptr(DI, 64, 64), vreg(t, "Z14")}, "6271fd48107701"},
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// Conversions and narrowing stores (reg = wide source).
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{"VCVTQQ2PD Z12,Z12", "VCVTQQ2PD", []Operand{vreg(t, "Z12"), vreg(t, "Z12")}, "6251fe48e6e4"},
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{"VCVTQQ2PD X13,X13", "VCVTQQ2PD", []Operand{vreg(t, "X13"), vreg(t, "X13")}, "6251fe08e6ed"},
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{"VPMOVSXDQ 32(SI),Z12", "VPMOVSXDQ", []Operand{Ptr(SI, 32, 32), vreg(t, "Z12")}, "62727d48256601"},
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{"VPMOVDW Z0,Y0", "VPMOVDW", []Operand{vreg(t, "Z0"), vreg(t, "Y0")}, "62f27e4833c0"},
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{"VPMOVQD Z11,Y11", "VPMOVQD", []Operand{vreg(t, "Z11"), vreg(t, "Y11")}, "62527e4835db"},
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// Lane extracts.
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{"VEXTRACTI64X4 $1,Z8,Y9", "VEXTRACTI64X4", []Operand{Imm(1), vreg(t, "Z8"), vreg(t, "Y9")}, "6253fd483bc101"},
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{"VEXTRACTF64X4 $1,Z10,Y11", "VEXTRACTF64X4", []Operand{Imm(1), vreg(t, "Z10"), vreg(t, "Y11")}, "6253fd481bd301"},
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// Broadcasts: GPR source (0x7C) vs memory source (0x58/0x59, disp8×4/8).
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{"VPBROADCASTD AX,Z15", "VPBROADCASTD", []Operand{AX, vreg(t, "Z15")}, "62727d487cf8"},
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{"VPBROADCASTD (SI),Z8", "VPBROADCASTD", []Operand{Ptr(SI, 0, 4), vreg(t, "Z8")}, "62727d485806"},
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{"VPBROADCASTD 4(SI),Z10", "VPBROADCASTD", []Operand{Ptr(SI, 4, 4), vreg(t, "Z10")}, "62727d48585601"},
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{"VPBROADCASTQ R8,X31", "VPBROADCASTQ", []Operand{vreg(t, "R8"), vreg(t, "X31")}, "6242fd087cf8"},
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{"VPBROADCASTQ AX,Z9", "VPBROADCASTQ", []Operand{AX, vreg(t, "Z9")}, "6272fd487cc8"},
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// Register indices 16–31 exist only in EVEX encodings.
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{"VPBROADCASTD AX,Y30", "VPBROADCASTD", []Operand{AX, vreg(t, "Y30")}, "62627d287cf0"},
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}
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for _, c := range cases {
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want := strings.ReplaceAll(c.want, " ", "")
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code, err := Encode(c.mnem, c.ops...)
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if err != nil {
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t.Errorf("%s: Encode: %v", c.name, err)
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continue
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}
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if got := hexCompact(code); got != want {
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t.Errorf("%s: bytes %s, want %s", c.name, got, want)
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continue
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}
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inst, err := x86asm.Decode(code, 64)
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if err != nil {
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t.Errorf("%s: Decode(%x): %v", c.name, code, err)
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continue
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}
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if inst.Len != len(code) {
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t.Errorf("%s: Decode consumed %d of %d bytes", c.name, inst.Len, len(code))
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}
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if inst.Op.String() != c.mnem {
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t.Errorf("%s: decoded as %s", c.name, inst.Op.String())
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}
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}
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}
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// TestEvexErrors checks the EVEX-specific error paths.
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func TestEvexErrors(t *testing.T) {
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cases := []struct {
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name string
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mnem string
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ops []Operand
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}{
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{"NDS arity", "VPXORD", []Operand{vreg(t, "Z0"), vreg(t, "Z1")}},
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{"KMOVW arity", "KMOVW", []Operand{vreg(t, "K1")}},
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{"KMOVW no K", "KMOVW", []Operand{AX, CX}},
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{"VMOVUPD Z gpr", "VMOVUPD", []Operand{AX, vreg(t, "Z1")}},
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{"broadcast src", "VPBROADCASTD", []Operand{Imm(1), vreg(t, "Z1")}},
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{"VPMOVDW src", "VPMOVDW", []Operand{AX, vreg(t, "Y0")}},
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{"align arity", "VALIGND", []Operand{Imm(1), vreg(t, "Z0"), vreg(t, "Z1")}},
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// VEX-only mnemonics reject registers only EVEX can encode.
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{"VPSHUFD X16", "VPSHUFD", []Operand{Imm(1), vreg(t, "X16"), vreg(t, "X17")}},
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}
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for _, c := range cases {
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if _, err := Encode(c.mnem, c.ops...); err == nil {
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t.Errorf("%s: expected an error, got none", c.name)
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}
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}
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}
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// TestAssembleGoFlacAVX512Kernel assembles the whole production AVX-512
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// kernel — all functions plus the file-global idx16 constant — and checks
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// that the static-symbol load resolves to the right bytes in the image.
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// Skipped when the sibling repository is not checked out.
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func TestAssembleGoFlacAVX512Kernel(t *testing.T) {
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path := "../../go-libraries/go-flac/avx512_amd64.s"
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if _, err := os.Stat(path); err != nil {
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t.Skip("go-libraries repository not present next to gasm-devkit")
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}
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src, err := os.ReadFile(path)
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if err != nil {
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t.Fatal(err)
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}
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f, errs := parser.Parse(path, string(src))
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if len(errs) > 0 {
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t.Fatalf("parse: %v", errs)
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}
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img, err := AssembleFile(f)
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if err != nil {
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t.Fatalf("AssembleFile: %v", err)
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}
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if len(img.Funcs) != 10 {
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t.Errorf("functions = %d, want 10", len(img.Funcs))
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}
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// idx16 as the DATA directives define it: dwords 1..16.
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idx := make([]byte, 0, 64)
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for i := 1; i <= 16; i++ {
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idx = append(idx, byte(i), 0, 0, 0)
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}
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image := img.Bytes()
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base := img.Symbols["idx16"]
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if base == 0 {
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t.Fatal("idx16 not laid out")
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}
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if got := image[base : base+64]; hexCompact(got) != hexCompact(idx) {
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t.Errorf("idx16 contents %x, want %x", got, idx)
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}
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// The VMOVDQU32 idx16(SB), Z13 load (62 71 7e 48 6f 2d + rel32) must
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// resolve to idx16 within the image.
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loads := 0
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for _, fn := range img.Funcs {
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code := img.Code[fn.Offset : fn.Offset+fn.Size]
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pat := []byte{0x62, 0x71, 0x7e, 0x48, 0x6f, 0x2d}
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for pos := 0; ; {
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i := indexOf(code[pos:], pat)
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if i < 0 {
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break
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}
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i += pos
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rel := int32(uint32(code[i+6]) | uint32(code[i+7])<<8 | uint32(code[i+8])<<16 | uint32(code[i+9])<<24)
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target := fn.Offset + i + 10 + int(rel)
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if target != base {
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t.Errorf("%s: idx16 load at +%d targets 0x%x, want 0x%x", fn.Name, i, target, base)
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}
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loads++
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pos = i + 10
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}
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}
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if loads != 1 {
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t.Errorf("idx16 loads found = %d, want 1", loads)
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}
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}
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// hexCompact renders bytes as a lowercase hex string without separators.
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func hexCompact(b []byte) string {
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const hexdig = "0123456789abcdef"
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out := make([]byte, len(b)*2)
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for i, c := range b {
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out[i*2] = hexdig[c>>4]
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out[i*2+1] = hexdig[c&0xf]
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}
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return string(out)
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}
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// indexOf returns the index of the first occurrence of pat in b, or -1.
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func indexOf(b, pat []byte) int {
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for i := 0; i+len(pat) <= len(b); i++ {
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j := 0
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for j < len(pat) && b[i+j] == pat[j] {
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j++
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}
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if j == len(pat) {
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return i
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}
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}
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return -1
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}
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