410 lines
14 KiB
Go
410 lines
14 KiB
Go
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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// arm64 frame mapping, matching the Go toolchain's arm64 backend.
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//
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// Go's arm64 functions use R29 as the frame pointer (FP) and R30 as the link
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// register (LR). R31 is the stack pointer (SP). FP and SP in the source
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// are synthetic pseudo-registers resolved against the hardware SP and the
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// frame size.
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//
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// The autosize is the real stack adjustment: the declared local frame plus
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// 8 bytes for the saved link register, rounded up to a 16-byte multiple.
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// The toolchain adds an "extrasize" to align: if autosize%16 == 8, add 8;
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// if autosize%16 == 0, add 16.
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//
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// Prologue (autosize > 0, small frame ≤ 0xf0):
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//
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// MOVD.W LR, -autosize(SP) // pre-index: SP -= autosize, store LR at SP
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// MOVD FP, -8(SP) // store FP at SP-8
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// SUB $8, SP, FP // FP = SP - 8
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//
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// Prologue (autosize > 0, large frame > 0xf0):
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//
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// SUB $autosize, SP, R20 // R20 = SP - autosize
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// STP (FP, LR), -8(R20) // store FP,LR at R20-8
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// MOVD R20, SP // SP = R20
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// SUB $8, SP, FP // FP = SP - 8
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//
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// Epilogue (non-leaf, small frame):
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//
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// ADD $autosize-8, SP, FP // restore FP
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// ADD $autosize, SP, SP // deallocate frame
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// MOVD -8(SP), FP // (actually the reverse of prologue)
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// Actually:
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// MOVD -8(SP), FP // load FP from SP-8
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// MOVD.P autosize(SP), LR // post-index: load LR, SP += autosize
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//
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// Epilogue (non-leaf, large frame):
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// ADD $autosize-8, SP, FP
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// ADD $autosize, SP, SP
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// Actually:
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// LDP -8(SP), (FP, LR) // load FP,LR
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// ADD $autosize, SP, SP // deallocate frame
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//
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// Epilogue (leaf with frame):
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// ADD $autosize-8, SP, FP
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// ADD $autosize, SP, SP
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//
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// RET always emits as BR LR (0xd65f03c0).
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import (
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"strings"
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"sourcedock.dev/petrbalvin/gasm-devkit/ast"
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)
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// arm64FrameInfo holds the frame layout derived from a TEXT directive.
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type arm64FrameInfo struct {
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autosize int // the real SP adjustment (locals + saved LR + alignment)
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frame int // the declared $framesize
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args int // the declared -argsize
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noSplit bool // the NOSPLIT flag
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leaf bool // no call instructions in the body
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// Stack-split guard state: needSplit mirrors the toolchain, which skips
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// the check for NOSPLIT functions and auto-marks leaf functions with an
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// autosize below StackSmall as NOSPLIT.
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needSplit bool
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splitClass int // 0: <=StackSmall, 1: <=StackBig, 2: >StackBig
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}
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// arm64ComputeFrame derives the frame layout for a TEXT function.
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func arm64ComputeFrame(t *ast.Text) arm64FrameInfo {
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fi := arm64FrameInfo{
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frame: frameSize(t),
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args: argsSize(t),
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}
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for _, f := range t.Flags {
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if f == "NOSPLIT" {
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fi.noSplit = true
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}
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}
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fi.leaf = arm64IsLeaf(t)
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if fi.frame != 0 || !fi.leaf {
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fi.autosize = fi.frame + 8 // space for the saved LR
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// The toolchain always adds an extrasize: 8 when the total leaves a
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// 16-byte alignment gap, another 16 when already aligned.
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switch fi.autosize % 16 {
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case 8:
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fi.autosize += 8
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case 0:
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fi.autosize += 16
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default:
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// The toolchain rejects unaligned frames; round up so such
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// sources still assemble.
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fi.autosize += 16 - (fi.autosize % 16)
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}
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}
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switch {
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case fi.noSplit:
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case fi.autosize < stackSmall && fi.leaf:
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// Auto-NOSPLIT, as the toolchain's leaf mark concludes.
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default:
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fi.needSplit = true
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switch {
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case fi.autosize <= stackSmall:
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fi.splitClass = 0
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case fi.autosize <= stackBig:
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fi.splitClass = 1
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default:
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fi.splitClass = 2
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}
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}
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return fi
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}
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// arm64GuardLen returns the byte length of the stack-split guard prefix
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// (zero when the function needs no guard). The big class materialises
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// framesize-StackSmall into REGTMP, whose MOVZ/MOVK sequence length varies.
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func arm64GuardLen(fi arm64FrameInfo) int {
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if !fi.needSplit {
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return 0
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}
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switch fi.splitClass {
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case 0:
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return 12
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case 1:
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return 16
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default:
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n, err := arm64LoadImmLen(int64(fi.autosize - stackSmall))
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if err != nil {
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return 0
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}
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return 4 + n + 4 + 4 + 4 + 4
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}
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}
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// arm64LoadImmLen returns the byte length of the MOVZ/MOVK sequence that
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// loads v into a register.
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func arm64LoadImmLen(v int64) (int, error) {
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b, err := encodeARM64LoadImm(27, v, "MOVD")
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if err != nil {
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return 0, err
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}
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return len(b), nil
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}
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// arm64IsLeaf reports whether a function contains no call instructions
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// (BL/CALL), matching the toolchain's LEAF mark.
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func arm64IsLeaf(t *ast.Text) bool {
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for _, stmt := range t.Body {
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in, ok := stmt.(*ast.Instr)
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if !ok {
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continue
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}
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switch strings.ToUpper(in.Mnemonic.Text) {
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case "BL", "CALL":
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return false
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}
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}
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return true
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}
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// arm64Prologue returns the prologue bytes for an arm64 function.
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func arm64Prologue(fi arm64FrameInfo) []byte {
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if fi.autosize == 0 {
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return nil
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}
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if fi.autosize <= 0xf0 {
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// Small frame: MOVD.W LR, -autosize(SP); MOVD FP, -8(SP); SUB $8, SP, FP
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return a64WordsLE(
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arm64PreStoreImm(3, 0, int32(-fi.autosize), 31, 30), // STR.W LR, -autosize(SP) (pre-index store)
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arm64UnscaledStore(3, 0, -8, 31, 29), // STUR FP, [SP, #-8]
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a64AddSub(1, 1, 0, 0, 8, 31, 29), // SUB $8, SP, FP (op=1 for SUB)
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)
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}
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// Large frame: SUB $autosize, SP, R20; STP (FP,LR), -8(R20); ADD $0, R20, SP; SUB $8, SP, FP
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ws := arm64SubImmWords(uint32(fi.autosize), 20)
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ws = append(ws,
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a64LSP(2, 0, 0, -1, 30, 20, 29), // STP FP, LR, [R20, #-8] (opc=2 for 64-bit pair)
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a64AddSub(1, 0, 0, 0, 0, 20, 31), // ADD $0, R20, SP (= MOV R20, SP)
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a64AddSub(1, 1, 0, 0, 8, 31, 29), // SUB $8, SP, FP (op=1 for SUB)
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)
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return a64WordsLE(ws...)
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}
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// arm64SubImmWords emits SUB $imm, SP, Rd: the immediate form when the value
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// fits the imm12 field (plain, or shifted left by 12 when it is a multiple
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// of 4096); otherwise the toolchain materialises it into REGTMP (R27) and
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// subtracts the register in the extended-register form.
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func arm64SubImmWords(imm uint32, rd uint32) []uint32 {
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if imm <= 0xFFF {
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return []uint32{a64AddSub(1, 1, 0, 0, imm, 31, rd)}
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}
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if imm <= 4095<<12 && imm&0xFFF == 0 {
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return []uint32{a64AddSub(1, 1, 0, 1, imm>>12, 31, rd)}
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}
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mov, err := encodeARM64LoadImm(27, int64(imm), "MOVD")
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if err != nil {
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mov = nil
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}
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return append(wordsOf(mov), arm64DPExtWords(arm64OpSub, 27, 31, rd))
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}
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// arm64AddImmWords emits ADD $imm, SP, Rd with the same imm12, shifted-imm12
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// and REGTMP fallback ladder.
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func arm64AddImmWords(imm uint32, rd uint32) []uint32 {
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if imm <= 0xFFF {
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return []uint32{a64AddSub(1, 0, 0, 0, imm, 31, rd)}
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}
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if imm <= 4095<<12 && imm&0xFFF == 0 {
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return []uint32{a64AddSub(1, 0, 0, 1, imm>>12, 31, rd)}
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}
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mov, err := encodeARM64LoadImm(27, int64(imm), "MOVD")
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if err != nil {
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mov = nil
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}
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return append(wordsOf(mov), arm64DPExtWords(arm64OpAdd, 27, 31, rd))
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}
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// arm64Return returns the bytes for a RET: the epilogue (restore FP/LR and
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// deallocate the frame when present) followed by RET (BR LR).
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func arm64Return(fi arm64FrameInfo) []byte {
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var ws []uint32
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if fi.autosize != 0 {
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if fi.leaf {
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// Leaf with frame: ADD $autosize-8, SP, FP; ADD $autosize, SP, SP
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ws = append(ws, arm64AddImmWords(uint32(fi.autosize-8), 29)...)
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ws = append(ws, arm64AddImmWords(uint32(fi.autosize), 31)...)
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} else if fi.autosize <= 0xf0 {
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// Non-leaf small frame: LDR FP, [SP, #-8]; LDR.P LR, [SP], #autosize
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ws = append(ws,
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arm64UnscaledLoad(3, 0, -8, 31, 29), // LDR FP, [SP, #-8]
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arm64PostLoad(3, 0, int32(fi.autosize), 31, 30), // LDR.P LR, [SP], #autosize
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)
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} else {
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// Large frame: LDP -8(SP), (FP, LR); ADD $autosize, SP, SP
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ws = append(ws,
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a64LSP(2, 0, 1, -1, 30, 31, 29), // LDP FP, LR, [SP, #-8] (opc=2 for 64-bit pair)
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)
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ws = append(ws, arm64AddImmWords(uint32(fi.autosize), 31)...)
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}
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}
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// RET: BR LR (0xd65f03c0)
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ws = append(ws, a64UncondBranch(2, 30, 0)) // opc=2(RET), Rn=LR(30), Rd=0
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return a64WordsLE(ws...)
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}
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// arm64PrologueSpadjPC returns the function-relative byte offset where the
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// prologue has finished decrementing SP (the delta becomes autosize).
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func arm64PrologueSpadjPC(fi arm64FrameInfo) int {
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if fi.autosize == 0 {
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return 0
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}
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if fi.autosize <= 0xf0 {
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return 4 // MOVD.W instruction decrements SP
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}
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return 8 // SUB + STP + MOVD (3 instructions, SP updated at the MOVD)
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}
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// arm64ReturnEpilogueLen returns the byte length of the RET's epilogue up to
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// (but not including) the final RET instruction.
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func arm64ReturnEpilogueLen(fi arm64FrameInfo) int {
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if fi.autosize == 0 {
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return 0
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}
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if fi.leaf {
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return 8 // ADD + ADD
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}
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if fi.autosize <= 0xf0 {
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return 8 // LDR + LDR.P
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}
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return 8 // LDP + ADD
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}
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// arm64ResolvePseudo translates a pseudo-register memory reference into a
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// hardware base register and offset. x+N(FP) → (N + autosize + 8)(SP);
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// x+N(SP) → (N + frame + 8)(SP). Returns base = -1 for an unresolvable
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// reference (SB: static data, handled by the relocation path).
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//
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// The Go toolchain resolves all pseudo-register references against the
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// hardware stack pointer (R31/SP): FP references add autosize+8 (the
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// distance from SP after the prologue to the caller's argument area),
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// SP references add frame+8 (the distance to the local area).
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func arm64ResolvePseudo(sym *ast.Symbol, fi arm64FrameInfo) (base int, off int32) {
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if sym == nil {
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return -1, 0
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}
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switch sym.Pseudo {
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case "FP":
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return 31, int32(sym.Offset) + int32(fi.autosize) + 8
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case "SP":
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return 31, int32(sym.Offset) + int32(fi.frame) + 8
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case "SB":
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return -1, int32(sym.Offset)
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}
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return -1, 0
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}
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// arm64PreStoreImm encodes a pre-index store (STR with writeback):
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// size<<30 | 7<<27 | V<<26 | opc<<22 | 1<<11 | 1<<10 | imm9<<12 | Rn<<5 | Rt.
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func arm64PreStoreImm(size, V int, imm9 int32, rn, rt int) uint32 {
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return uint32(size)<<30 | 7<<27 | uint32(V)<<26 | 0<<22 |
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3<<10 | (uint32(imm9)&0x1FF)<<12 | uint32(rn&31)<<5 | uint32(rt&31)
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}
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// arm64UnscaledStore encodes an unscaled store (STUR):
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// size<<30 | 7<<27 | V<<26 | opc<<22 | 0<<11 | 0<<10 | imm9<<12 | Rn<<5 | Rt.
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func arm64UnscaledStore(size, V int, imm9 int32, rn, rt int) uint32 {
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return uint32(size)<<30 | 7<<27 | uint32(V)<<26 | 0<<22 |
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(uint32(imm9)&0x1FF)<<12 | uint32(rn&31)<<5 | uint32(rt&31)
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}
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// arm64UnscaledLoad encodes an unscaled load (LDUR):
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// size<<30 | 7<<27 | V<<26 | opc<<22 | 0<<11 | 0<<10 | imm9<<12 | Rn<<5 | Rt.
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func arm64UnscaledLoad(size, V int, imm9 int32, rn, rt int) uint32 {
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return uint32(size)<<30 | 7<<27 | uint32(V)<<26 | 1<<22 |
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(uint32(imm9)&0x1FF)<<12 | uint32(rn&31)<<5 | uint32(rt&31)
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}
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// arm64PostLoad encodes a post-index load (LDR with post-increment):
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// size<<30 | 7<<27 | V<<26 | opc<<22 | 0<<11 | 1<<10 | imm9<<12 | Rn<<5 | Rt.
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func arm64PostLoad(size, V int, imm9 int32, rn, rt int) uint32 {
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return uint32(size)<<30 | 7<<27 | uint32(V)<<26 | 1<<22 |
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1<<10 | (uint32(imm9)&0x1FF)<<12 | uint32(rn&31)<<5 | uint32(rt&31)
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}
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// Data-processing (shifted register) base opcodes for the guard blocks.
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const (
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arm64OpAdd = 1<<31 | 0<<30 | 0<<29 | 0x0b<<24
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arm64OpSub = 1<<31 | 1<<30 | 0<<29 | 0x0b<<24
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arm64OpSubs = 1<<31 | 1<<30 | 1<<29 | 0x0b<<24
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)
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// arm64DPSRWords builds one data-processing (shifted register) word:
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// OP Rm, Rn, Rd in the Go assembler's operand order.
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func arm64DPSRWords(base uint32, rm, rn, rd uint32) uint32 {
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return base | rm<<16 | rn<<5 | rd
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}
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// arm64DPExtWords builds one data-processing (extended register) word, the
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// form the toolchain picks when a large immediate was materialised into
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// REGTMP before the operation: base | 1<<21 | Rm<<16 | UXTX<<13 | Rn<<5 | Rd.
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func arm64DPExtWords(base, rm, rn, rd uint32) uint32 {
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return base | 1<<21 | rm<<16 | 3<<13 | rn<<5 | rd
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}
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// wordsOf converts little-endian instruction bytes back to words.
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func wordsOf(b []byte) []uint32 {
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ws := make([]uint32, 0, len(b)/4)
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for i := 0; i+4 <= len(b); i += 4 {
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ws = append(ws, uint32(b[i])|uint32(b[i+1])<<8|uint32(b[i+2])<<16|uint32(b[i+3])<<24)
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}
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return ws
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}
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// arm64GuardBytes emits the stack-split guard prefix; blockStart is the
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// function-relative byte address of the morestack block the branches target.
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func arm64GuardBytes(fi arm64FrameInfo, blockStart int) []byte {
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// MOVD 16(R28), R16 (g.stackguard0)
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ws := []uint32{a64LSU(3, 0, 1, 2, 28, 16)}
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br := func(from int, cond uint32) uint32 {
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return a64BranchCond(int32((blockStart-from)>>2), cond)
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}
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switch fi.splitClass {
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case 0:
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// CMP R16, RSP in the exact encoding go tool asm emits for it.
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ws = append(ws, 0xeb3063ff)
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ws = append(ws, br(8, a64CondLS))
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case 1:
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ws = append(ws, a64AddSub(1, 1, 0, 0, uint32(fi.autosize-stackSmall), 31, 17))
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ws = append(ws, arm64DPSRWords(arm64OpSubs, 16, 17, 31)) // CMP R16, R17
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ws = append(ws, br(12, a64CondLS))
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default:
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mov, err := encodeARM64LoadImm(27, int64(fi.autosize-stackSmall), "MOVD")
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if err != nil {
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mov = nil
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}
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ws = append(ws, wordsOf(mov)...)
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ml := len(mov) / 4
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ws = append(ws, arm64DPExtWords(arm64OpSubs, 27, 31, 17)) // SUBS R17, RSP, R27
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ws = append(ws, br(8+ml, a64CondLO))
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ws = append(ws, arm64DPSRWords(arm64OpSubs, 16, 17, 31)) // CMP R16, R17
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ws = append(ws, br(8+ml+8, a64CondLS))
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}
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return a64WordsLE(ws...)
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}
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// arm64MoreStackBlock emits the trailing block: MOVD R30, R3 (save LR),
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// BL runtime.morestack_noctxt, B back to the function start. The BL carries
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// the R_CALLARM64 relocation.
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func arm64MoreStackBlock(blockStart int) ([]byte, Reloc) {
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ws := []uint32{
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1<<31 | 1<<29 | 0x0a<<24 | 30<<16 | 31<<5 | 3, // MOVD R30, R3
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a64Branch(1, 0), // BL, patched by the linker
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}
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bPC := blockStart + 8
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ws = append(ws, a64Branch(0, int32(-bPC>>2))) // B back to the entry
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reloc := Reloc{
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Off: blockStart + 4,
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After: blockStart + 8,
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Name: "runtime\u00b7morestack_noctxt",
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Kind: RelArm64Branch,
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}
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return a64WordsLE(ws...), reloc
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}
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