410 lines
21 KiB
Go
410 lines
21 KiB
Go
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// This file carries the amd64 side of the extended-instruction layer:
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// instructions the Go toolchain does not know at all, described as data and
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// validated against golden vectors from the Intel SDM rather than against the
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// toolchain. It sits beside the generated table, never inside it:
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// arch/amd64_gen.go stays untouched, and asm.Encodable keeps answering false
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// for every mnemonic here, so the layer stays out of the main encoders.
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//
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// The families are AVX512-BF16, AVX512-VP2INTERSECT and the scalar core of
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// AVX512-FP16, in their EVEX register forms. The encodings are transcribed
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// from the SDM instruction entries and cross-checked against binutils-gdb's
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// assembler testsuite; the golden vectors in amd64_ext_test.go pin the
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// bytes. VPOPCNTD and VPOPCNTQ, the third family of the 2026-09-19 survey,
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// no longer belong here: the Go toolchain's assembler knows them today, they
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// live in the generated table and the EVEX encoder, and a mnemonic the
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// toolchain has is not an extension.
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//
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// Memory operands, write masking ({k1}{z}) and embedded rounding arrive with
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// a later slice; every form here encodes the unmasked register forms, which
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// is what the golden-vector path exercises.
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package arch
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import "fmt"
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// The features the amd64 layer covers.
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const (
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ExtFeatureBF16 ExtFeature = "avx512bf16"
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ExtFeatureVP2INTERSECT ExtFeature = "avx512vp2intersect"
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ExtFeatureFP16 ExtFeature = "avx512fp16"
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)
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// ExtXmm, ExtYmm and ExtZmm build vector operands of the three EVEX register
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// widths, VADDPS ZMM1, ZMM2, ZMM3 style. The register number runs 0..31,
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// XMM16 and above included: EVEX carries five register bits in every
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// position, and the golden vectors exercise the high registers on purpose.
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func ExtXmm(reg int) ExtOperand { return ExtOperand{Kind: ExtXMM, Reg: reg} }
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func ExtYmm(reg int) ExtOperand { return ExtOperand{Kind: ExtYMM, Reg: reg} }
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func ExtZmm(reg int) ExtOperand { return ExtOperand{Kind: ExtZMM, Reg: reg} }
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// ExtMask builds an opmask operand, VP2INTERSECTD K1, ZMM2, ZMM3 style. The
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// register number runs 0..7.
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func ExtMask(reg int) ExtOperand { return ExtOperand{Kind: ExtKReg, Reg: reg} }
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// ExtGpr32 and ExtGpr64 build general-register operands, VCVTSI2SH XMM1,
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// XMM2, EAX style. The register number runs 0..15.
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func ExtGpr32(reg int) ExtOperand { return ExtOperand{Kind: ExtR32, Reg: reg} }
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func ExtGpr64(reg int) ExtOperand { return ExtOperand{Kind: ExtR64, Reg: reg} }
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// amd64LengthClass reads the vector length the template encodes out of the
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// L'L field of the EVEX byte three and names the register class every vector
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// operand of that entry must carry.
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func amd64LengthClass(b []byte) ExtOperandKind {
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switch (b[3] >> 5) & 3 {
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case 0:
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return ExtXMM
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case 1:
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return ExtYMM
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default:
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return ExtZMM
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}
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}
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// amd64HalfClass names the half-width companion of a vector class, the
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// destination class of the narrow conversions. At 128 bits the companion is
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// the class itself, which is what the manual gives for the narrowest form.
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func amd64HalfClass(k ExtOperandKind) ExtOperandKind {
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switch k {
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case ExtZMM:
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return ExtYMM
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case ExtYMM:
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return ExtXMM
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default:
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return ExtXMM
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}
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}
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// amd64Encode returns the template with the register-derived bits filled in:
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// dest and rm are register numbers for the ModR/M reg and r/m fields, vvvv is
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// the third-operand register or -1 when the form leaves it unused. The EVEX
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// plumbing follows the encoder in asm: reg[3] rides R bar and reg[4] R prime
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// bar, rm[3] rides B bar, and in a register form rm[4] rides X bar, while
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// vvvv[4] rides V prime bar in byte three.
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func amd64Encode(b []byte, dest, vvvv, rm int) []byte {
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out := make([]byte, len(b))
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copy(out, b)
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rBar, rPrimeBar := 1, 1
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if dest&8 != 0 {
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rBar = 0
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}
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if dest&16 != 0 {
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rPrimeBar = 0
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}
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xBar, bBar := 1, 1
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if rm&8 != 0 {
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bBar = 0
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}
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if rm&16 != 0 {
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xBar = 0
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}
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out[1] |= byte(rBar<<7 | xBar<<6 | bBar<<5 | rPrimeBar<<4)
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vBar, vPrimeBar := 15, 1
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if vvvv >= 0 {
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vBar = 15 - (vvvv & 15)
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if vvvv&16 != 0 {
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vPrimeBar = 0
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}
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}
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out[2] |= byte(vBar << 3)
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out[3] |= byte(vPrimeBar << 3)
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out[5] |= byte((dest&7)<<3 | rm&7)
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return out
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}
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// amd64PlainReg checks the invariants every amd64 register operand carries:
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// no arm64 arrangement, no predicate qualifier, and a register number inside
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// the class the instruction encodes.
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func (in ExtInstr) amd64PlainReg(op ExtOperand, max, pos int) error {
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if op.Arr != ExtArrNone {
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return fmt.Errorf("%s: operand %d carries an arrangement suffix, the amd64 layer takes none", in.Name, pos)
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}
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if op.Qual != ExtQualNone {
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return fmt.Errorf("%s: operand %d carries a predicate qualifier, the amd64 layer takes none", in.Name, pos)
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}
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if op.Reg < 0 || op.Reg > max {
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return fmt.Errorf("%s: operand %d is register %d, outside 0-%d", in.Name, pos, op.Reg, max)
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}
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return nil
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}
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// amd64Vector checks one vector operand against the class the entry encodes.
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func (in ExtInstr) amd64Vector(op ExtOperand, class ExtOperandKind, pos int) error {
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if op.Kind != class {
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return fmt.Errorf("%s: operand %d wants a %s, got %s", in.Name, pos, class, op.Kind)
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}
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return in.amd64PlainReg(op, 31, pos)
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}
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// amd64Gpr checks the general-register operand against the width the entry
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// encodes: the W bit picks 32-bit or 64-bit, unless the entry ignores W, and
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// the general registers run 0..15.
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func (in ExtInstr) amd64Gpr(op ExtOperand, pos int) error {
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want := ExtR32
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if in.Bytes[2]&0x80 != 0 {
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want = ExtR64
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}
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if in.Wig {
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if op.Kind != ExtR32 && op.Kind != ExtR64 {
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return fmt.Errorf("%s: operand %d wants a 32-bit or 64-bit general register, got %s", in.Name, pos, op.Kind)
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}
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} else if op.Kind != want {
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return fmt.Errorf("%s: operand %d wants a %s, got %s", in.Name, pos, want, op.Kind)
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}
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return in.amd64PlainReg(op, 15, pos)
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}
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// encodeAmd64 encodes the amd64 forms: it validates the operand list against
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// the class the template encodes and fills the register bits. An operand the
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// form cannot carry is an error, never a silent mis-encoding.
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func (in ExtInstr) encodeAmd64(ops []ExtOperand) ([]byte, error) {
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switch in.Form {
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case ExtFormAmdVec3:
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return in.encodeAmdVec3(ops)
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case ExtFormAmdVec2, ExtFormAmdVec2Half:
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return in.encodeAmdVec2(ops)
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case ExtFormAmdMask2:
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return in.encodeAmdMask2(ops)
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case ExtFormAmdVecGprVec:
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return in.encodeAmdVecGprVec(ops)
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case ExtFormAmdGprVec, ExtFormAmdVecGpr:
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return in.encodeAmdGprPair(ops)
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default:
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return nil, fmt.Errorf("%s: unknown form %d", in.Name, in.Form)
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}
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}
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// encodeAmdVec3 fills the non-destructive three-vector form: src1, src2,
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// dest, all under one register class.
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func (in ExtInstr) encodeAmdVec3(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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for i, op := range ops {
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if err := in.amd64Vector(op, class, i+1); err != nil {
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return nil, err
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}
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}
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return amd64Encode(in.Bytes, ops[2].Reg, ops[0].Reg, ops[1].Reg), nil
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}
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// encodeAmdVec2 fills the two-vector form: src, dest. The half form narrows
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// the destination: VCVTNEPS2BF16 converts 512 bits of source into 256 bits
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// of destination, and at 128 bits the companion stays the class itself.
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func (in ExtInstr) encodeAmdVec2(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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destClass := class
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if in.Form == ExtFormAmdVec2Half {
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destClass = amd64HalfClass(class)
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}
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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if err := in.amd64Vector(ops[1], destClass, 2); err != nil {
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return nil, err
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}
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return amd64Encode(in.Bytes, ops[1].Reg, -1, ops[0].Reg), nil
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}
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// encodeAmdMask2 fills the mask-destination form: src1, src2, dest, where the
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// destination is an opmask register and both sources share the class.
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func (in ExtInstr) encodeAmdMask2(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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if err := in.amd64Vector(ops[1], class, 2); err != nil {
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return nil, err
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}
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if ops[2].Kind != ExtKReg {
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return nil, fmt.Errorf("%s: operand 3 wants an opmask register, got %s", in.Name, ops[2].Kind)
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}
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if err := in.amd64PlainReg(ops[2], 7, 3); err != nil {
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return nil, err
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}
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return amd64Encode(in.Bytes, ops[2].Reg, ops[0].Reg, ops[1].Reg), nil
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}
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// encodeAmdVecGprVec fills the conversion form with a general-register
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// source: src1, gpr, dest. VCVTSI2SH XMM1, XMM2, EAX style.
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func (in ExtInstr) encodeAmdVecGprVec(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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if err := in.amd64Gpr(ops[1], 2); err != nil {
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return nil, err
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}
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if err := in.amd64Vector(ops[2], class, 3); err != nil {
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return nil, err
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}
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return amd64Encode(in.Bytes, ops[2].Reg, ops[0].Reg, ops[1].Reg), nil
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}
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// encodeAmdGprPair fills the two-operand general-register forms: gpr, vec
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// (the move into a vector register and the integer conversions) and vec, gpr
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// (the move out of one). In both orders the second operand is the
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// destination in the reg field and the first the r/m source; the vector
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// changes position with the form.
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func (in ExtInstr) encodeAmdGprPair(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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vecPos := 1
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if in.Form == ExtFormAmdVecGpr {
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vecPos = 0
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}
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if err := in.amd64Vector(ops[vecPos], class, vecPos+1); err != nil {
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return nil, err
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}
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if err := in.amd64Gpr(ops[1-vecPos], 2-vecPos); err != nil {
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return nil, err
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}
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return amd64Encode(in.Bytes, ops[1].Reg, -1, ops[0].Reg), nil
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}
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// --- the amd64 AVX512-BF16 and VP2INTERSECT table -----------------------------
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// amd64Extensions is the extended-instruction layer of amd64. The encodings
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// are transcribed from the Intel SDM instruction entries and cross-checked
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// against binutils-gdb's assembler testsuite (gas/testsuite/gas/i386/
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// avx512_bf16.d, avx512_bf16_vl.d and x86-64-vp2intersect.d), whose register
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// forms the golden vectors in amd64_ext_test.go quote byte for byte. Each
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// template carries the fixed bits of one encoding with every register-derived
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// bit zero: the map selection in byte one, the W bit, the mandatory prefix
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// and the reserved one-bit in byte two, the vector length in byte three, and
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// the ModR/M mod bits.
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var amd64Extensions = []ExtInstr{
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// AVX512-BF16: the two-way packed single to BF16 conversion and the
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// dot product accumulate. The prefixes differ inside the family, the
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// three-register convert carries F2 while the narrow convert and the dot
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// product carry F3, which the golden vectors pin byte for byte.
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{Name: "VCVTNE2PS2BF16", Summary: "Convert two packed single-precision vectors to packed BF16, truncating",
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Bytes: []byte{0x62, 0x02, 0x07, 0x40, 0x72, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VCVTNE2PS2BF16 (EVEX.NDS.512.F2.0F38.W0 72 /r)"},
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{Name: "VCVTNE2PS2BF16", Summary: "Convert two packed single-precision vectors to packed BF16, truncating",
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Bytes: []byte{0x62, 0x02, 0x07, 0x20, 0x72, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VCVTNE2PS2BF16 (EVEX.NDS.256.F2.0F38.W0 72 /r)"},
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{Name: "VCVTNE2PS2BF16", Summary: "Convert two packed single-precision vectors to packed BF16, truncating",
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Bytes: []byte{0x62, 0x02, 0x07, 0x00, 0x72, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VCVTNE2PS2BF16 (EVEX.NDS.128.F2.0F38.W0 72 /r)"},
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{Name: "VCVTNEPS2BF16", Summary: "Convert packed single precision to packed BF16, truncating, half-width destination",
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Bytes: []byte{0x62, 0x02, 0x06, 0x40, 0x72, 0xC0}, Form: ExtFormAmdVec2Half, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VCVTNEPS2BF16 (EVEX.512.F3.0F38.W0 72 /r, YMM destination)"},
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{Name: "VCVTNEPS2BF16", Summary: "Convert packed single precision to packed BF16, truncating, half-width destination",
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Bytes: []byte{0x62, 0x02, 0x06, 0x20, 0x72, 0xC0}, Form: ExtFormAmdVec2Half, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VCVTNEPS2BF16 (EVEX.256.F3.0F38.W0 72 /r, XMM destination)"},
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{Name: "VCVTNEPS2BF16", Summary: "Convert packed single precision to packed BF16, truncating, half-width destination",
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Bytes: []byte{0x62, 0x02, 0x06, 0x00, 0x72, 0xC0}, Form: ExtFormAmdVec2Half, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VCVTNEPS2BF16 (EVEX.128.F3.0F38.W0 72 /r, XMM destination)"},
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{Name: "VDPBF16PS", Summary: "Multiply BF16 pairs and accumulate the dot product into single precision",
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Bytes: []byte{0x62, 0x02, 0x06, 0x40, 0x52, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VDPBF16PS (EVEX.NDS.512.F3.0F38.W0 52 /r)"},
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{Name: "VDPBF16PS", Summary: "Multiply BF16 pairs and accumulate the dot product into single precision",
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Bytes: []byte{0x62, 0x02, 0x06, 0x20, 0x52, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VDPBF16PS (EVEX.NDS.256.F3.0F38.W0 52 /r)"},
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{Name: "VDPBF16PS", Summary: "Multiply BF16 pairs and accumulate the dot product into single precision",
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Bytes: []byte{0x62, 0x02, 0x06, 0x00, 0x52, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureBF16,
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Ref: "Intel SDM Vol. 2C, VDPBF16PS (EVEX.NDS.128.F3.0F38.W0 52 /r)"},
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// AVX512-VP2INTERSECT: the pairwise intersection indices, one opmask
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// destination and two vector sources, EVEX.NDS.66.0F38. The instruction
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// takes no write mask of its own.
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{Name: "VP2INTERSECTD", Summary: "Store the indices of the first pairwise intersections of two dword vectors",
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Bytes: []byte{0x62, 0x02, 0x07, 0x40, 0x68, 0xC0}, Form: ExtFormAmdMask2, Feature: ExtFeatureVP2INTERSECT,
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Ref: "Intel SDM Vol. 2C, VP2INTERSECTD/VP2INTERSECTQ (EVEX.NDS.512.F2.0F38.W0 68 /r)"},
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{Name: "VP2INTERSECTD", Summary: "Store the indices of the first pairwise intersections of two dword vectors",
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Bytes: []byte{0x62, 0x02, 0x07, 0x20, 0x68, 0xC0}, Form: ExtFormAmdMask2, Feature: ExtFeatureVP2INTERSECT,
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Ref: "Intel SDM Vol. 2C, VP2INTERSECTD/VP2INTERSECTQ (EVEX.NDS.256.F2.0F38.W0 68 /r)"},
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{Name: "VP2INTERSECTD", Summary: "Store the indices of the first pairwise intersections of two dword vectors",
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Bytes: []byte{0x62, 0x02, 0x07, 0x00, 0x68, 0xC0}, Form: ExtFormAmdMask2, Feature: ExtFeatureVP2INTERSECT,
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Ref: "Intel SDM Vol. 2C, VP2INTERSECTD/VP2INTERSECTQ (EVEX.NDS.128.F2.0F38.W0 68 /r)"},
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{Name: "VP2INTERSECTQ", Summary: "Store the indices of the first pairwise intersections of two qword vectors",
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Bytes: []byte{0x62, 0x02, 0x87, 0x40, 0x68, 0xC0}, Form: ExtFormAmdMask2, Feature: ExtFeatureVP2INTERSECT,
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Ref: "Intel SDM Vol. 2C, VP2INTERSECTD/VP2INTERSECTQ (EVEX.NDS.512.F2.0F38.W1 68 /r)"},
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{Name: "VP2INTERSECTQ", Summary: "Store the indices of the first pairwise intersections of two qword vectors",
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Bytes: []byte{0x62, 0x02, 0x87, 0x20, 0x68, 0xC0}, Form: ExtFormAmdMask2, Feature: ExtFeatureVP2INTERSECT,
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Ref: "Intel SDM Vol. 2C, VP2INTERSECTD/VP2INTERSECTQ (EVEX.NDS.256.F2.0F38.W1 68 /r)"},
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{Name: "VP2INTERSECTQ", Summary: "Store the indices of the first pairwise intersections of two qword vectors",
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Bytes: []byte{0x62, 0x02, 0x87, 0x00, 0x68, 0xC0}, Form: ExtFormAmdMask2, Feature: ExtFeatureVP2INTERSECT,
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Ref: "Intel SDM Vol. 2C, VP2INTERSECTD/VP2INTERSECTQ (EVEX.NDS.128.F2.0F38.W1 68 /r)"},
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// AVX512-FP16, the scalar core: move, arithmetic, compare and
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// conversion on one half-precision value in the low XMM lane, the
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// register forms of the manual's scalar entries. The family lives in
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// the EVEX maps five and six the toolchain has never emitted, with the
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// mandatory prefixes the manual gives each entry; the golden vectors
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// pin every prefix byte for byte. LIG encodes as L'L = 00, the XMM
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// class alone.
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{Name: "VMOVSH", Summary: "Move a scalar FP16 value",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x10, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMOVSH (EVEX.NDS.LIG.F3.MAP5.W0 10 /r)"},
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{Name: "VMOVW", Summary: "Move a word between a general register and an XMM register",
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Bytes: []byte{0x62, 0x05, 0x05, 0x00, 0x6E, 0xC0}, Form: ExtFormAmdGprVec, Feature: ExtFeatureFP16, Wig: true,
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Ref: "Intel SDM Vol. 2C, VMOVW (EVEX.128.66.MAP5.WIG 6E /r)"},
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{Name: "VMOVW", Summary: "Move a word between an XMM register and a general register",
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|
Bytes: []byte{0x62, 0x05, 0x05, 0x00, 0x7E, 0xC0}, Form: ExtFormAmdVecGpr, Feature: ExtFeatureFP16, Wig: true,
|
|
Ref: "Intel SDM Vol. 2C, VMOVW (EVEX.128.66.MAP5.WIG 7E /r)"},
|
|
{Name: "VADDSH", Summary: "Add scalar FP16 values",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x58, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VADDSH (EVEX.NDS.LIG.F3.MAP5.W0 58 /r)"},
|
|
{Name: "VSUBSH", Summary: "Subtract scalar FP16 values",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VSUBSH (EVEX.NDS.LIG.F3.MAP5.W0 5C /r)"},
|
|
{Name: "VMULSH", Summary: "Multiply scalar FP16 values",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x59, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VMULSH (EVEX.NDS.LIG.F3.MAP5.W0 59 /r)"},
|
|
{Name: "VDIVSH", Summary: "Divide scalar FP16 values",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VDIVSH (EVEX.NDS.LIG.F3.MAP5.W0 5E /r)"},
|
|
{Name: "VMINSH", Summary: "Return the minimum of scalar FP16 values",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VMINSH (EVEX.NDS.LIG.F3.MAP5.W0 5D /r)"},
|
|
{Name: "VMAXSH", Summary: "Return the maximum of scalar FP16 values",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VMAXSH (EVEX.NDS.LIG.F3.MAP5.W0 5F /r)"},
|
|
{Name: "VSQRTSH", Summary: "Compute the square root of a scalar FP16 value",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x51, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VSQRTSH (EVEX.NDS.LIG.F3.MAP5.W0 51 /r)"},
|
|
{Name: "VCOMISH", Summary: "Compare a scalar FP16 value and set EFLAGS",
|
|
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x2F, 0xC0}, Form: ExtFormAmdVec2, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCOMISH (EVEX.LIG.MAP5.W0 2F /r)"},
|
|
{Name: "VUCOMISH", Summary: "Unordered-compare a scalar FP16 value and set EFLAGS",
|
|
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x2E, 0xC0}, Form: ExtFormAmdVec2, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VUCOMISH (EVEX.LIG.MAP5.W0 2E /r)"},
|
|
{Name: "VCVTSS2SH", Summary: "Convert one FP32 value to one FP16 value",
|
|
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x1D, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSS2SH (EVEX.NDS.LIG.MAP5.W0 1D /r)"},
|
|
{Name: "VCVTSH2SS", Summary: "Convert a low FP16 value to an FP32 value",
|
|
Bytes: []byte{0x62, 0x06, 0x04, 0x00, 0x13, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSH2SS (EVEX.NDS.LIG.MAP6.W0 13 /r)"},
|
|
{Name: "VCVTSH2SD", Summary: "Convert a low FP16 value to an FP64 value",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5A, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSH2SD (EVEX.NDS.LIG.F3.MAP5.W0 5A /r)"},
|
|
{Name: "VCVTSD2SH", Summary: "Convert one FP64 value to one FP16 value",
|
|
Bytes: []byte{0x62, 0x05, 0x87, 0x00, 0x5A, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSD2SH (EVEX.NDS.LIG.F2.MAP5.W1 5A /r)"},
|
|
{Name: "VCVTSI2SH", Summary: "Convert one signed 32-bit integer to one FP16 value",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x2A, 0xC0}, Form: ExtFormAmdVecGprVec, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSI2SH (EVEX.NDS.LIG.F3.MAP5.W0 2A /r)"},
|
|
{Name: "VCVTSI2SH", Summary: "Convert one signed 64-bit integer to one FP16 value",
|
|
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x2A, 0xC0}, Form: ExtFormAmdVecGprVec, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSI2SH (EVEX.NDS.LIG.F3.MAP5.W1 2A /r)"},
|
|
{Name: "VCVTUSI2SH", Summary: "Convert one unsigned 32-bit integer to one FP16 value",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x7B, 0xC0}, Form: ExtFormAmdVecGprVec, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTUSI2SH (EVEX.NDS.LIG.F3.MAP5.W0 7B /r)"},
|
|
{Name: "VCVTUSI2SH", Summary: "Convert one unsigned 64-bit integer to one FP16 value",
|
|
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x7B, 0xC0}, Form: ExtFormAmdVecGprVec, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTUSI2SH (EVEX.NDS.LIG.F3.MAP5.W1 7B /r)"},
|
|
{Name: "VCVTSH2SI", Summary: "Convert a low FP16 value to a signed 32-bit integer",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x2D, 0xC0}, Form: ExtFormAmdVecGpr, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSH2SI (EVEX.LIG.F3.MAP5.W0 2D /r)"},
|
|
{Name: "VCVTSH2SI", Summary: "Convert a low FP16 value to a signed 64-bit integer",
|
|
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x2D, 0xC0}, Form: ExtFormAmdVecGpr, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSH2SI (EVEX.LIG.F3.MAP5.W1 2D /r)"},
|
|
{Name: "VCVTSH2USI", Summary: "Convert a low FP16 value to an unsigned 32-bit integer",
|
|
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x79, 0xC0}, Form: ExtFormAmdVecGpr, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSH2USI (EVEX.LIG.F3.MAP5.W0 79 /r)"},
|
|
{Name: "VCVTSH2USI", Summary: "Convert a low FP16 value to an unsigned 64-bit integer",
|
|
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x79, 0xC0}, Form: ExtFormAmdVecGpr, Feature: ExtFeatureFP16,
|
|
Ref: "Intel SDM Vol. 2C, VCVTSH2USI (EVEX.LIG.F3.MAP5.W1 79 /r)"},
|
|
}
|