557 lines
18 KiB
Go
557 lines
18 KiB
Go
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import "fmt"
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// This file implements EVEX (AVX-512) instruction encoding: the four-byte
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// EVEX prefix with 5-bit vector register fields (Z0–Z31, X/Y 16–31), the
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// compressed disp8×N displacement, and the operand shapes the go-flac
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// AVX-512 kernels use. Masking ({k}) and zeroing ({z}) are not supported —
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// the kernels do not use them. K-register operands (mask destinations,
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// KMOVW, KTESTW) are.
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// evexSpec describes one EVEX instruction's encoding parameters. The form
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// field reuses the vexForm shapes, which carry over unchanged.
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type evexSpec struct {
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mapSel int // 1 = 0F, 2 = 0F38, 3 = 0F3A
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opcode byte
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w int
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pp int // 0 = none, 1 = 66, 2 = F3, 3 = F2
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opdigit int // ModRM.reg /digit, or -1 when reg is a register
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form vexForm // vexNDS3, vexRM, vexShiftImm, vexNDS3Imm, vexExtract
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n [3]int // disp8×N multiplier per vector length (128/256/512)
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}
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// evexTable maps an upper-case mnemonic to its EVEX encoding. Mnemonics
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// that also have a VEX form (VPADDD, VMOVUPD, …) are dispatched here only
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// when an operand demands EVEX (a ZMM or K register); EVEX-only mnemonics
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// (VPXORD, VALIGND, …) always encode through this table. The N multipliers
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// are taken from the Go assembler's opcode tables, which are authoritative
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// for byte-for-byte agreement.
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var evexTable = map[string]evexSpec{
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// EVEX.128/256/512.66.0F — integer arithmetic / logic, NDS form.
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"VPADDD": {1, 0xFE, 0, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPADDQ": {1, 0xD4, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPSUBD": {1, 0xFA, 0, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPSUBQ": {1, 0xFB, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPUNPCKLDQ": {1, 0x62, 0, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPUNPCKHDQ": {1, 0x6A, 0, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPXORD": {1, 0xEF, 0, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPXORQ": {1, 0xEF, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPCMPEQD": {1, 0x76, 0, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VFMADD231PD": {2, 0xB8, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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// EVEX.128/256/512.66.0F.W1 — packed double arithmetic.
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"VADDPD": {1, 0x58, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VMULPD": {1, 0x59, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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// EVEX.512.66.0F3A — align (NDS + imm8).
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"VALIGND": {3, 0x03, 0, 1, -1, vexNDS3Imm, [3]int{16, 32, 64}},
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// EVEX.128/256/512.66.0F — immediate shift (VPSRAD /4).
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"VPSRAD": {1, 0x72, 0, 1, 4, vexShiftImm, [3]int{16, 32, 64}},
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// EVEX.128/256/512.66.0F.W1 — variable shift with an XMM count (VPSRAQ;
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// the W bit distinguishes it from VPSRAD's E2 form).
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"VPSRAQ": {1, 0xE2, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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// EVEX.128/256/512.F3.0F.W1 — signed qword to packed double (reg=dst,
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// rm=src, no vvvv).
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"VCVTQQ2PD": {1, 0xE6, 1, 2, -1, vexRM, [3]int{16, 32, 64}},
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// EVEX.128/256/512.66.0F38.W0 — sign-extend dwords to qwords; the memory
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// operand is the narrow source, so disp8×N follows its size (8/16/32 for
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// the xmm/ymm/zmm destination lengths).
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"VPMOVSXDQ": {2, 0x25, 0, 1, -1, vexRM, [3]int{8, 16, 32}},
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// EVEX.512.66.0F3A.W1 — lane extract (reg=ZMM source, rm=YMM/memory
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// destination, imm8).
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"VEXTRACTI64X4": {3, 0x3B, 1, 1, -1, vexExtract, [3]int{0, 0, 32}},
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"VEXTRACTF64X4": {3, 0x1B, 1, 1, -1, vexExtract, [3]int{0, 0, 32}},
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// EVEX.66.0F38 — more integer NDS forms (W distinguishes D/Q).
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"VPMULLD": {2, 0x40, 0, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPMULLQ": {2, 0x40, 1, 1, -1, vexNDS3, [3]int{16, 32, 64}},
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"VPERMD": {2, 0x36, 0, 1, -1, vexNDS3, [3]int{0, 32, 64}},
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// EVEX.66.0F — immediate shift (VPSLLD /6).
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"VPSLLD": {1, 0x72, 0, 1, 6, vexShiftImm, [3]int{16, 32, 64}},
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// EVEX.F3.0F38.W0 — narrowing stores: reg = wide source, rm = narrow
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// destination (VPMOVDW dword→word, VPMOVQD qword→dword).
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"VPMOVDW": {2, 0x33, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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"VPMOVQD": {2, 0x35, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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}
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// evexBcastSpec describes an EVEX broadcast (VPBROADCASTD/Q): the opcode
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// depends on the source kind — a GPR source uses opReg, a memory source uses
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// opMem with a disp8×N of n.
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type evexBcastSpec struct {
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mapSel int
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opReg byte
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opMem byte
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w int
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n int
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}
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var evexBcastTable = map[string]evexBcastSpec{
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// EVEX.128/256/512.66.0F38 — broadcast a dword/qword to all lanes.
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"VPBROADCASTD": {2, 0x7C, 0x58, 0, 4},
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"VPBROADCASTQ": {2, 0x7C, 0x59, 1, 8},
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}
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// evexMoveSpec describes an EVEX move (load and store opcodes, like the VEX
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// move table).
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type evexMoveSpec struct {
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mapSel int
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pp int
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load byte // r/m → vector
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store byte // vector → r/m
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w int
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n [3]int
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}
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// evexMoveTable maps an upper-case EVEX move mnemonic to its encoding.
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var evexMoveTable = map[string]evexMoveSpec{
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// EVEX.128/256/512.F3.0F.W0 — unaligned integer move.
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"VMOVDQU32": {1, 2, 0x6F, 0x7F, 0, [3]int{16, 32, 64}},
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// EVEX.128/256/512.66.0F.W1 — unaligned packed double move.
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"VMOVUPD": {1, 1, 0x10, 0x11, 1, [3]int{16, 32, 64}},
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}
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// isEvex reports whether the mnemonic has an EVEX encoding we handle.
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func isEvex(mnemUpper string) bool {
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if _, ok := evexTable[mnemUpper]; ok {
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return true
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}
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if _, ok := evexBcastTable[mnemUpper]; ok {
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return true
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}
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_, ok := evexMoveTable[mnemUpper]
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return ok
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}
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// evexRequired reports whether the operands force the EVEX encoding of a
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// mnemonic that also has a VEX form: ZMM and K registers do, and so do
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// register indices 16–31, which only EVEX can represent (X16–Y31 exist
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// solely under AVX-512).
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func evexRequired(upper string, ops []Operand) bool {
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_, inVex := vexTable[upper]
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_, inVexMove := vexMoveTable[upper]
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if !inVex && !inVexMove {
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return true // EVEX-only mnemonic
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}
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for _, op := range ops {
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if r, ok := op.(Reg); ok && (r.size == 64 || r.mask || (r.isVec() && r.idx >= 16)) {
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return true
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}
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}
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return false
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}
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// encodeEvex encodes an EVEX instruction with operands in Plan 9 order.
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func (e *enc) encodeEvex(mnemUpper string, ops []Operand) error {
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if bs, ok := evexBcastTable[mnemUpper]; ok {
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return e.encodeEvexBcast(bs, ops)
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}
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if ms, ok := evexMoveTable[mnemUpper]; ok {
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return e.encodeEvexMove(mnemUpper, ms, ops)
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}
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spec, ok := evexTable[mnemUpper]
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if !ok {
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return fmt.Errorf("unsupported instruction %q for ZMM/K operands", mnemUpper)
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}
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switch spec.form {
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case vexNDS3:
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return e.encodeEvexNDS3(spec, ops)
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case vexRM:
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return e.encodeEvexRM(spec, ops)
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case vexRMRev:
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return e.encodeEvexRMRev(spec, ops)
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case vexShiftImm:
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return e.encodeEvexShiftImm(spec, ops)
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case vexNDS3Imm:
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return e.encodeEvexNDS3Imm(spec, ops)
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case vexExtract:
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return e.encodeEvexExtract(spec, ops)
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}
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return fmt.Errorf("unhandled EVEX form for %s", mnemUpper)
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}
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// encodeEvexNDS3 encodes the three-operand NDS form: OP src2, src1, dst. The
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// destination may be an opmask register (VPCMPEQD), in which case the vector
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// length comes from the sources.
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func (e *enc) encodeEvexNDS3(spec evexSpec, ops []Operand) error {
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if len(ops) != 3 {
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return fmt.Errorf("EVEX NDS instruction expects 3 operands, got %d", len(ops))
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}
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src2, src1, dst := ops[0], ops[1], ops[2]
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dstReg, ok := dst.(Reg)
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if !ok || (!dstReg.isVec() && !dstReg.mask) {
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return fmt.Errorf("EVEX destination must be a vector or mask register")
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}
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vvvvReg, ok := src1.(Reg)
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if !ok || !vvvvReg.isVec() {
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return fmt.Errorf("EVEX vvvv operand must be a vector register")
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}
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ll := dstReg.vecLenBit()
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if dstReg.mask {
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ll = vvvvReg.vecLenBit()
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if r, ok := src2.(Reg); ok && r.isVec() {
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ll = r.vecLenBit()
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}
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}
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return e.emitEvexFields(spec, ll, dstReg.idx, vvvvReg.idx, src2)
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}
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// encodeEvexRM encodes the two-operand form: OP src, dst (reg=dst, rm=src,
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// no vvvv), e.g. VCVTQQ2PD.
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func (e *enc) encodeEvexRM(spec evexSpec, ops []Operand) error {
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if len(ops) != 2 {
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return fmt.Errorf("EVEX two-operand instruction expects 2 operands, got %d", len(ops))
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}
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src, dst := ops[0], ops[1]
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dstReg, ok := dst.(Reg)
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if !ok || !dstReg.isVec() {
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return fmt.Errorf("EVEX destination must be a vector register")
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}
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return e.emitEvexFields(spec, dstReg.vecLenBit(), dstReg.idx, -1, src)
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}
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// encodeEvexShiftImm encodes an immediate shift: OP $imm, src, dst
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// (ModRM.reg = /digit, vvvv = dst, rm = src, imm8), e.g. VPSRAD $31, Z3, Z5.
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func (e *enc) encodeEvexShiftImm(spec evexSpec, ops []Operand) error {
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if len(ops) != 3 {
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return fmt.Errorf("EVEX shift expects 3 operands ($imm, src, dst), got %d", len(ops))
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}
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imm, src, dst := ops[0], ops[1], ops[2]
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immVal, ok := imm.(Imm)
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if !ok {
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return fmt.Errorf("shift count must be an immediate")
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}
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srcReg, ok := src.(Reg)
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if !ok || !srcReg.isVec() {
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return fmt.Errorf("shift source must be a vector register")
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}
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dstReg, ok := dst.(Reg)
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if !ok || !dstReg.isVec() {
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return fmt.Errorf("shift destination must be a vector register")
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}
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immByte, err := imm8(int64(immVal))
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if err != nil {
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return err
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}
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if err := e.emitEvexFields(spec, dstReg.vecLenBit(), spec.opdigit, dstReg.idx, srcReg); err != nil {
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return err
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}
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e.out = append(e.out, immByte)
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return nil
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}
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// encodeEvexNDS3Imm encodes OP $imm, src2, src1, dst (reg=dst, vvvv=src1,
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// rm=src2, imm8), e.g. VALIGND.
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func (e *enc) encodeEvexNDS3Imm(spec evexSpec, ops []Operand) error {
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if len(ops) != 4 {
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return fmt.Errorf("instruction expects 4 operands ($imm, src2, src1, dst), got %d", len(ops))
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}
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imm, src2, src1, dst := ops[0], ops[1], ops[2], ops[3]
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immVal, ok := imm.(Imm)
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if !ok {
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return fmt.Errorf("shuffle control must be an immediate")
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}
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dstReg, ok := dst.(Reg)
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if !ok || !dstReg.isVec() {
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return fmt.Errorf("destination must be a vector register")
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}
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vvvvReg, ok := src1.(Reg)
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if !ok || !vvvvReg.isVec() {
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return fmt.Errorf("second source must be a vector register")
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}
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immByte, err := imm8(int64(immVal))
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if err != nil {
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return err
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}
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if err := e.emitEvexFields(spec, dstReg.vecLenBit(), dstReg.idx, vvvvReg.idx, src2); err != nil {
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return err
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}
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e.out = append(e.out, immByte)
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return nil
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}
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// encodeEvexExtract encodes OP $imm, zsrc, ydst (reg=ZMM source, rm=YMM/memory
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// destination, imm8), e.g. VEXTRACTI64X4.
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func (e *enc) encodeEvexExtract(spec evexSpec, ops []Operand) error {
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if len(ops) != 3 {
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return fmt.Errorf("extract expects 3 operands ($imm, zsrc, ydst), got %d", len(ops))
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}
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imm, src, dst := ops[0], ops[1], ops[2]
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immVal, ok := imm.(Imm)
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if !ok {
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return fmt.Errorf("extract lane must be an immediate")
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}
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srcReg, ok := src.(Reg)
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if !ok || !srcReg.isVec() {
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return fmt.Errorf("extract source must be a vector register")
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}
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immByte, err := imm8(int64(immVal))
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if err != nil {
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return err
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}
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if err := e.emitEvexFields(spec, srcReg.vecLenBit(), srcReg.idx, -1, dst); err != nil {
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return err
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}
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e.out = append(e.out, immByte)
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return nil
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}
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// encodeEvexMove encodes a two-operand EVEX move; a vector→vector move uses
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// the store-form opcode (reg = source, rm = destination), matching the Go
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// assembler.
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func (e *enc) encodeEvexMove(mnem string, ms evexMoveSpec, ops []Operand) error {
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if len(ops) != 2 {
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return fmt.Errorf("EVEX move expects 2 operands, got %d", len(ops))
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}
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src, dst := ops[0], ops[1]
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srcReg, srcIsVec := vecReg(src)
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dstReg, dstIsVec := vecReg(dst)
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op := ms.store
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var reg Reg
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var rm Operand
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switch {
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case srcIsVec && dstIsVec:
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reg, rm = srcReg, dst
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case srcIsVec:
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if !memOperand(dst) {
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return fmt.Errorf("%s: invalid destination operand", mnem)
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}
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reg, rm = srcReg, dst
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case dstIsVec:
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if !memOperand(src) {
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return fmt.Errorf("%s: invalid source operand", mnem)
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}
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op = ms.load
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reg, rm = dstReg, src
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default:
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return fmt.Errorf("%s needs a vector register operand", mnem)
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}
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spec := evexSpec{mapSel: ms.mapSel, opcode: op, w: ms.w, pp: ms.pp, opdigit: -1, n: ms.n}
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return e.emitEvexFields(spec, reg.vecLenBit(), reg.idx, -1, rm)
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}
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// memOperand reports whether op is a memory reference (including a
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// static-symbol reference).
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func memOperand(op Operand) bool {
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switch op.(type) {
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case Mem, sbMem:
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return true
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}
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return false
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}
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// encodeEvexRMRev encodes the narrowing-store form: OP src, dst with the wide
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// source in the reg field and the narrow destination in r/m (VPMOVDW/QD).
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func (e *enc) encodeEvexRMRev(spec evexSpec, ops []Operand) error {
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if len(ops) != 2 {
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return fmt.Errorf("EVEX store instruction expects 2 operands, got %d", len(ops))
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}
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src, dst := ops[0], ops[1]
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srcReg, ok := src.(Reg)
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if !ok || !srcReg.isVec() {
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return fmt.Errorf("EVEX source must be a vector register")
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}
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return e.emitEvexFields(spec, srcReg.vecLenBit(), srcReg.idx, -1, dst)
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}
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// encodeEvexBcast encodes VPBROADCASTD/Q: OP src, dst with the GPR or memory
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// source broadcast to every lane of the vector destination.
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func (e *enc) encodeEvexBcast(bs evexBcastSpec, ops []Operand) error {
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if len(ops) != 2 {
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return fmt.Errorf("broadcast expects 2 operands, got %d", len(ops))
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}
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src, dst := ops[0], ops[1]
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dstReg, ok := dst.(Reg)
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if !ok || !dstReg.isVec() {
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return fmt.Errorf("broadcast destination must be a vector register")
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}
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spec := evexSpec{mapSel: bs.mapSel, w: bs.w, pp: 1, opdigit: -1}
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switch src.(type) {
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case Mem, sbMem:
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spec.opcode = bs.opMem
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spec.n = [3]int{bs.n, bs.n, bs.n}
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case Reg:
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spec.opcode = bs.opReg
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default:
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return fmt.Errorf("broadcast source must be a register or memory")
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}
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return e.emitEvexFields(spec, dstReg.vecLenBit(), dstReg.idx, -1, src)
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}
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// emitEvexFields emits the EVEX prefix, opcode, ModR/M, SIB and displacement
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// (disp8×N compressed) for the given precomputed fields. regIdx is the
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// unextended reg-field register index, or a /digit (0–7); vvvvIdx is the
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// vvvv register index, or -1 when unused.
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func (e *enc) emitEvexFields(spec evexSpec, ll, regIdx, vvvvIdx int, rm Operand) error {
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if ll > 2 {
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return fmt.Errorf("invalid vector length")
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}
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// reg-field extension bits (R̄, R'̄), inverted.
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rBar, rPrimeBar := 1, 1
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if regIdx&8 != 0 {
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rBar = 0
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}
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if regIdx&16 != 0 {
|
||
rPrimeBar = 0
|
||
}
|
||
// vvvv (inverted) and its extension bit V'̄.
|
||
vBar, vPrimeBar := 15, 1
|
||
if vvvvIdx >= 0 {
|
||
vBar = 15 - (vvvvIdx & 15)
|
||
if vvvvIdx&16 != 0 {
|
||
vPrimeBar = 0
|
||
}
|
||
}
|
||
|
||
var modrm, sib int
|
||
var disp []byte
|
||
xBar, bBar := 1, 1
|
||
var sb *sbRef
|
||
switch r := rm.(type) {
|
||
case Reg:
|
||
// ModRM.mod = 11: rm[3] extends via B̄, rm[4] via X̄.
|
||
modrm = 0xC0 | (regIdx&7)<<3 | (r.idx & 7)
|
||
sib = -1
|
||
if r.idx&8 != 0 {
|
||
bBar = 0
|
||
}
|
||
if r.idx&16 != 0 {
|
||
xBar = 0
|
||
}
|
||
case Mem:
|
||
var err error
|
||
modrm, sib, disp, xBar, bBar, err = memComponentsEvex(regIdx&7, r, spec.n[ll])
|
||
if err != nil {
|
||
return err
|
||
}
|
||
// An indexed memory operand carries index[4] in V'̄ (Go folds it
|
||
// together with vvvv[4] into the same bit).
|
||
if r.HasIndex && r.Index.idx&16 != 0 {
|
||
vPrimeBar = 0
|
||
}
|
||
case sbMem:
|
||
// RIP-relative static-symbol reference; disp32 patched at link time
|
||
// (no disp8 scaling for RIP-relative addressing).
|
||
modrm = (regIdx&7)<<3 | 0x05
|
||
sib = -1
|
||
disp = le32(0)
|
||
sb = &sbRef{name: r.name, addend: r.addend}
|
||
default:
|
||
return fmt.Errorf("invalid EVEX r/m operand")
|
||
}
|
||
|
||
p0 := byte(rBar<<7 | xBar<<6 | bBar<<5 | rPrimeBar<<4 | spec.mapSel)
|
||
p1 := byte(spec.w<<7 | vBar<<3 | 1<<2 | spec.pp)
|
||
p2 := byte(ll<<5 | vPrimeBar<<3) // z = 0, b = 0, aaa = 0
|
||
e.out = append(e.out, 0x62, p0, p1, p2, spec.opcode, byte(modrm))
|
||
if sib >= 0 {
|
||
e.out = append(e.out, byte(sib))
|
||
}
|
||
if sb != nil {
|
||
e.patches = append(e.patches, encPatch{off: len(e.out), name: sb.name, addend: sb.addend})
|
||
}
|
||
e.out = append(e.out, disp...)
|
||
return nil
|
||
}
|
||
|
||
// memComponentsEvex computes the ModR/M byte (with the given reg field), the
|
||
// SIB byte (-1 if none), the displacement bytes and the (inverted sense)
|
||
// index/base extension bits for an EVEX memory operand. The displacement is
|
||
// compressed to disp8×N when it is a multiple of n and the quotient fits a
|
||
// signed byte; otherwise a full disp32 is used.
|
||
func memComponentsEvex(regField int, m Mem, n int) (modrm, sib int, disp []byte, xBar, bBar int, err error) {
|
||
sib = -1
|
||
xBar, bBar = 1, 1 // inverted bits: 1 = no extension
|
||
if !m.HasBase && !m.HasIndex {
|
||
return regField<<3 | 0x05, -1, le32(m.Disp), 1, 1, nil // RIP-relative
|
||
}
|
||
|
||
needSIB := m.HasIndex || (m.HasBase && m.Base.idx&7 == 4)
|
||
|
||
var mod int
|
||
switch {
|
||
case !m.HasBase:
|
||
mod = 0
|
||
disp = le32(m.Disp)
|
||
case m.Base.idx&7 == 5 && m.Disp == 0:
|
||
mod = 1
|
||
disp = []byte{0}
|
||
case m.Disp == 0:
|
||
mod = 0
|
||
case n > 0 && m.Disp%int64(n) == 0 && m.Disp/int64(n) >= -128 && m.Disp/int64(n) <= 127:
|
||
mod = 1
|
||
disp = []byte{byte(int8(m.Disp / int64(n)))}
|
||
default:
|
||
mod = 2
|
||
disp = le32(m.Disp)
|
||
}
|
||
|
||
if needSIB {
|
||
idxField := 4 // 100 = no index
|
||
if m.HasIndex {
|
||
idxField = m.Index.idx & 7
|
||
if m.Index.idx&8 != 0 {
|
||
xBar = 0
|
||
}
|
||
}
|
||
baseField := 5 // 101 = no base (with mod=00 → disp32)
|
||
if m.HasBase {
|
||
baseField = m.Base.idx & 7
|
||
if m.Base.idx&8 != 0 {
|
||
bBar = 0
|
||
}
|
||
}
|
||
return mod<<6 | regField<<3 | 0x04, scaleBits(m.Scale)<<6 | idxField<<3 | baseField, disp, xBar, bBar, nil
|
||
}
|
||
|
||
if m.Base.idx&8 != 0 {
|
||
bBar = 0
|
||
}
|
||
return mod<<6 | regField<<3 | (m.Base.idx & 7), -1, disp, 1, bBar, nil
|
||
}
|
||
|
||
// encodeKmovw encodes KMOVW, whose opcode depends on the operand direction:
|
||
// 90 (k/mem → K), 91 (K → mem), 92 (GPR → K), 93 (K → GPR); k → k uses 90.
|
||
func (e *enc) encodeKmovw(ops []Operand) error {
|
||
if len(ops) != 2 {
|
||
return fmt.Errorf("KMOVW expects 2 operands, got %d", len(ops))
|
||
}
|
||
src, dst := ops[0], ops[1]
|
||
srcReg, srcIsReg := src.(Reg)
|
||
dstReg, dstIsReg := dst.(Reg)
|
||
srcK := srcIsReg && srcReg.mask
|
||
dstK := dstIsReg && dstReg.mask
|
||
spec := vexSpec{mapSel: 1, w: 0, pp: 0, opdigit: -1}
|
||
switch {
|
||
case srcK && dstK:
|
||
spec.opcode = 0x90 // k ← k: reg = dst, rm = src
|
||
return e.emitVexFields(spec, 0, dstReg.idx&7, 0, 15, src)
|
||
case srcK && dstIsReg:
|
||
spec.opcode = 0x93 // GPR ← k: reg = dst, rm = src
|
||
rBit := 0
|
||
if dstReg.idx >= 8 {
|
||
rBit = 1
|
||
}
|
||
return e.emitVexFields(spec, 0, dstReg.idx&7, rBit, 15, src)
|
||
case srcK:
|
||
if _, ok := dst.(Mem); !ok {
|
||
return fmt.Errorf("KMOVW: invalid destination operand")
|
||
}
|
||
spec.opcode = 0x91 // mem ← k: reg = src, rm = dst
|
||
return e.emitVexFields(spec, 0, srcReg.idx&7, 0, 15, dst)
|
||
case dstK:
|
||
spec.opcode = 0x92 // k ← GPR/mem: reg = dst, rm = src
|
||
return e.emitVexFields(spec, 0, dstReg.idx&7, 0, 15, src)
|
||
}
|
||
return fmt.Errorf("KMOVW requires a K register operand")
|
||
}
|