333 lines
16 KiB
Go
333 lines
16 KiB
Go
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import (
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"strings"
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"testing"
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"golang.org/x/arch/x86/x86asm"
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)
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func vreg(t *testing.T, name string) Reg {
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t.Helper()
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r, ok := ParseReg(name)
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if !ok {
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t.Fatalf("unknown register %s", name)
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}
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return r
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}
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// TestVexNDS3 encodes `mnem Y0, Y1, Y2` for every three-operand NDS
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// instruction and verifies it round-trips through the x86 decoder to the same
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// mnemonic. A wrong opcode/map/pp surfaces as a different decoded instruction.
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func TestVexNDS3(t *testing.T) {
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for mnem, spec := range vexTable {
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if spec.form != vexNDS3 {
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continue
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}
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// Scalar (F2/F3 pp) instructions exist only in the 128-bit form.
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vec := "Y"
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if spec.pp >= 2 {
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vec = "X"
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}
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code, err := Encode(mnem, vreg(t, vec+"0"), vreg(t, vec+"1"), vreg(t, vec+"2"))
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if err != nil {
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t.Errorf("%s: Encode: %v", mnem, err)
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continue
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}
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inst, err := x86asm.Decode(code, 64)
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if err != nil {
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t.Errorf("%s: Decode(% x): %v", mnem, code, err)
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continue
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}
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if inst.Op.String() != mnem {
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t.Errorf("%s: decoded as %s (% x)", mnem, inst.Op.String(), code)
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}
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}
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}
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// TestVexGoFlac checks a representative go-flac instruction sequence encodes
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// and decodes as expected.
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func TestVexGoFlac(t *testing.T) {
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// VPADDD Y5, Y8, Y8 → vpaddd ymm8, ymm8, ymm5.
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code, err := Encode("VPADDD", vreg(t, "Y5"), vreg(t, "Y8"), vreg(t, "Y8"))
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if err != nil {
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t.Fatalf("Encode: %v", err)
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}
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inst, err := x86asm.Decode(code, 64)
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if err != nil {
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t.Fatalf("Decode(% x): %v", code, err)
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}
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if inst.Op != x86asm.VPADDD {
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t.Fatalf("decoded %s, want VPADDD", inst.Op)
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}
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}
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// TestVexXMM checks the 128-bit (XMM) form selects VEX.L=0.
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func TestVexXMM(t *testing.T) {
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code, err := Encode("VPXOR", vreg(t, "X7"), vreg(t, "X7"), vreg(t, "X7"))
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if err != nil {
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t.Fatalf("Encode: %v", err)
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}
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inst, err := x86asm.Decode(code, 64)
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if err != nil {
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t.Fatalf("Decode(% x): %v", code, err)
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}
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if inst.Op != x86asm.VPXOR {
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t.Fatalf("decoded %s, want VPXOR", inst.Op)
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}
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// vpxor xmm7, xmm7, xmm7 → C5 C1 EF FF (2-byte VEX, L=0).
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if code[0] != 0xC5 {
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t.Errorf("expected 2-byte VEX (C5), got % x", code)
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}
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}
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// TestVexRM validates the two-operand (reg=dst, rm=src, no vvvv) forms by
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// round-tripping through the decoder.
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func TestVexRM(t *testing.T) {
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cases := []struct {
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mnem string
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ops []Operand
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want x86asm.Op
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}{
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{"VPMOVSXWD", []Operand{Ptr(SI, 0, 16), vreg(t, "Y0")}, x86asm.VPMOVSXWD},
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{"VPMOVSXDQ", []Operand{vreg(t, "X0"), vreg(t, "Y4")}, x86asm.VPMOVSXDQ},
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{"VPMOVZXDQ", []Operand{vreg(t, "X4"), vreg(t, "Y4")}, x86asm.VPMOVZXDQ},
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{"VPBROADCASTD", []Operand{vreg(t, "X0"), vreg(t, "Y15")}, x86asm.VPBROADCASTD},
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{"VPMOVMSKB", []Operand{vreg(t, "X11"), AX}, x86asm.VPMOVMSKB},
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{"VMOVMSKPS", []Operand{vreg(t, "Y7"), AX}, x86asm.VMOVMSKPS},
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}
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for _, c := range cases {
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code, err := Encode(c.mnem, c.ops...)
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if err != nil {
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t.Errorf("%s: Encode: %v", c.mnem, err)
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continue
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}
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inst, err := x86asm.Decode(code, 64)
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if err != nil {
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t.Errorf("%s: Decode(% x): %v", c.mnem, code, err)
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continue
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}
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if inst.Op != c.want {
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t.Errorf("%s: decoded as %s (% x)", c.mnem, inst.Op, code)
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}
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}
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}
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// TestVexShiftImm validates the immediate-shift form, checking the destination
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// (VEX.vvvv) and source (ModRM.rm) land in the right places.
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func TestVexShiftImm(t *testing.T) {
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// VPSLLD $1, Y3, Y4 → vpslld ymm4, ymm3, 1.
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code, err := Encode("VPSLLD", Imm(1), vreg(t, "Y3"), vreg(t, "Y4"))
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if err != nil {
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t.Fatalf("Encode: %v", err)
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}
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inst, err := x86asm.Decode(code, 64)
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if err != nil {
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t.Fatalf("Decode(% x): %v", code, err)
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}
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if inst.Op != x86asm.VPSLLD {
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t.Fatalf("decoded %s, want VPSLLD (% x)", inst.Op, code)
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}
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// Intel order: dst, src, imm → "vpslld ymm4, ymm3, 0x1".
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if got := x86asm.IntelSyntax(inst, 0, nil); got != "vpslld ymm4, ymm3, 0x1" {
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t.Errorf("VPSLLD syntax = %q, want \"vpslld ymm4, ymm3, 0x1\" (% x)", got, code)
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}
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// VPSRAD $31, Y3, Y3 → vpsrad ymm3, ymm3, 31.
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code, err = Encode("VPSRAD", Imm(31), vreg(t, "Y3"), vreg(t, "Y3"))
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if err != nil {
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t.Fatalf("Encode VPSRAD: %v", err)
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}
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inst, err = x86asm.Decode(code, 64)
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if err != nil || inst.Op != x86asm.VPSRAD {
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t.Fatalf("VPSRAD decoded %v (err %v), want VPSRAD", inst.Op, err)
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}
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}
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// TestVexGroundTruth checks byte-for-byte agreement with the real Go
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// assembler. The expected bytes were extracted from the machine code the Go
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// toolchain produced for exactly these instructions (go build + a .text
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// section dump of the resulting binary), never from a disassembler's
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// rendering. This locks the v̄vvv = 1111 rule for unused vvvv fields (a
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// value the hardware rejects with #UD and the x86 decoder silently ignores)
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// as well as every new operand form.
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func TestVexGroundTruth(t *testing.T) {
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cases := []struct {
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name string
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mnem string
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ops []Operand
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want string
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}{
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// Three-operand NDS form.
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{"VPADDQ Y8,Y9,Y8", "VPADDQ", []Operand{vreg(t, "Y8"), vreg(t, "Y9"), vreg(t, "Y8")}, "c44135d4c0"},
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{"VPADDQ X9,X8,X8", "VPADDQ", []Operand{vreg(t, "X9"), vreg(t, "X8"), vreg(t, "X8")}, "c44139d4c1"},
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{"VPXOR X7,X7,X7", "VPXOR", []Operand{vreg(t, "X7"), vreg(t, "X7"), vreg(t, "X7")}, "c5c1efff"},
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{"VPSHUFB Y1,Y2,Y3", "VPSHUFB", []Operand{vreg(t, "Y1"), vreg(t, "Y2"), vreg(t, "Y3")}, "c4e26d00d9"},
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{"VPMULLD Y1,Y2,Y3", "VPMULLD", []Operand{vreg(t, "Y1"), vreg(t, "Y2"), vreg(t, "Y3")}, "c4e26d40d9"},
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{"VPUNPCKLDQ Y4,Y3,Y5", "VPUNPCKLDQ", []Operand{vreg(t, "Y4"), vreg(t, "Y3"), vreg(t, "Y5")}, "c5e562ec"},
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{"VPERMD Y1,Y2,Y3", "VPERMD", []Operand{vreg(t, "Y1"), vreg(t, "Y2"), vreg(t, "Y3")}, "c4e26d36d9"},
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// Floating point (packed and scalar) and FMA — same NDS form, the pp
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// bits and map select the operation.
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{"VADDPD Y9,Y8,Y8", "VADDPD", []Operand{vreg(t, "Y9"), vreg(t, "Y8"), vreg(t, "Y8")}, "c4413d58c1"},
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{"VADDPD X1,X2,X3", "VADDPD", []Operand{vreg(t, "X1"), vreg(t, "X2"), vreg(t, "X3")}, "c5e958d9"},
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{"VMULPD Y12,Y12,Y12", "VMULPD", []Operand{vreg(t, "Y12"), vreg(t, "Y12"), vreg(t, "Y12")}, "c4411d59e4"},
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{"VXORPD Y8,Y8,Y8", "VXORPD", []Operand{vreg(t, "Y8"), vreg(t, "Y8"), vreg(t, "Y8")}, "c4413d57c0"},
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{"VUNPCKHPD X8,X8,X9", "VUNPCKHPD", []Operand{vreg(t, "X8"), vreg(t, "X8"), vreg(t, "X9")}, "c4413915c8"},
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{"VADDSD X9,X8,X8", "VADDSD", []Operand{vreg(t, "X9"), vreg(t, "X8"), vreg(t, "X8")}, "c4413b58c1"},
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{"VMULSD X0,X1,X1", "VMULSD", []Operand{vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X1")}, "c5f359c8"},
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{"VFMADD231PD Y14,Y12,Y8", "VFMADD231PD", []Operand{vreg(t, "Y14"), vreg(t, "Y12"), vreg(t, "Y8")}, "c4429db8c6"},
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{"VFMADD231PD (DI),Y12,Y8", "VFMADD231PD", []Operand{Ptr(DI, 0, 32), vreg(t, "Y12"), vreg(t, "Y8")}, "c4629db807"},
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// Two-operand reg/rm form (v̄vvv must be 1111).
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{"VPMOVSXDQ X0,Y4", "VPMOVSXDQ", []Operand{vreg(t, "X0"), vreg(t, "Y4")}, "c4e27d25e0"},
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{"VPMOVSXWD (SI),Y0", "VPMOVSXWD", []Operand{Ptr(SI, 0, 8), vreg(t, "Y0")}, "c4e27d2306"},
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{"VPBROADCASTD X0,Y15", "VPBROADCASTD", []Operand{vreg(t, "X0"), vreg(t, "Y15")}, "c4627d58f8"},
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{"VCVTDQ2PD X12,Y12", "VCVTDQ2PD", []Operand{vreg(t, "X12"), vreg(t, "Y12")}, "c4417ee6e4"},
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{"VCVTDQ2PD (SI),Y4", "VCVTDQ2PD", []Operand{Ptr(SI, 0, 16), vreg(t, "Y4")}, "c5fee626"},
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{"VPMOVMSKB X11,AX", "VPMOVMSKB", []Operand{vreg(t, "X11"), AX}, "c4c179d7c3"},
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{"VMOVMSKPS Y7,AX", "VMOVMSKPS", []Operand{vreg(t, "Y7"), AX}, "c5fc50c7"},
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// Immediate shifts.
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{"VPSLLD $1,Y3,Y4", "VPSLLD", []Operand{Imm(1), vreg(t, "Y3"), vreg(t, "Y4")}, "c5dd72f301"},
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{"VPSRLQ $2,Y5,Y6", "VPSRLQ", []Operand{Imm(2), vreg(t, "Y5"), vreg(t, "Y6")}, "c5cd73d502"},
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// Variable-count shifts: the count lives in an XMM register or memory
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// and the instruction takes the NDS form.
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{"VPSRLQ X0,Y8,Y8", "VPSRLQ", []Operand{vreg(t, "X0"), vreg(t, "Y8"), vreg(t, "Y8")}, "c53dd3c0"},
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{"VPSRLQ (AX),Y8,Y8", "VPSRLQ", []Operand{Ptr(AX, 0, 16), vreg(t, "Y8"), vreg(t, "Y8")}, "c53dd300"},
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{"VPSLLD X0,Y1,Y2", "VPSLLD", []Operand{vreg(t, "X0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c5f5f2d0"},
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{"VPSRLD X0,Y1,Y2", "VPSRLD", []Operand{vreg(t, "X0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c5f5d2d0"},
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{"VPSRAD X0,Y1,Y2", "VPSRAD", []Operand{vreg(t, "X0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c5f5e2d0"},
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{"VPSLLQ X0,Y1,Y2", "VPSLLQ", []Operand{vreg(t, "X0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c5f5f3d0"},
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// Immediate shuffle (reg=dst, rm=src, imm8).
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{"VPSHUFD $0xEE,X8,X9", "VPSHUFD", []Operand{Imm(0xEE), vreg(t, "X8"), vreg(t, "X9")}, "c4417970c8ee"},
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{"VPSHUFD $0xEE,Y1,Y2", "VPSHUFD", []Operand{Imm(0xEE), vreg(t, "Y1"), vreg(t, "Y2")}, "c5fd70d1ee"},
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{"VPERMQ $0x1B,Y1,Y2", "VPERMQ", []Operand{Imm(0x1B), vreg(t, "Y1"), vreg(t, "Y2")}, "c4e3fd00d11b"},
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{"VPERMQ $0x1B,Y11,Y12", "VPERMQ", []Operand{Imm(0x1B), vreg(t, "Y11"), vreg(t, "Y12")}, "c443fd00e31b"},
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// Three-operand + immediate (reg=dst, vvvv=src1, rm=src2, imm8).
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{"VSHUFPD $1,X1,X2,X3", "VSHUFPD", []Operand{Imm(1), vreg(t, "X1"), vreg(t, "X2"), vreg(t, "X3")}, "c5e9c6d901"},
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{"VSHUFPD $1,Y1,Y2,Y3", "VSHUFPD", []Operand{Imm(1), vreg(t, "Y1"), vreg(t, "Y2"), vreg(t, "Y3")}, "c5edc6d901"},
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{"VPERM2I128 $0x31,Y1,Y2,Y3", "VPERM2I128", []Operand{Imm(0x31), vreg(t, "Y1"), vreg(t, "Y2"), vreg(t, "Y3")}, "c4e36d46d931"},
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{"VINSERTI128 $1,X5,Y1,Y2", "VINSERTI128", []Operand{Imm(1), vreg(t, "X5"), vreg(t, "Y1"), vreg(t, "Y2")}, "c4e37538d501"},
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// Lane extract (reg=YMM source, rm=XMM/memory destination, imm8).
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{"VEXTRACTI128 $1,Y8,X9", "VEXTRACTI128", []Operand{Imm(1), vreg(t, "Y8"), vreg(t, "X9")}, "c4437d39c101"},
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{"VEXTRACTI128 $1,Y8,(DI)", "VEXTRACTI128", []Operand{Imm(1), vreg(t, "Y8"), Ptr(DI, 0, 16)}, "c4637d390701"},
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{"VEXTRACTF128 $1,Y8,X9", "VEXTRACTF128", []Operand{Imm(1), vreg(t, "Y8"), vreg(t, "X9")}, "c4437d19c101"},
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// Moves — each direction picks its own opcode and VEX.W.
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{"VMOVDQU (SI),Y1", "VMOVDQU", []Operand{Ptr(SI, 0, 32), vreg(t, "Y1")}, "c5fe6f0e"},
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{"VMOVDQU Y3,(DI)", "VMOVDQU", []Operand{vreg(t, "Y3"), Ptr(DI, 0, 32)}, "c5fe7f1f"},
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{"VMOVDQU X1,X2", "VMOVDQU", []Operand{vreg(t, "X1"), vreg(t, "X2")}, "c5fa7fca"},
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{"VMOVUPD (DI),Y14", "VMOVUPD", []Operand{Ptr(DI, 0, 32), vreg(t, "Y14")}, "c57d1037"},
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{"VMOVUPD Y14,(DI)", "VMOVUPD", []Operand{vreg(t, "Y14"), Ptr(DI, 0, 32)}, "c57d1137"},
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{"VMOVUPD X1,X2", "VMOVUPD", []Operand{vreg(t, "X1"), vreg(t, "X2")}, "c5f911ca"},
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{"VMOVQ X8,AX", "VMOVQ", []Operand{vreg(t, "X8"), AX}, "c461f97ec0"},
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{"VMOVQ AX,X9", "VMOVQ", []Operand{AX, vreg(t, "X9")}, "c461f96ec8"},
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{"VMOVQ X8,(DI)", "VMOVQ", []Operand{vreg(t, "X8"), Ptr(DI, 0, 8)}, "c461f97e07"},
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{"VMOVQ (SI),X9", "VMOVQ", []Operand{Ptr(SI, 0, 8), vreg(t, "X9")}, "c461f96e0e"},
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{"VMOVQ X8,X2", "VMOVQ", []Operand{vreg(t, "X8"), vreg(t, "X2")}, "c579d6c2"},
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{"VMOVQ X2,X8", "VMOVQ", []Operand{vreg(t, "X2"), vreg(t, "X8")}, "c4c179d6d0"},
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{"VMOVD X0,(SI)", "VMOVD", []Operand{vreg(t, "X0"), Ptr(SI, 0, 4)}, "c5f97e06"},
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{"VMOVD AX,X0", "VMOVD", []Operand{AX, vreg(t, "X0")}, "c5f96ec0"},
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{"VMOVSD (SI),X8", "VMOVSD", []Operand{Ptr(SI, 0, 8), vreg(t, "X8")}, "c57b1006"},
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{"VMOVSD X8,(SI)", "VMOVSD", []Operand{vreg(t, "X8"), Ptr(SI, 0, 8)}, "c57b1106"},
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// No-operand.
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{"VZEROUPPER", "VZEROUPPER", nil, "c5f877"},
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}
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for _, c := range cases {
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code, err := Encode(c.mnem, c.ops...)
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if err != nil {
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t.Errorf("%s: Encode: %v", c.name, err)
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continue
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}
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if got := strings.ReplaceAll(hexBytes(code), " ", ""); got != c.want {
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t.Errorf("%s: bytes %s, want %s", c.name, got, c.want)
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continue
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}
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inst, err := x86asm.Decode(code, 64)
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if err != nil {
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t.Errorf("%s: Decode(% x): %v", c.name, code, err)
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continue
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}
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if inst.Len != len(code) {
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t.Errorf("%s: Decode consumed %d of %d bytes", c.name, inst.Len, len(code))
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}
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if inst.Op.String() != c.mnem {
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t.Errorf("%s: decoded as %s", c.name, inst.Op.String())
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}
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}
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}
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// TestVexNewFormsSyntax checks the decoded Intel-syntax rendering of the new
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// SIMD forms (operand order is the decoder's, confirming the fields landed).
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func TestVexNewFormsSyntax(t *testing.T) {
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checkSyntax(t, "vpshufd xmm9, xmm8, 0xee", "VPSHUFD", Imm(0xEE), vreg(t, "X8"), vreg(t, "X9"))
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checkSyntax(t, "vpermq ymm2, ymm1, 0x1b", "VPERMQ", Imm(0x1B), vreg(t, "Y1"), vreg(t, "Y2"))
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checkSyntax(t, "vextracti128 xmm9, ymm8, 0x1", "VEXTRACTI128", Imm(1), vreg(t, "Y8"), vreg(t, "X9"))
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checkSyntax(t, "vinserti128 ymm2, ymm1, xmm5, 0x1", "VINSERTI128", Imm(1), vreg(t, "X5"), vreg(t, "Y1"), vreg(t, "Y2"))
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checkSyntax(t, "vperm2i128 ymm3, ymm2, ymm1, 0x31", "VPERM2I128", Imm(0x31), vreg(t, "Y1"), vreg(t, "Y2"), vreg(t, "Y3"))
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checkSyntax(t, "vpermd ymm3, ymm2, ymm1", "VPERMD", vreg(t, "Y1"), vreg(t, "Y2"), vreg(t, "Y3"))
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checkSyntax(t, "vshufpd xmm3, xmm2, xmm1, 0x1", "VSHUFPD", Imm(1), vreg(t, "X1"), vreg(t, "X2"), vreg(t, "X3"))
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checkSyntax(t, "vmovq rax, xmm8", "VMOVQ", vreg(t, "X8"), AX)
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checkSyntax(t, "vmovq xmm9, rax", "VMOVQ", AX, vreg(t, "X9"))
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checkSyntax(t, "vmovdqu ymm1, ymmword ptr [rsi]", "VMOVDQU", Ptr(SI, 0, 32), vreg(t, "Y1"))
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checkSyntax(t, "vmovdqu ymmword ptr [rdi], ymm3", "VMOVDQU", vreg(t, "Y3"), Ptr(DI, 0, 32))
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checkSyntax(t, "vzeroupper", "VZEROUPPER")
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}
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|
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// TestVexMemoryForms round-trips the new forms with memory sources/destinations,
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// covering the SIB/indexed path through the VEX prefix emitter.
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func TestVexMemoryForms(t *testing.T) {
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checkSyntax(t, "vpshufd ymm1, ymmword ptr [rsi], 0x4e", "VPSHUFD", Imm(0x4E), Ptr(SI, 0, 32), vreg(t, "Y1"))
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checkSyntax(t, "vinserti128 ymm2, ymm1, xmmword ptr [rdi], 0x1", "VINSERTI128", Imm(1), Ptr(DI, 0, 16), vreg(t, "Y1"), vreg(t, "Y2"))
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checkSyntax(t, "vmovdqu ymm1, ymmword ptr [rax+4*rbx]", "VMOVDQU", Idx(AX, BX, 4, 0, 32), vreg(t, "Y1"))
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checkSyntax(t, "vpermq ymm2, ymmword ptr [rsi], 0x1b", "VPERMQ", Imm(0x1B), Ptr(SI, 0, 32), vreg(t, "Y2"))
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checkSyntax(t, "vfmadd231pd ymm8, ymm12, ymm14", "VFMADD231PD", vreg(t, "Y14"), vreg(t, "Y12"), vreg(t, "Y8"))
|
|
checkSyntax(t, "vcvtdq2pd ymm12, xmmword ptr [rsi]", "VCVTDQ2PD", Ptr(SI, 0, 16), vreg(t, "Y12"))
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|
// The top and bottom of the accepted imm8 span: $255 and $-1 both encode
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// an all-bits-set control.
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|
checkSyntax(t, "vpshufd xmm1, xmm0, 0xff", "VPSHUFD", Imm(255), vreg(t, "X0"), vreg(t, "X1"))
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checkSyntax(t, "vpshufd xmm1, xmm0, 0xff", "VPSHUFD", Imm(-1), vreg(t, "X0"), vreg(t, "X1"))
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|
}
|
|
|
|
// TestVexErrors checks that invalid operand shapes are rejected.
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|
func TestVexErrors(t *testing.T) {
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|
cases := []struct {
|
|
name string
|
|
mnem string
|
|
ops []Operand
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|
}{
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|
{"VPSHUFD arity", "VPSHUFD", []Operand{vreg(t, "X0"), vreg(t, "X1")}},
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|
{"VPSHUFD non-imm control", "VPSHUFD", []Operand{vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X2")}},
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|
{"VPSHUFD gpr dst", "VPSHUFD", []Operand{Imm(1), vreg(t, "X0"), AX}},
|
|
{"VEXTRACTI128 arity", "VEXTRACTI128", []Operand{Imm(1), vreg(t, "Y0")}},
|
|
{"VEXTRACTI128 non-vec src", "VEXTRACTI128", []Operand{Imm(1), AX, vreg(t, "X0")}},
|
|
{"VINSERTI128 arity", "VINSERTI128", []Operand{Imm(1), vreg(t, "X0"), vreg(t, "Y1")}},
|
|
{"VINSERTI128 non-vec vvvv", "VINSERTI128", []Operand{Imm(1), vreg(t, "X0"), AX, vreg(t, "Y1")}},
|
|
{"VPERM2I128 non-imm control", "VPERM2I128", []Operand{AX, vreg(t, "Y0"), vreg(t, "Y1"), vreg(t, "Y2")}},
|
|
{"VMOVSD reg-reg", "VMOVSD", []Operand{vreg(t, "X1"), vreg(t, "X2")}},
|
|
{"VMOVD reg-reg", "VMOVD", []Operand{vreg(t, "X1"), vreg(t, "X2")}},
|
|
{"VMOVQ ymm", "VMOVQ", []Operand{vreg(t, "Y1"), AX}},
|
|
{"VMOVQ mixed X/Y", "VMOVQ", []Operand{vreg(t, "X1"), vreg(t, "Y2")}},
|
|
{"VMOVQ no vector", "VMOVQ", []Operand{AX, BX}},
|
|
{"VMOVDQU gpr", "VMOVDQU", []Operand{AX, vreg(t, "Y1")}},
|
|
{"VMOVUPD gpr", "VMOVUPD", []Operand{vreg(t, "X1"), AX}},
|
|
{"VZEROUPPER operands", "VZEROUPPER", []Operand{AX}},
|
|
{"VPSLLD non-vec dst", "VPSLLD", []Operand{Imm(1), vreg(t, "Y0"), AX}},
|
|
{"VPSLLD non-imm count", "VPSLLD", []Operand{AX, vreg(t, "Y0"), vreg(t, "Y1")}},
|
|
{"VPSLLD non-vec src", "VPSLLD", []Operand{Imm(1), AX, vreg(t, "Y1")}},
|
|
{"VPADDD non-vec vvvv", "VPADDD", []Operand{vreg(t, "Y0"), AX, vreg(t, "Y1")}},
|
|
{"VEXTRACTI128 non-imm lane", "VEXTRACTI128", []Operand{AX, vreg(t, "Y0"), vreg(t, "X0")}},
|
|
{"VMOVQ imm operand", "VMOVQ", []Operand{Imm(1), vreg(t, "X0")}},
|
|
{"VPSHUFD imm rm", "VPSHUFD", []Operand{Imm(1), Imm(2), vreg(t, "X0")}},
|
|
{"VPSHUFD imm range", "VPSHUFD", []Operand{Imm(256), vreg(t, "X0"), vreg(t, "X1")}},
|
|
{"VPERMQ imm range", "VPERMQ", []Operand{Imm(300), vreg(t, "Y0"), vreg(t, "Y1")}},
|
|
{"VEXTRACTI128 imm range", "VEXTRACTI128", []Operand{Imm(256), vreg(t, "Y0"), vreg(t, "X0")}},
|
|
{"VPSLLD imm range", "VPSLLD", []Operand{Imm(-129), vreg(t, "Y0"), vreg(t, "Y1")}},
|
|
}
|
|
for _, c := range cases {
|
|
if _, err := Encode(c.mnem, c.ops...); err == nil {
|
|
t.Errorf("%s: expected an error, got none", c.name)
|
|
}
|
|
}
|
|
}
|