feat(arch): the SVE2 three-source and bitwise combine families

Assisted-by: GLM 5.3 Flash

asm/arm64_ext_asm_test.go

@@ -794,6 +794,18 @@ func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
 		{"ZLSR Z15.B, Z0.B, P3.M, Z0.B", 0x04118de0},
 		{"ZLSR Z7.D, Z6.H, Z13.H", 0x046784cd},
 		{"ZLSRR Z15.B, Z0.B, P3.M, Z0.B", 0x04158de0},
+		// The three-source and bitwise combine families.
+		{"ZBCAX Z23.D, Z13.D, Z21.D, Z21.D", 0x046d3af5},
+		{"ZEOR3 Z23.D, Z13.D, Z21.D, Z21.D", 0x042d3af5},
+		{"ZBSL Z23.D, Z13.D, Z21.D, Z21.D", 0x042d3ef5},
+		{"ZBSL1N Z23.D, Z13.D, Z21.D, Z21.D", 0x046d3ef5},
+		{"ZBSL2N Z23.D, Z13.D, Z21.D, Z21.D", 0x04ad3ef5},
+		{"ZNBSL Z23.D, Z13.D, Z21.D, Z21.D", 0x04ed3ef5},
+		{"ZBDEP Z7.D, Z23.D, Z13.D", 0x45c7b6ed},
+		{"ZBEXT Z7.D, Z23.D, Z13.D", 0x45c7b2ed},
+		{"ZBGRP Z7.D, Z23.D, Z13.D", 0x45c7baed},
+		{"ZEORBT Z7.D, Z23.D, Z13.D", 0x45c792ed},
+		{"ZEORTB Z7.D, Z23.D, Z13.D", 0x45c796ed},
 	}
 	for _, tt := range tests {
 		words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")

asm/extension_test.go

@@ -304,6 +304,17 @@ func TestExtensionNamesARM64(t *testing.T) {
 		"ZLSLR",
 		"ZLSR",
 		"ZLSRR",
+		"ZBCAX",
+		"ZBDEP",
+		"ZBEXT",
+		"ZBGRP",
+		"ZBSL",
+		"ZBSL1N",
+		"ZBSL2N",
+		"ZEOR3",
+		"ZEORBT",
+		"ZEORTB",
+		"ZNBSL",
 		// The stage-three families: the SVE2 crypto group, the predicate
 		// counters and loop terminators with the 32-bit while compares, and
 		// the reductions into a SIMD register.
@@ -416,7 +427,7 @@ func TestExtensionNamesARM64(t *testing.T) {
 	if strings.Join(got, ",") != strings.Join(want, ",") {
 		t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
 	}
-	if n := len(arch.Extensions(arch.ARM64)); n != 414 {
-		t.Errorf("the family registers %d instructions, want 414", n)
+	if n := len(arch.Extensions(arch.ARM64)); n != 425 {
+		t.Errorf("the family registers %d instructions, want 425", n)
 	}
 }