feat(arch): the SVE2 shift-by-vector family
Assisted-by: GLM 5.3 Flash
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@@ -679,6 +679,11 @@ const (
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// the predicate in the narrow governing field and the vector in the
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// destination slot, the reduction class's own layout.
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ExtFormQuadReduce
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// ExtFormShiftWide is the wide-vector shift, ZASR Z7.D, Z6.H, Z13.H:
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// the shift amounts ride a double-width vector locked to .D while the
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// shifted data shares one narrower arrangement, which feeds the size
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// field. Operands: Zm.D, Zn.T, Zd.T.
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ExtFormShiftWide
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)
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// Arity returns the operand count the form takes.
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@@ -716,7 +721,7 @@ func (f ExtForm) Arity() int {
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return 2
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case ExtFormReduceReadBack:
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return 4
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case ExtFormSveLoad, ExtFormSveStore, ExtFormNarrow, ExtFormQuadReduce:
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case ExtFormSveLoad, ExtFormSveStore, ExtFormNarrow, ExtFormQuadReduce, ExtFormShiftWide:
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return 3
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case ExtFormNone:
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return 0
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@@ -787,7 +792,7 @@ func (f ExtForm) Kinds() []ExtOperandKind {
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return []ExtOperandKind{ExtSveMem, ExtPReg, ExtZReg}
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case ExtFormSveStore:
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return []ExtOperandKind{ExtZReg, ExtPReg, ExtSveMem}
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case ExtFormNarrow:
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case ExtFormNarrow, ExtFormShiftWide:
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return []ExtOperandKind{ExtZReg, ExtZReg, ExtZReg}
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case ExtFormQuadReduce:
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return []ExtOperandKind{ExtZReg, ExtPReg, ExtVReg}
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@@ -917,6 +922,8 @@ func (f ExtForm) String() string {
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return "narrowing two-to-one"
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case ExtFormQuadReduce:
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return "quadword reduction"
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case ExtFormShiftWide:
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return "wide shift"
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case ExtFormNone:
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return "no operands"
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default:
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@@ -1173,6 +1180,8 @@ func (in ExtInstr) Encode(ops []ExtOperand) ([]byte, error) {
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return in.encodeNarrow(ops)
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case ExtFormQuadReduce:
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return in.encodeQuadReduce(ops)
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case ExtFormShiftWide:
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return in.encodeShiftWide(ops)
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case ExtFormNone:
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if len(ops) != 0 {
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return nil, fmt.Errorf("%s: the %s form takes no operands, got %d",
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@@ -2629,6 +2638,42 @@ func (in ExtInstr) encodeQuadReduce(ops []ExtOperand) ([]byte, error) {
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return extWordLE(word), nil
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}
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// encodeShiftWide fills the wide-vector shift: Zm.D, Zn.T, Zd.T. The shift
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// amounts ride a double-width vector locked to .D while the shifted data
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// carries one shared narrower arrangement, which feeds the size field.
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func (in ExtInstr) encodeShiftWide(ops []ExtOperand) ([]byte, error) {
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zm, zn, zd := ops[0], ops[1], ops[2]
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if err := in.zVector(zm, 1); err != nil {
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return nil, err
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}
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if zm.Arr != ExtArrD {
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return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .D",
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in.Name, zm.Arr)
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}
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if err := in.zVector(zn, 2); err != nil {
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return nil, err
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}
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if err := in.zVector(zd, 3); err != nil {
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return nil, err
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}
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if zn.Arr != zd.Arr {
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return nil, fmt.Errorf("%s: operands 2 and 3 carry arrangements %s and %s, they must match",
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in.Name, zn.Arr, zd.Arr)
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}
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size, err := in.zSize(zn.Arr)
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if err != nil {
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return nil, err
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}
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word := in.Word
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word = extSet(word, extFieldRm, uint32(zm.Reg))
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word = extSet(word, extFieldRn, uint32(zn.Reg))
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word = extSet(word, extFieldRd, uint32(zd.Reg))
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if size != 0 {
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word = extSet(word, in.Size, size)
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}
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return extWordLE(word), nil
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}
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// sharedSize returns the one element-size encoding the given arrangements
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// agree on, or an error when any operand is bare, they disagree, or the
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// arrangement has no size field.
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@@ -3259,6 +3304,44 @@ var arm64Extensions = []ExtInstr{
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Word: 0x040f2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZUMINQV; inst_gen.go + arm64sveenc.s"},
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// --- the SVE2 shift-by-vector family --------------------------------------
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//
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// The arithmetic, logical and rounding shift steps over a vector of
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// shift amounts: the predicated-source shapes share one arrangement,
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// and the wide three-vector shape takes its amounts from a double-width
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// vector locked to .D. The shift-by-immediate shapes of the same
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// mnemonics (the tsz:imm3 class) are not wired yet. Provenance as
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// above: the toolchain encoding table and its generated corpus, both
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// produced from Arm's official ISA description, and the golden test
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// pins every corpus line of the covered shapes.
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{Name: "ZASR", Summary: "Shift right arithmetic by a vector, merging",
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Word: 0x04108000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZASR; inst_gen.go + arm64sveenc.s"},
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{Name: "ZASR", Summary: "Shift right arithmetic by a wide vector, unpredicated",
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Word: 0x04208000, Form: ExtFormShiftWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZASR; inst_gen.go + arm64sveenc.s"},
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{Name: "ZASRR", Summary: "Shift right arithmetic by a vector with rounding, merging",
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Word: 0x04148000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZASRR; inst_gen.go + arm64sveenc.s"},
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{Name: "ZLSL", Summary: "Shift left by a vector, merging",
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Word: 0x04138000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZLSL; inst_gen.go + arm64sveenc.s"},
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{Name: "ZLSL", Summary: "Shift left by a wide vector, unpredicated",
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Word: 0x04208c00, Form: ExtFormShiftWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZLSL; inst_gen.go + arm64sveenc.s"},
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{Name: "ZLSLR", Summary: "Shift left by a vector with rounding, merging",
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Word: 0x04178000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZLSLR; inst_gen.go + arm64sveenc.s"},
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{Name: "ZLSR", Summary: "Shift right logical by a vector, merging",
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Word: 0x04118000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZLSR; inst_gen.go + arm64sveenc.s"},
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{Name: "ZLSR", Summary: "Shift right logical by a wide vector, unpredicated",
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Word: 0x04208400, Form: ExtFormShiftWide, Size: extSizeBHSD, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZLSR; inst_gen.go + arm64sveenc.s"},
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{Name: "ZLSRR", Summary: "Shift right logical by a vector with rounding, merging",
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Word: 0x04158000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZLSRR; inst_gen.go + arm64sveenc.s"},
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// --- the SVE2 crypto family ----------------------------------------------
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//
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// The multi-precision carry steps (ADCLB, ADCLT, SBCLB, SBCLT), the SHA3
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@@ -1440,6 +1440,37 @@ func TestArm64ExtStage4Golden(t *testing.T) {
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{"ZFMINQV Z25.S, P3, V5.S4", "ZFMINQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x6497af25},
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// The shift-by-vector family.
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{"ZASR Z15.B, Z0.B, P3.M, Z0.B", "ZASR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
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0x04108de0},
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{"ZASR Z2.D, Z10.D, P3.M, Z10.D", "ZASR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(2, ExtArrD), ExtVector(10, ExtArrD), ExtPredicate(3, ExtQualMerging), ExtVector(10, ExtArrD)},
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0x04d08c4a},
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{"ZASR Z7.D, Z6.H, Z13.H", "ZASR", ExtFormShiftWide, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrH), ExtVector(13, ExtArrH)},
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0x046780cd},
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{"ZASRR Z15.B, Z0.B, P3.M, Z0.B", "ZASRR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
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0x04148de0},
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{"ZLSL Z2.D, Z10.D, P3.M, Z10.D", "ZLSL", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(2, ExtArrD), ExtVector(10, ExtArrD), ExtPredicate(3, ExtQualMerging), ExtVector(10, ExtArrD)},
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0x04d38c4a},
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{"ZLSL Z7.D, Z6.H, Z13.H", "ZLSL", ExtFormShiftWide, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrH), ExtVector(13, ExtArrH)},
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0x04678ccd},
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{"ZLSLR Z15.B, Z0.B, P3.M, Z0.B", "ZLSLR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
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0x04178de0},
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{"ZLSR Z15.B, Z0.B, P3.M, Z0.B", "ZLSR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
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0x04118de0},
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{"ZLSR Z7.D, Z6.H, Z13.H", "ZLSR", ExtFormShiftWide, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrH), ExtVector(13, ExtArrH)},
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0x046784cd},
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{"ZLSRR Z15.B, Z0.B, P3.M, Z0.B", "ZLSRR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
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0x04158de0},
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} {
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in := extInstructionMeta(t, tt.mnem, tt.form, tt.qual, tt.arr)
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got, err := in.Encode(tt.ops)
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@@ -783,6 +783,17 @@ func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
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{"ZFMAXQV Z25.S, P3, V5.S4", 0x6496af25},
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{"ZFMINNMQV Z25.S, P3, V5.S4", 0x6495af25},
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{"ZFMINQV Z25.S, P3, V5.S4", 0x6497af25},
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// The shift-by-vector family.
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{"ZASR Z15.B, Z0.B, P3.M, Z0.B", 0x04108de0},
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{"ZASR Z2.D, Z10.D, P3.M, Z10.D", 0x04d08c4a},
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{"ZASR Z7.D, Z6.H, Z13.H", 0x046780cd},
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{"ZASRR Z15.B, Z0.B, P3.M, Z0.B", 0x04148de0},
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{"ZLSL Z2.D, Z10.D, P3.M, Z10.D", 0x04d38c4a},
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{"ZLSL Z7.D, Z6.H, Z13.H", 0x04678ccd},
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{"ZLSLR Z15.B, Z0.B, P3.M, Z0.B", 0x04178de0},
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{"ZLSR Z15.B, Z0.B, P3.M, Z0.B", 0x04118de0},
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{"ZLSR Z7.D, Z6.H, Z13.H", 0x046784cd},
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{"ZLSRR Z15.B, Z0.B, P3.M, Z0.B", 0x04158de0},
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}
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for _, tt := range tests {
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words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
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@@ -298,6 +298,12 @@ func TestExtensionNamesARM64(t *testing.T) {
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"ZSMINQV",
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"ZUMAXQV",
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"ZUMINQV",
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"ZASR",
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"ZASRR",
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"ZLSL",
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"ZLSLR",
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"ZLSR",
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"ZLSRR",
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// The stage-three families: the SVE2 crypto group, the predicate
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// counters and loop terminators with the 32-bit while compares, and
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// the reductions into a SIMD register.
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@@ -410,7 +416,7 @@ func TestExtensionNamesARM64(t *testing.T) {
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if strings.Join(got, ",") != strings.Join(want, ",") {
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t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
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}
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if n := len(arch.Extensions(arch.ARM64)); n != 405 {
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t.Errorf("the family registers %d instructions, want 405", n)
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if n := len(arch.Extensions(arch.ARM64)); n != 414 {
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t.Errorf("the family registers %d instructions, want 414", n)
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}
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}
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