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feat(arch): the SVE2 three-source and bitwise combine families

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 20:35:41 +02:00
1 parent bd80499c74
commit 0760cc91af
4 files changed
+144 -3
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asm/arm64_ext_asm_test.go
+12
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@@ -794,6 +794,18 @@ func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
{"ZLSR Z15.B, Z0.B, P3.M, Z0.B", 0x04118de0},
{"ZLSR Z7.D, Z6.H, Z13.H", 0x046784cd},
{"ZLSRR Z15.B, Z0.B, P3.M, Z0.B", 0x04158de0},
// The three-source and bitwise combine families.
{"ZBCAX Z23.D, Z13.D, Z21.D, Z21.D", 0x046d3af5},
{"ZEOR3 Z23.D, Z13.D, Z21.D, Z21.D", 0x042d3af5},
{"ZBSL Z23.D, Z13.D, Z21.D, Z21.D", 0x042d3ef5},
{"ZBSL1N Z23.D, Z13.D, Z21.D, Z21.D", 0x046d3ef5},
{"ZBSL2N Z23.D, Z13.D, Z21.D, Z21.D", 0x04ad3ef5},
{"ZNBSL Z23.D, Z13.D, Z21.D, Z21.D", 0x04ed3ef5},
{"ZBDEP Z7.D, Z23.D, Z13.D", 0x45c7b6ed},
{"ZBEXT Z7.D, Z23.D, Z13.D", 0x45c7b2ed},
{"ZBGRP Z7.D, Z23.D, Z13.D", 0x45c7baed},
{"ZEORBT Z7.D, Z23.D, Z13.D", 0x45c792ed},
{"ZEORTB Z7.D, Z23.D, Z13.D", 0x45c796ed},
}
for _, tt := range tests {
words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")