fix(asm): route the riscv64 register moves through the toolchain forms
Assisted-by: GLM 5.3
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petrbalvin committed
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da35883633
commit
36d1ac804a
1 file changed
+209
-9
+209
-9
@@ -6,8 +6,10 @@ package asm
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import (
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"errors"
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"fmt"
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"math"
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"math/bits"
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"slices"
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"strconv"
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"strings"
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"sourcedock.dev/petrbalvin/gasm-sdk/ast"
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@@ -368,6 +370,17 @@ func riscvInstrSize(instr *ast.Instr, fi riscvFrameInfo) int {
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return len(riscvReturn(fi))
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}
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if strings.HasPrefix(mnem, "MOV") && len(ops) == 2 {
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// FP constant: FMV from X0 for a zero bit pattern, otherwise the
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// 8-byte AUIPC + FLW/FLD pool load.
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if (mnem == "MOVF" || mnem == "MOVD") && isImmOperand(ops[0]) &&
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!ops[0].Imm.HasVal && ops[0].Imm.Sym == nil && ops[0].Imm.Str == "" {
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if pattern, _, err := riscvFPConstBits(mnem, ops[0]); err == nil {
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if pattern == 0 {
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return 4
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}
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return 8
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}
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}
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// MOV $sym(SB), rd → 8 bytes (AUIPC + ADDI).
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if isImmOperand(ops[0]) && ops[0].Imm.Sym != nil && ops[0].Imm.Sym.Pseudo == "SB" {
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return 8
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@@ -410,6 +423,29 @@ func riscvInstrSize(instr *ast.Instr, fi riscvFrameInfo) int {
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if isMemOperand(ops[1]) && !isMemOperand(ops[0]) {
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return riscvFrameMemSize(ops[1], fi)
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}
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// Register-to-register width moves: the SLLI + SRAI/SRLI extension
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// pairs carry their per-half compression; the single-word forms are
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// four bytes before the RVC pass (bare MOV compresses to C.MV or
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// C.LI, which the post-encoding pass resolves from real bytes).
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if !isMemOperand(ops[0]) && !isMemOperand(ops[1]) {
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rd := regFromOperand(ops[1])
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rs1 := regFromOperand(ops[0])
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switch mnem {
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case "MOVB", "MOVH":
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shamt := 56
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if mnem == "MOVH" {
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shamt = 48
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}
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return len(riscvExtendBytes(rd, rs1, shamt, true))
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case "MOVHU", "MOVWU":
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shamt := 48
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if mnem == "MOVWU" {
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shamt = 32
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}
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return len(riscvExtendBytes(rd, rs1, shamt, false))
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}
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return 4
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}
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}
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// I-type arithmetic with a large immediate expands to several instructions.
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if (mnem == "ADDI" || mnem == "ANDI" || mnem == "ORI" || mnem == "XORI") && len(ops) >= 1 && isImmOperand(ops[0]) {
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@@ -1831,6 +1867,43 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc, lits *
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// Immediate → register.
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if isImmOperand(src) {
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mnem := strings.ToUpper(instr.Mnemonic.Text)
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// FP constant → FP register: a zero bit pattern moves through FMV
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// from X0, anything else loads from the pooled $f32/$f64 constant
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// symbol the toolchain synthesises (AUIPC + FLW/FLD through TMP).
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// An integer constant is not an FP load source, exactly as the
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// toolchain rejects the non-FCONST forms.
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if (mnem == "MOVF" || mnem == "MOVD") && !src.Imm.HasVal && src.Imm.Sym == nil && src.Imm.Str == "" {
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rd := regFromOperand(dst)
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if rd < 0 || !riscvIsFloatRegOperand(dst) {
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return nil, fmt.Errorf("%s $float: invalid destination register", mnem)
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}
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pattern, _, err := riscvFPConstBits(mnem, src)
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if err != nil {
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return nil, fmt.Errorf("%s: invalid floating-point constant %q", mnem, src.Imm.Float)
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}
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if pattern == 0 {
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op := uint32(0x78) << 25 // FMV.W.X
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if mnem == "MOVD" {
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op = uint32(0x79) << 25 // FMV.D.X
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}
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return wordLE(op | uint32(rd)<<7 | 0x53), nil
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}
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var name string
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var data []byte
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double := mnem == "MOVD"
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if double {
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name = fmt.Sprintf("$f64.%016x", pattern)
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data = riscvLiteralBytes(int64(pattern))
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} else {
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name = fmt.Sprintf("$f32.%08x", uint32(pattern))
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data = []byte{byte(pattern), byte(pattern >> 8), byte(pattern >> 16), byte(pattern >> 24)}
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}
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if lits != nil {
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lits.add(name, data)
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}
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return encodeRISCVSBFPLoad(name, rd, double, relocs), nil
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}
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// MOV $sym(SB), rd, load address of a static symbol or external.
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if src.Imm.Sym != nil && src.Imm.Sym.Pseudo == "SB" {
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rd := regFromOperand(dst)
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@@ -1874,7 +1947,6 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc, lits *
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// Memory → register (load).
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if isMemOperand(src) && !isMemOperand(dst) {
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rd := regFromOperand(dst)
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// MOV sym(SB), rd, load from static data.
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if src.Addr.Sym != nil && src.Addr.Sym.Pseudo == "SB" {
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if rd < 0 {
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return nil, fmt.Errorf("MOV sym(SB): invalid destination register")
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@@ -1891,7 +1963,6 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc, lits *
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// Register → memory (store).
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if !isMemOperand(src) && isMemOperand(dst) {
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rs2 := regFromOperand(src)
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// MOV rd, sym(SB), store to static data.
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if dst.Addr.Sym != nil && dst.Addr.Sym.Pseudo == "SB" {
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if rs2 < 0 {
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return nil, fmt.Errorf("MOV rd, sym(SB): invalid source register")
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@@ -1905,8 +1976,12 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc, lits *
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return riscvFrameMemOp(riscvMovEnc(strings.ToUpper(instr.Mnemonic.Text), true), true, rs2, rs1, off), nil
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}
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// Register → register: MOVD/MOVF are FP moves (fsgnj with rs2 = rs1),
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// everything else is ADDI $0, src, dst.
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// Register → register. The width suffix selects the toolchain's
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// synthesis: MOVF/MOVD between the integer and FP banks are FMV and
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// inside the FP bank FSGNJ with rs2 = rs1; MOVW is ADDIW $0; MOVBU is
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// ANDI $255; MOVB and MOVH sign-extend through SLLI+SRAI and MOVHU/
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// MOVWU zero-extend through SLLI+SRLI; bare MOV is ADDI $0, which the
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// RVC pass compresses.
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{
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rs1 := regFromOperand(src)
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rd := regFromOperand(dst)
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@@ -1914,12 +1989,50 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc, lits *
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return nil, fmt.Errorf("MOV: invalid register operand")
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}
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mnem := strings.ToUpper(instr.Mnemonic.Text)
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if mnem == "MOVD" || mnem == "MOVF" {
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op := uint32(0x20000053) // FSGNJ.S
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if mnem == "MOVD" {
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op = 0x22000053 // FSGNJ.D
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srcF, dstF := riscvIsFloatRegOperand(src), riscvIsFloatRegOperand(dst)
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switch mnem {
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case "MOVF", "MOVD":
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switch {
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case srcF && dstF:
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op := uint32(0x20000053) // FSGNJ.S
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if mnem == "MOVD" {
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op = 0x22000053 // FSGNJ.D
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}
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return wordLE(op | uint32(rs1)<<15 | uint32(rs1)<<20 | uint32(rd)<<7), nil
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case dstF && !srcF:
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op := uint32(0x78) << 25 // FMV.W.X
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if mnem == "MOVD" {
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op = uint32(0x79) << 25 // FMV.D.X
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}
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return wordLE(op | uint32(rs1)<<15 | uint32(rd)<<7 | 0x53), nil
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case srcF && !dstF:
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op := uint32(0x70) << 25 // FMV.X.W
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if mnem == "MOVD" {
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op = uint32(0x71) << 25 // FMV.X.D
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}
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return wordLE(op | uint32(rs1)<<15 | uint32(rd)<<7 | 0x53), nil
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}
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return wordLE(op | uint32(rs1)<<15 | uint32(rs1)<<20 | uint32(rd)<<7), nil
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return nil, fmt.Errorf("%s: both registers must be in the same bank", mnem)
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case "MOVW":
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// ADDIW $0, rs, rd; the two-operand-only form never has
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// rd == rs1 in real sources, and the toolchain's C.ADDIW
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// forbids a zero immediate, so the word stays uncompressed.
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return wordLE(riscvIType(riscvEnc{0x1B, 0x0, 0x00}, rd, rs1, 0)), nil
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case "MOVBU":
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// ANDI $255, rs, rd; 255 never fits C.ANDI's six signed bits.
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return wordLE(riscvIType(riscvEnc{0x13, 0x7, 0x00}, rd, rs1, 0xFF)), nil
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case "MOVB", "MOVH":
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shamt := 56
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if mnem == "MOVH" {
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shamt = 48
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}
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return riscvExtendBytes(rd, rs1, shamt, true), nil
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case "MOVHU", "MOVWU":
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shamt := 48
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if mnem == "MOVWU" {
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shamt = 32
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}
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return riscvExtendBytes(rd, rs1, shamt, false), nil
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}
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word := riscvIType(riscvEnc{0x13, 0x0, 0x00}, rd, rs1, 0)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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@@ -2238,6 +2351,93 @@ func riscvLiteralBytes(v int64) []byte {
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byte(v >> 32), byte(v >> 40), byte(v >> 48), byte(v >> 56)}
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}
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// riscvIsFloatRegOperand reports whether the operand spells a floating-point
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// register: every F-bank spelling starts with F, and the one integer name
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// that does (FP, the frame pointer alias of X8) is excluded.
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func riscvIsFloatRegOperand(op *ast.Operand) bool {
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name := ""
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if op.Addr.Base != "" {
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name = op.Addr.Base
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} else if op.Addr.Sym != nil {
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name = op.Addr.Sym.Name
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}
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return name != "FP" && strings.HasPrefix(name, "F")
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}
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// riscvFPConstBits resolves an FP constant operand to the bit pattern the
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// toolchain moves or pools: MOVF narrows through float32 first, MOVD keeps
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// the float64 bits. The bare spelling fills Imm.Float and the parenthesised
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// one ($ (709.78…)) leaves only the raw text, exactly as on arm64.
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func riscvFPConstBits(mnem string, src *ast.Operand) (uint64, bool, error) {
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text := src.Imm.Float
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if text == "" {
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s := strings.Join(strings.Fields(src.Raw), "")
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s = strings.TrimPrefix(s, "$")
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if strings.HasPrefix(s, "(") && strings.HasSuffix(s, ")") &&
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strings.ContainsAny(s[1:len(s)-1], ".eE") {
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text = s[1 : len(s)-1]
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}
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}
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if text == "" {
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return 0, false, fmt.Errorf("not a floating-point constant")
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}
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f, err := strconv.ParseFloat(text, 64)
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if err != nil {
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return 0, false, err
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}
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if src.Imm.Neg {
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f = -f
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}
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if mnem == "MOVF" {
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return uint64(math.Float32bits(float32(f))), false, nil
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}
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return math.Float64bits(f), true, nil
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}
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// riscvExtendBytes emits the SLLI + SRAI/SRLI pair the toolchain synthesises
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// for the MOVB/MOVH/MOVHU/MOVWU register moves, with the per-half compression
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// its compress pass applies: the SLLI compresses only in place (rd == rs1),
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// the SRAI/SRLI only for the prime registers X8 to X15.
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func riscvExtendBytes(rd, rs1, shamt int, arithmetic bool) []byte {
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var out []byte
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if rd == rs1 && rd != 0 {
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out = word16(rvcSLLI(uint32(rd), uint32(shamt)))
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} else {
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out = wordLE(riscvIType(riscvEnc{0x13, 0x1, 0x00}, rd, rs1, int32(shamt)))
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}
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if isRVCIntReg(rd) {
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funct2 := uint32(0x0)
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if arithmetic {
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funct2 = 0x1
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}
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out = append(out, word16(rvcCBShift(funct2, rvcReg3(rd), uint32(shamt)))...)
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} else {
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imm := int32(shamt)
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if arithmetic {
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imm = 0x400 | int32(shamt) // funct6 010000, the SRAI half
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}
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out = append(out, wordLE(riscvIType(riscvEnc{0x13, 0x5, 0x00}, rd, rd, imm))...)
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}
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return out
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}
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// encodeRISCVSBFPLoad emits AUIPC X31 + FLW/FLD against a pooled constant
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// symbol, the toolchain's form for an FP destination: the address lands in
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// TMP because the destination register is not an integer one. The single
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// R_RISCV_PCREL_ITYPE relocation covers the pair.
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func encodeRISCVSBFPLoad(name string, rd int, double bool, relocs *[]Reloc) []byte {
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if relocs != nil {
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*relocs = append(*relocs, Reloc{Off: 0, After: 8, Name: name, Kind: RelRISCVPCRELIType})
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}
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auipc := riscvUType(riscvEnc{0x17, 0x0, 0x00}, 31, 0)
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width := uint32(0x2) // FLW
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if double {
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width = 0x3 // FLD
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}
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fl := riscvIType(riscvEnc{0x07, width, 0x00}, rd, 31, 0)
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return append(wordLE(auipc), wordLE(fl)...)
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}
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// RiscvLiteral is one pooled 64-bit constant: a MOV whose immediate sits
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// beyond both the 32-bit span and the shift sequences loads its bits from a
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// read-only data symbol named like the toolchain's $i64 pool.
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