feat(asm): encode the arm64 register-offset addressing forms
Assisted-by: GLM 5.3 Flash
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@@ -2008,6 +2008,14 @@ func encodeARM64MemOp(mnem string, mem *ast.Operand, reg int, load bool, fi arm6
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lt = a64LoadTable["MOVD"]
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}
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// Register-offset addressing: (Rn)(Rm), (Rn)(Rm<<k), (Rn)(Rm.UXTW) and
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// friends. The toolchain accepts the LSL (UXTX), UXTW, SXTW and SXTX
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// options with a shift amount of either zero or the access size's log2,
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// rejects every other spelling, and rejects the whole form on FMOVQ.
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if mem.Addr.Index != "" {
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return encodeARM64RegOffset(mnem, mem, rn, reg, load, lt, wb)
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}
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scale := a64LSScale(lt)
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storeOpc := a64StoreOpc(lt)
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var opc int
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@@ -2094,7 +2102,78 @@ func arm64PoolAccess(mnem string, lt a64LSType, opc int, off int64, rn, reg, pc
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// option the toolchain's register-offset accesses use:
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// size<<30 | 0x38<<24 | V<<26 | opc<<22 | 1<<21 | Rm<<16 | 011<<13 | 10<<10 | Rn<<5 | Rt.
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func a64LSReg(size, V, opc, rm, rn, rt uint32) uint32 {
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return size<<30 | 0x38<<24 | V<<26 | opc<<22 | 1<<21 | rm<<16 | 3<<13 | 2<<10 | rn<<5 | rt
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return a64LSRegExt(size, V, opc, rm, rn, rt, 3, 0)
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}
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// a64LSRegExt encodes the extended-register-offset load/store:
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// size<<30 | 0x38<<24 | V<<26 | opc<<22 | 1<<21 | Rm<<16 | option<<13 |
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// S<<12 | 10<<10 | Rn<<5 | Rt, with S meaning "scale by the access size".
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func a64LSRegExt(size, V, opc, rm, rn, rt, option, s uint32) uint32 {
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return size<<30 | 0x38<<24 | V<<26 | opc<<22 | 1<<21 | rm<<16 | option<<13 | s<<12 | 2<<10 | rn<<5 | rt
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}
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// encodeARM64RegOffset encodes the register-offset addressing forms of the
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// MOV family: (Rn)(Rm), (Rn)(Rm*1), (Rn)(Rm<<k) and the extend spellings
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// (Rn)(Rm.UXTW<<k), (Rn)(Rm.SXTW), (Rn)(Rm.SXTX<<k). The toolchain's
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// contract, probed against `go tool asm`: the four options UXTX/LSL, UXTW,
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// SXTW and SXTX exist (the spellings UXTX, UXTB, SXTH and friends are
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// rejected), the shift amount is either zero or the access size's log2, FMOVQ
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// carries no register-offset form at all, and writeback does not combine with
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// an index.
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func encodeARM64RegOffset(mnem string, mem *ast.Operand, rn, reg int, load bool, lt a64LSType, wb string) ([]byte, error) {
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if wb != "" {
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return nil, fmt.Errorf("%s: writeback does not combine with a register offset", mnem)
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}
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if mnem == "FMOVQ" {
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return nil, fmt.Errorf("%s: illegal combination: the register offset form does not exist", mnem)
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}
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if mem.Addr.Scale > 1 {
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return nil, fmt.Errorf("%s: the register offset addressing mode takes no scale factor", mnem)
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}
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name, ext, _ := strings.Cut(mem.Addr.Index, ".")
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var option uint32
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switch strings.ToUpper(ext) {
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case "":
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option = 3 // UXTX / LSL
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case "UXTW":
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option = 2
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case "SXTW":
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option = 6
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case "SXTX":
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option = 7
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default:
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return nil, fmt.Errorf("%s: invalid shift for the register offset addressing mode: %s", mnem, ext)
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}
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rm := arm64RegNum(name)
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if rm < 0 {
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return nil, fmt.Errorf("%s: invalid index register %q", mnem, name)
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}
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amount := 0
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shift := strings.Join(strings.Fields(mem.Addr.Shift), "")
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shift = strings.TrimSuffix(shift, ")")
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if shift != "" {
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if !strings.HasPrefix(shift, "<<") {
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return nil, fmt.Errorf("%s: invalid shift for the register offset addressing mode: %s", mnem, shift)
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}
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v, err := strconv.Atoi(strings.TrimPrefix(shift, "<<"))
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if err != nil {
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return nil, fmt.Errorf("%s: invalid shift for the register offset addressing mode: %s", mnem, shift)
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}
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amount = v
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}
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log2 := bits.TrailingZeros64(uint64(a64LSScale(lt)))
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if amount != 0 && amount != log2 {
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return nil, fmt.Errorf("%s: invalid index shift amount %d", mnem, amount)
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}
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s := uint32(0)
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if amount == log2 && log2 > 0 {
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s = 1
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}
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opc := lt.opc
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if !load {
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opc = a64StoreOpc(lt)
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}
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return a64wordLE(a64LSRegExt(uint32(lt.size), uint32(lt.V), uint32(opc), uint32(rm), uint32(rn), uint32(reg), option, s)), nil
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}
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// arm64OffsetSplitReach reports whether an offset stays within the band the
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@@ -1825,3 +1825,72 @@ func TestArm64SplitFrameSpadj(t *testing.T) {
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}
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}
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}
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// TestArm64RegOffsetEncodings pins the register-offset addressing forms of
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// the MOV family against `go tool asm` words (Go 1.27, arm64): the LSL,
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// UXTW, SXTW and SXTX options, the shift amount equal to the access size's
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// log2, and the rejections the toolchain raises for the other spellings.
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func TestArm64RegOffsetEncodings(t *testing.T) {
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got := arm64Words(t,
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"\tMOVD (R2)(R6.SXTW), R4\n"+
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"\tMOVD (R3)(R6), R5\n"+
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"\tMOVD (R2)(R6<<3), R4\n"+
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"\tMOVWU (R5)(R4.UXTW), R10\n"+
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"\tMOVW (R9)(R8.SXTW<<2), R19\n"+
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"\tMOVD (R3)(R7.SXTX<<3), R8\n"+
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"\tMOVBU (R10)(R6), R15\n"+
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"\tFMOVS (R2)(R6<<2), F4\n"+
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"\tFMOVD (R2)(R6), F4\n"+
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"\tMOVD R5, (R2)(R6<<3)\n"+
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"\tMOVW R7, (R3)(R4.SXTW)\n"+
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"\tMOVD ZR, (R6)(R7.SXTX<<3)\n")
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want := []uint32{
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0xf866c844, // MOVD (R2)(R6.SXTW), R4
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0xf8666865, // MOVD (R3)(R6), R5
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0xf8667844, // MOVD (R2)(R6<<3), R4
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0xb86448aa, // MOVWU (R5)(R4.UXTW), R10
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0xb8a8d933, // MOVW (R9)(R8.SXTW<<2), R19
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0xf867f868, // MOVD (R3)(R7.SXTX<<3), R8
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0x3866694f, // MOVBU (R10)(R6), R15
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0xbc667844, // FMOVS (R2)(R6<<2), F4
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0xfc666844, // FMOVD (R2)(R6), F4
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0xf8267845, // MOVD R5, (R2)(R6<<3)
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0xb824c867, // MOVW R7, (R3)(R4.SXTW)
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0xf827f8df, // MOVD ZR, (R6)(R7.SXTX<<3)
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0xd65f03c0, // RET
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}
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if len(got) != len(want) {
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t.Fatalf("word count = %d, want %d", len(got), len(want))
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}
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for i := range want {
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if got[i] != want[i] {
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t.Errorf("word %d = %08x, want %08x", i, got[i], want[i])
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}
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}
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}
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// TestArm64RegOffsetRejections pins the spellings the toolchain refuses for
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// the register-offset addressing: the UXTX/UXTB/SXTH extend names, a shift
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// amount outside {0, log2(access)}, the scaled *k index, writeback with an
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// index, and the FMOVQ form the toolchain rejects outright.
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func TestArm64RegOffsetRejections(t *testing.T) {
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for _, src := range []string{
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"\tMOVD\t(R2)(R3.UXTX), R1\n",
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"\tMOVD\t(R2)(R3.UXTB), R1\n",
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"\tMOVD\t(R2)(R3.SXTH), R1\n",
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"\tMOVD\t(R2)(R3<<1), R1\n",
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"\tMOVD\t(R2)(R3<<2), R1\n",
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"\tMOVBU\t(R1)(R2<<1), R3\n",
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"\tMOVD\t(R2)(R3*8), R1\n",
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"\tMOVD.P\tR5, (R2)(R3)\n",
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"\tFMOVQ\t(R2)(R6), F4\n",
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} {
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f, errs := parser.Parse("test_arm64.s", "#include \"textflag.h\"\n\nTEXT ·f(SB), NOSPLIT, $0-0\n"+src+"\tRET\n")
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if len(errs) > 0 {
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continue // a parse rejection is a rejection
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}
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if _, err := AssembleFileARM64(f); err == nil {
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t.Errorf("expected rejection for %q, got nil", strings.TrimSpace(src))
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}
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}
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}
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Vendored
+71
@@ -0,0 +1,71 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Differential kernel for the arm64 register-offset addressing forms:
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// (Rn)(Rm), (Rn)(Rm<<k), (Rn)(Rm*1) and the extend spellings
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// (Rn)(Rm.UXTW<<k), (Rn)(Rm.SXTW), (Rn)(Rm.SXTX<<k). Every function is
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// byte-compared against go tool asm.
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#include "textflag.h"
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// func loads()
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TEXT ·loads(SB), NOSPLIT, $0-0
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MOVD (R2)(R6.SXTW), R4
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MOVD (R3)(R6), R5
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MOVD (R3)(R6*1), R5
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MOVD (R2)(R6), R4
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MOVWU (R19)(R20<<2), R20
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MOVD (R2)(R3<<0), R1
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MOVD (R2)(R6<<3), R4
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MOVD (R3)(R7.SXTX<<3), R8
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MOVWU (R5)(R4.UXTW), R10
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MOVBU (R3)(R9.UXTW), R8
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MOVBU (R5)(R8), R10
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MOVHU (R2)(R7.SXTW<<1), R11
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MOVHU (R1)(R2<<1), R5
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MOVBU (R9)(R3.UXTW), R6
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MOVBU (R10)(R6), R15
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MOVBU (R29)(R30<<0), R14
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MOVH (R5)(R7.SXTX<<1), R19
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MOVH (R8)(R4<<1), R10
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MOVW (R9)(R8.SXTW<<2), R19
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MOVW (R1)(R4.SXTX), R11
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MOVW (R1)(R4.SXTX), ZR
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MOVW (R2)(R5), R12
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FMOVS (R2)(R6), F4
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FMOVS (R2)(R6<<2), F4
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FMOVD (R2)(R6), F4
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FMOVD (R2)(R6<<3), F4
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RET
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// func stores()
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TEXT ·stores(SB), NOSPLIT, $0-0
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MOVD R5, (R2)(R6<<3)
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MOVD R9, (R6)(R7.SXTX<<3)
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MOVD ZR, (R6)(R7.SXTX<<3)
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MOVW R8, (R2)(R3.UXTW<<2)
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MOVW R7, (R3)(R4.SXTW)
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MOVB R4, (R2)(R6.SXTX)
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MOVB R8, (R3)(R9.UXTW)
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MOVB R10, (R5)(R8)
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MOVB R10, (R5)(R8*1)
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MOVH R11, (R2)(R7.SXTW<<1)
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MOVH R5, (R1)(R2<<1)
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MOVH R7, (R2)(R5.SXTX<<1)
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MOVH R8, (R3)(R6.UXTW)
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MOVB R4, (R2)(R6.SXTX)
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FMOVS F4, (R2)(R6)
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FMOVS F4, (R2)(R6<<2)
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FMOVD F4, (R2)(R6)
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FMOVD F4, (R2)(R6<<3)
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RET
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// func frames()
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TEXT ·frames(SB), NOSPLIT, $0-0
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MOVD (RSP)(R3), R1
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MOVD (R2)(RSP), R1
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MOVD (R2)(R2), R2
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MOVW (R2)(R3.SXTW), R1
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MOVBU (R1)(R2<<0), R3
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MOVH (R1)(R2<<1), R3
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RET
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@@ -37,6 +37,7 @@ func TestGroundTruthARM64(t *testing.T) {
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"../testdata/verify/atomics_arm64.s",
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"../testdata/verify/qmov_arm64.s",
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"../testdata/verify/splits_arm64.s",
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"../testdata/verify/regoffset_arm64.s",
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"../testdata/verify/crypto_arm64.s",
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"../testdata/verify/integer_arm64.s",
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"../testdata/verify/simd_arm64.s",
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