feat(asm): encode the arm64 register-offset addressing forms

Assisted-by: GLM 5.3 Flash

testdata/verify/regoffset_arm64.s

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+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// Differential kernel for the arm64 register-offset addressing forms:
+// (Rn)(Rm), (Rn)(Rm<<k), (Rn)(Rm*1) and the extend spellings
+// (Rn)(Rm.UXTW<<k), (Rn)(Rm.SXTW), (Rn)(Rm.SXTX<<k).  Every function is
+// byte-compared against go tool asm.
+
+#include "textflag.h"
+
+// func loads()
+TEXT ·loads(SB), NOSPLIT, $0-0
+	MOVD  (R2)(R6.SXTW), R4
+	MOVD  (R3)(R6), R5
+	MOVD  (R3)(R6*1), R5
+	MOVD  (R2)(R6), R4
+	MOVWU (R19)(R20<<2), R20
+	MOVD  (R2)(R3<<0), R1
+	MOVD  (R2)(R6<<3), R4
+	MOVD  (R3)(R7.SXTX<<3), R8
+	MOVWU (R5)(R4.UXTW), R10
+	MOVBU (R3)(R9.UXTW), R8
+	MOVBU (R5)(R8), R10
+	MOVHU (R2)(R7.SXTW<<1), R11
+	MOVHU (R1)(R2<<1), R5
+	MOVBU (R9)(R3.UXTW), R6
+	MOVBU (R10)(R6), R15
+	MOVBU (R29)(R30<<0), R14
+	MOVH  (R5)(R7.SXTX<<1), R19
+	MOVH  (R8)(R4<<1), R10
+	MOVW  (R9)(R8.SXTW<<2), R19
+	MOVW  (R1)(R4.SXTX), R11
+	MOVW  (R1)(R4.SXTX), ZR
+	MOVW  (R2)(R5), R12
+	FMOVS (R2)(R6), F4
+	FMOVS (R2)(R6<<2), F4
+	FMOVD (R2)(R6), F4
+	FMOVD (R2)(R6<<3), F4
+	RET
+
+// func stores()
+TEXT ·stores(SB), NOSPLIT, $0-0
+	MOVD  R5, (R2)(R6<<3)
+	MOVD  R9, (R6)(R7.SXTX<<3)
+	MOVD  ZR, (R6)(R7.SXTX<<3)
+	MOVW  R8, (R2)(R3.UXTW<<2)
+	MOVW  R7, (R3)(R4.SXTW)
+	MOVB  R4, (R2)(R6.SXTX)
+	MOVB  R8, (R3)(R9.UXTW)
+	MOVB  R10, (R5)(R8)
+	MOVB  R10, (R5)(R8*1)
+	MOVH  R11, (R2)(R7.SXTW<<1)
+	MOVH  R5, (R1)(R2<<1)
+	MOVH  R7, (R2)(R5.SXTX<<1)
+	MOVH  R8, (R3)(R6.UXTW)
+	MOVB  R4, (R2)(R6.SXTX)
+	FMOVS F4, (R2)(R6)
+	FMOVS F4, (R2)(R6<<2)
+	FMOVD F4, (R2)(R6)
+	FMOVD F4, (R2)(R6<<3)
+	RET
+
+// func frames()
+TEXT ·frames(SB), NOSPLIT, $0-0
+	MOVD  (RSP)(R3), R1
+	MOVD  (R2)(RSP), R1
+	MOVD  (R2)(R2), R2
+	MOVW  (R2)(R3.SXTW), R1
+	MOVBU (R1)(R2<<0), R3
+	MOVH  (R1)(R2<<1), R3
+	RET