fix(cmd/gasm): probe the riscv64 operand shapes the encoder accepts
Assisted-by: GLM 5.3 Flash
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+37
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@@ -305,22 +305,57 @@ func probeShapes(a arch.Arch) []string {
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"(X5), X6", "F0, F1, F2", "F0, F1", "p2", "X1, p2", "X0, p2",
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"(X5), X6", "F0, F1, F2", "F0, F1", "p2", "X1, p2", "X0, p2",
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"X5, X6, p2", "p2(SB)",
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"X5, X6, p2", "p2(SB)",
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// AMO atomics: destination, base, source.
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// AMO atomics: destination, base, source.
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"R5, (R4), R6", "X5, (X4), X6",
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"R5, (R4), R6", "X5, (R4), R6", "X5, (X4), X6",
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// Segment stores take the first vector register aligned
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// Segment stores take the first vector register aligned
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// to the segment count, as the toolchain requires.
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// to the segment count, as the toolchain requires.
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"(X5), X6, V0, V8", "(X5), X6, V0", "(X5), X0, V4",
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"(X5), X6, V0, V8", "(X5), X6, V0", "(X5), X0, V4",
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// The FP multiply-add family takes four registers.
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// The FP multiply-add family takes four registers.
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"F0, F1, F2, F3",
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"F0, F1, F2, F3",
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// The register banks the conversions and comparisons read:
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// FCLASS and the float-to-int moves end in an integer
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// register, the int-to-float forms open with one, and the
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// FP compares write their verdict into the integer file.
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"F0, X5", "X5, F0", "F0, F1, X5",
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// The RVV slice: register, vector-register and vtype forms.
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// The RVV slice: register, vector-register and vtype forms.
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"V1, V2, V3", "V1, X5, V2", "V1", "V1, (X5)", "(X5), V1",
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"V1, V2, V3", "V1, X5, V2", "V1", "V1, (X5)", "(X5), V1",
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"$15, V1", "$15", "V1, V2", "V1, X5",
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"$15, V1", "$15", "V1, V2", "V1, X5",
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"X5, X6, p2", "R5, R6, p2",
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"X5, X6, p2", "R5, R6, p2",
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"X5, E8, M8, TA, MA, X6", "$4, E32, M1, TA, MA, X1",
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"X5, E8, M8, TA, MA, X6", "$4, E32, M1, TA, MA, X1",
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"(X5), X6, V1, V2",
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"(X5), X6, V1, V2",
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// The vector scalar forms: the float scalar in the rs1
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// field (VFADDVF and the whole VF family, VFMVVF), the
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// integer scalar spellings (VMVVX, VMVXS, VCPOPM) and the
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// masked four-operand shapes.
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"F1, V2, V3", "V1, F2, V3", "F1, V2", "V1, F2",
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"X1, V2", "V1, X2",
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"F1, V2, V0, V3", "V1, F2, V0, V3", "V2, F1, V0, V3",
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// The indexed vector loads and stores name a vector index
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// register, the strided ones an integer stride.
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"(X5), V2, V1", "V1, V2, (X5)", "V1, X6, (X5)",
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// The CSR immediate forms the toolchain's testdata spells:
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// The CSR immediate forms the toolchain's testdata spells:
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// immediate, CSR name, destination.
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// immediate, CSR name, destination.
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"$2, TIME, X5",
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"$2, TIME, X5",
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"",
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// The vector carry and merge forms carry the mandatory V0
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// mask between the sources and the destination; the
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// carry-producing ones take the mask-free three-operand
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// shape, and CANDI's immediate form lands on a prime
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// register.
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"V1, V2, V0, V3", "X5, V2, V0, V3", "$15, V2, V0, V3",
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"$15, V2, V3", "X5, V2, V3", "$-32, X10",
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// The runtime's bookkeeping pair, the compiler's own
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// no-operand statements.
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"$1, $0", "",
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// The compressed instructions the toolchain's own testdata
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// spells: the stack-based loads and stores pin their base to
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// SP, the register-based ones live in the prime registers
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// X8-X15, and the control forms branch PC-relatively.
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"20(SP), X10", "24(SP), X10", "32(SP), F10",
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"X10, 20(SP)", "X10, 24(SP)", "F10, 32(SP)",
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"20(X10), X11", "24(X10), X11", "32(X10), F11",
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"X11, 20(X10)", "X11, 24(X10)", "F11, 32(X10)",
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"1(PC)", "X5, p2", "X10, 1(PC)",
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"$-32, X5", "$-512, SP", "$4, SP, X10", "$63, X10",
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"X9, X8", "X6, X5",
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}
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}
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case arch.LOONG64:
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case arch.LOONG64:
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return []string{
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return []string{
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