test(disasm): pin the amd64 lines the objdump listing fragments

Assisted-by: GLM 5.3 Flash

disasm/parity_test.go

@@ -18,7 +18,7 @@ import (
 // The parity fixtures carry a deterministic slice of the Go toolchain's own
 // view of the encoder corpus, one instruction per line as
 //
-//	HEXBYTES\tTOOLCHAINTEXT
+//	HEXBYTES	TOOLCHAINTEXT
 //
 // where HEXBYTES are the instruction's bytes in storage order and
 // TOOLCHAINTEXT is what `go tool objdump` prints for them (its decoder is
@@ -26,6 +26,14 @@ import (
 // data with a fixed stride: amd64enc.s (the x87, SSE/MMX, VEX, XSAVE and
 // system families), amd64enc_extra.s, amd64.s, arm64enc.s, riscv64.s and
 // loong64enc1.s.
+//
+// parity_amd64_unlisted.txt covers the amd64 lines the objdump chunk oracle
+// cannot attribute: the listing fragments at the opcodes its vendored decoder
+// refuses and desynchronises around.  Their bytes are the corpus's own
+// expected-encoding comments, which the toolchain's assembler test suite
+// machine-checks, and their text is the decoder's rendering, pinned here so a
+// decoder bump cannot move it silently; the round-trip test is the oracle
+// that keeps the text honest against the encoder.
 var parityFixtures = []struct {
 	arch arch.Arch
 	file string
@@ -33,6 +41,7 @@ var parityFixtures = []struct {
 	{arch.AMD64, "testdata/parity_amd64.txt"},
 	{arch.AMD64, "testdata/parity_amd64_extra.txt"},
 	{arch.AMD64, "testdata/parity_amd64_sys.txt"},
+	{arch.AMD64, "testdata/parity_amd64_unlisted.txt"},
 	{arch.ARM64, "testdata/parity_arm64.txt"},
 	{arch.RISCV, "testdata/parity_riscv64.txt"},
 	{arch.LOONG64, "testdata/parity_loong64.txt"},
@@ -169,6 +178,7 @@ var toolchainRenderNames = map[string]bool{
 	"LSS": true, "LGS": true, "LFS": true,
 	"WRGSBASE": true, "RDFSBASE": true, "STR": true, "SLDT": true,
 	"RDRAND": true, "POPF": true, "LRET": true,
+	"WRFSBASE": true, "FCOM": true,
 	"FDIV": true, "FADD": true, "FRINTS": true, "FRINTM": true,
 	"CMPPD": true, "STOSB": true, "PUSHL": true,
 	"MOVSD_XMM": true, "CMPSD_XMM": true,
@@ -223,6 +233,32 @@ var encoderDivergences = map[string]bool{
 	"FCLASSS F0, X5":               true,
 	"FCLASSD F0, X5":               true,
 	"AUIPC $524287, X10":           true,
+	// From the unlisted amd64 fixture: the 8-bit accumulator and register
+	// immediate short forms render with a 32-bit suffix ("ADDL $0x7, AL"),
+	// which re-assembles as the 32-bit form; MOVD re-encodes as the 64-bit
+	// MOVQ form; POPW drops the operand-size prefix.  Findings for asm,
+	// reported and not fixed here.
+	"ADDL $0x7, AL": true,
+	"MOVL $0x7, DL": true,
+	"SBBL $0x7, AL": true,
+	"POPW FS":       true,
+	"POPW GS":       true,
+	"MOVD DX, M2":   true,
+	"MOVD R11, M2":  true,
+	"MOVD DX, M3":   true,
+	"MOVD R11, M3":  true,
+	"MOVD M2, DX":   true,
+	"MOVD M3, DX":   true,
+	"MOVD M2, R11":  true,
+	"MOVD M3, R11":  true,
+	"MOVD X2, DX":   true,
+	"MOVD X11, DX":  true,
+	"MOVD X2, R11":  true,
+	"MOVD X11, R11": true,
+	"MOVD DX, X2":   true,
+	"MOVD R11, X2":  true,
+	"MOVD DX, X11":  true,
+	"MOVD R11, X11": true,
 }
 
 // TestDisassemblyRoundTrip is the cheap invariant over the same slice: