feat(riscv): add prologue, epilogue and frame pseudo-register support

Assisted-by: Kimi K3
This commit is contained in:
2026-08-02 00:18:00 +02:00
parent f860bf8ce6
commit a2acc9b5a3
5 changed files with 253 additions and 53 deletions
+9 -3
View File
@@ -374,8 +374,9 @@ requires -p, the package path, and the installed Go toolchain).
return 2
}
path := fs.Arg(0)
if arch.FromFilename(path) != arch.AMD64 {
fmt.Fprintln(os.Stderr, "gasm asm: only amd64 is supported in this Phase 2 increment")
targetArch := arch.FromFilename(path)
if targetArch != arch.AMD64 && targetArch != arch.RISCV {
fmt.Fprintln(os.Stderr, "gasm asm: only amd64 and riscv64 are supported")
return 1
}
src, err := readSource(path)
@@ -391,7 +392,12 @@ requires -p, the package path, and the installed Go toolchain).
return 1
}
img, err := asm.AssembleFile(f)
var img *asm.Image
if targetArch == arch.RISCV {
img, err = asm.AssembleFileRISCV(f)
} else {
img, err = asm.AssembleFile(f)
}
if err != nil {
fmt.Fprintf(os.Stderr, "%s: %v\n", path, err)
return 1