feat(asm): add RISC-V encoder with RV64I/RV64M instruction formats
Assisted-by: Kimi K3
This commit is contained in:
@@ -0,0 +1,237 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import (
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"fmt"
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"sourcedock.dev/petrbalvin/gasm-devkit/ast"
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)
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// assembleRISCV assembles a RISC-V TEXT function body into machine code.
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// It handles the core RV64I/RV64M instruction set with fixed 32-bit encoding.
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func assembleRISCV(t *ast.Text) ([]byte, map[string]int, error) {
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// First pass: compute label offsets (all RISC-V instructions are 4 bytes).
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offsets := map[string]int{}
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var instrs []*ast.Instr
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pos := 0
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for _, stmt := range t.Body {
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switch s := stmt.(type) {
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case *ast.Label:
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offsets[s.Name.Text] = pos
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case *ast.Instr:
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instrs = append(instrs, s)
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pos += 4 // all RISC-V instructions are 4 bytes
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}
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}
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// Second pass: encode instructions.
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out := make([]byte, 0, pos)
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for _, instr := range instrs {
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code, err := encodeRISCVInstr(instr, pos, offsets)
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if err != nil {
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return nil, nil, fmt.Errorf("%s: %w", instr.Mnemonic.Text, err)
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}
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out = append(out, code...)
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pos -= 4 // track remaining
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}
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return out, offsets, nil
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}
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// encodeRISCVInstr encodes a single RISC-V instruction.
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func encodeRISCVInstr(instr *ast.Instr, pc int, offsets map[string]int) ([]byte, error) {
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mnem := instr.Mnemonic.Text
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enc, ok := riscvInstrTable[mnem]
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if !ok {
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return nil, fmt.Errorf("unsupported RISC-V instruction %q", mnem)
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}
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ops := instr.Operands
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var word uint32
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switch {
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// R-type: rd, rs1, rs2 (3 register operands).
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case len(ops) == 3 && isRTypeInstr(mnem):
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rd := regFromOperand(ops[0])
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rs1 := regFromOperand(ops[1])
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rs2 := regFromOperand(ops[2])
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if rd < 0 || rs1 < 0 || rs2 < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvRType(enc, rd, rs1, rs2)
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// I-type with immediate: rd, rs1, imm.
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case len(ops) == 3 && isITypeInstr(mnem):
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rd := regFromOperand(ops[0])
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rs1 := regFromOperand(ops[1])
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imm := immFromOperand(ops[2])
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if rd < 0 || rs1 < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvIType(enc, rd, rs1, imm)
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// Loads: rd, offset(rs1) — parsed as rd, (rs1)+offset.
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case len(ops) == 2 && isLoadInstr(mnem):
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rd := regFromOperand(ops[0])
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rs1, imm := memFromOperand(ops[1])
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if rd < 0 || rs1 < 0 {
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return nil, fmt.Errorf("invalid operand in %s", mnem)
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}
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word = riscvIType(enc, rd, rs1, imm)
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// Stores: rs2, offset(rs1).
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case len(ops) == 2 && isStoreInstr(mnem):
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rs2 := regFromOperand(ops[0])
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rs1, imm := memFromOperand(ops[1])
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if rs2 < 0 || rs1 < 0 {
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return nil, fmt.Errorf("invalid operand in %s", mnem)
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}
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word = riscvSType(enc, rs1, rs2, imm)
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// Branches: rs1, rs2, label.
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case len(ops) == 3 && isBranchInstr(mnem):
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rs1 := regFromOperand(ops[0])
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rs2 := regFromOperand(ops[1])
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target := labelFromOperand(ops[2])
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targetOff, ok := offsets[target]
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if !ok {
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return nil, fmt.Errorf("undefined label %q", target)
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}
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rs1Off := 0 // placeholder
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_ = rs1Off
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offset := int32(targetOff - pc)
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if rs1 < 0 || rs2 < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvBType(enc, rs1, rs2, offset)
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// U-type: rd, imm.
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case len(ops) == 2 && isUTypeInstr(mnem):
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rd := regFromOperand(ops[0])
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imm := immFromOperand(ops[1])
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if rd < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvUType(enc, rd, imm)
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// JAL: rd, label (or just label for JMP).
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case mnem == "JAL" || mnem == "JMP":
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rd := 0 // JMP uses rd=0 (X0)
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if len(ops) >= 1 && mnem == "JAL" {
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rd = regFromOperand(ops[0])
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}
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var target string
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if len(ops) >= 2 {
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target = labelFromOperand(ops[len(ops)-1])
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} else if len(ops) == 1 && mnem == "JMP" {
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target = labelFromOperand(ops[0])
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}
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targetOff, ok := offsets[target]
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if !ok {
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return nil, fmt.Errorf("undefined label %q", target)
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}
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offset := int32(targetOff - pc)
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word = riscvJType(rd, offset)
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// RET: JALR X0, 0(X1).
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case mnem == "RET":
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word = riscvIType(riscvEnc{0x67, 0x0, 0x00}, 0, 1, 0)
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// CALL: AUIPC + JALR sequence (simplified: just encode as NOP placeholder).
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case mnem == "CALL":
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// CALL is a pseudo-instruction that expands to AUIPC + JALR.
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// For now, encode as a NOP (ADDI X0, X0, 0).
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word = riscvIType(riscvEnc{0x13, 0x0, 0x00}, 0, 0, 0)
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default:
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return nil, fmt.Errorf("cannot encode %s with %d operands", mnem, len(ops))
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}
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// Emit as little-endian 32-bit word.
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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}
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// Instruction type classifiers.
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func isRTypeInstr(m string) bool {
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switch m {
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case "ADD", "SUB", "SLL", "SLT", "SLTU", "XOR", "SRL", "SRA", "OR", "AND",
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"ADDW", "SUBW", "SLLW", "SRLW", "SRAW",
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"MUL", "MULH", "MULHSU", "MULHU", "DIV", "DIVU", "REM", "REMU",
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"MULW", "DIVW", "DIVUW", "REMW", "REMUW":
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return true
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}
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return false
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}
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func isITypeInstr(m string) bool {
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switch m {
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case "ADDI", "ADDIW", "SLTI", "SLTIU", "XORI", "ORI", "ANDI", "JALR":
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return true
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}
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return false
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}
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func isLoadInstr(m string) bool {
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switch m {
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case "LB", "LH", "LW", "LD", "LBU", "LHU", "LWU":
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return true
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}
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return false
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}
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func isStoreInstr(m string) bool {
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switch m {
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case "SB", "SH", "SW", "SD":
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return true
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}
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return false
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}
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func isBranchInstr(m string) bool {
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switch m {
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case "BEQ", "BNE", "BLT", "BGE", "BLTU", "BGEU":
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return true
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}
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return false
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}
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func isUTypeInstr(m string) bool {
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return m == "LUI" || m == "AUIPC"
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}
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// Operand helpers.
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func regFromOperand(op *ast.Operand) int {
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// Register is in Addr.Base (from (base) syntax) or Addr.Sym.Name (bare ident).
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if op.Addr.Base != "" {
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return riscvRegNum(op.Addr.Base)
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}
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if op.Addr.Sym != nil && op.Addr.Sym.Name != "" {
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return riscvRegNum(op.Addr.Sym.Name)
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}
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return -1
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}
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func immFromOperand(op *ast.Operand) int32 {
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if op.Imm.HasVal {
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v := op.Imm.Val
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if op.Imm.Neg {
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v = -v
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}
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return int32(v)
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}
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return 0
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}
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func memFromOperand(op *ast.Operand) (rs1 int, imm int32) {
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rs1 = riscvRegNum(op.Addr.Base)
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imm = int32(op.Addr.Offset)
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return
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}
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func labelFromOperand(op *ast.Operand) string {
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if op.Addr.Sym != nil {
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return op.Addr.Sym.Name
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}
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return op.Raw
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}
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@@ -0,0 +1,271 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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// RISC-V register encoding: maps register names to their 5-bit numbers.
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// The Go assembler uses the standard RISC-V ABI naming.
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// riscvRegNum returns the 5-bit register number for a RISC-V register name.
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// Returns -1 if the register is not recognized.
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func riscvRegNum(name string) int {
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switch name {
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// Numbered integer registers.
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case "X0", "ZERO":
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return 0
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case "X1", "RA":
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return 1
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case "X2", "SP":
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return 2
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case "X3", "GP":
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return 3
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case "X4", "TP":
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return 4
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case "X5", "T0", "LR":
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return 5
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case "X6", "T1", "TMP":
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return 6
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case "X7", "T2":
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return 7
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case "X8", "S0", "FP":
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return 8
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case "X9", "S1":
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return 9
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case "X10", "A0":
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return 10
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case "X11", "A1":
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return 11
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case "X12", "A2":
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return 12
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case "X13", "A3":
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return 13
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case "X14", "A4":
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return 14
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case "X15", "A5":
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return 15
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case "X16", "A6":
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return 16
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case "X17", "A7":
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return 17
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case "X18", "S2":
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return 18
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case "X19", "S3":
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return 19
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case "X20", "S4":
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return 20
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case "X21", "S5":
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return 21
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case "X22", "S6":
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return 22
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case "X23", "S7":
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return 23
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case "X24", "S8":
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return 24
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case "X25", "S9":
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return 25
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case "X26", "S10":
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return 26
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case "X27", "S11":
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return 27
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case "X28", "T3":
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return 28
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case "X29", "T4":
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return 29
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case "X30", "T5":
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return 30
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case "X31", "T6":
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return 31
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// Floating-point registers (F0-F31).
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case "F0", "FT0":
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return 0
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case "F1", "FT1":
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return 1
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case "F2", "FT2":
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return 2
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case "F3", "FT3":
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return 3
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case "F4", "FT4":
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return 4
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case "F5", "FT5":
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return 5
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case "F6", "FT6":
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return 6
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case "F7", "FT7":
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return 7
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case "F8", "FS0":
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return 8
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case "F9", "FS1":
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return 9
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case "F10", "FA0":
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return 10
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case "F11", "FA1":
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return 11
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case "F12", "FA2":
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return 12
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case "F13", "FA3":
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return 13
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case "F14", "FA4":
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return 14
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case "F15", "FA5":
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return 15
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case "F16", "FA6":
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return 16
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case "F17", "FA7":
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return 17
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case "F18", "FS2":
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return 18
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case "F19", "FS3":
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return 19
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case "F20", "FS4":
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return 20
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case "F21", "FS5":
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return 21
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case "F22", "FS6":
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return 22
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case "F23", "FS7":
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return 23
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case "F24", "FS8":
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return 24
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case "F25", "FS9":
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return 25
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case "F26", "FS10":
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return 26
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case "F27", "FS11":
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return 27
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case "F28", "FT8":
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return 28
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case "F29", "FT9":
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return 29
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case "F30", "FT10":
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return 30
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case "F31", "FT11":
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return 31
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default:
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return -1
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}
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}
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// RISC-V instruction encoding parameters.
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type riscvEnc struct {
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opcode uint32 // bits [6:0]
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funct3 uint32 // bits [14:12]
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funct7 uint32 // bits [31:25]
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}
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// riscvInstrTable maps RISC-V mnemonics to their encoding.
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var riscvInstrTable = map[string]riscvEnc{
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// RV64I — R-type arithmetic/logic.
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"ADD": {0x33, 0x0, 0x00},
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"SUB": {0x33, 0x0, 0x20},
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"SLL": {0x33, 0x1, 0x00},
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"SLT": {0x33, 0x2, 0x00},
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"SLTU": {0x33, 0x3, 0x00},
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"XOR": {0x33, 0x4, 0x00},
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"SRL": {0x33, 0x5, 0x00},
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"SRA": {0x33, 0x5, 0x20},
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"OR": {0x33, 0x6, 0x00},
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"AND": {0x33, 0x7, 0x00},
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// RV64I — 32-bit variants (W suffix).
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"ADDW": {0x3B, 0x0, 0x00},
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"SUBW": {0x3B, 0x0, 0x20},
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"SLLW": {0x3B, 0x1, 0x00},
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"SRLW": {0x3B, 0x5, 0x00},
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"SRAW": {0x3B, 0x5, 0x20},
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// RV64M — multiply/divide.
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"MUL": {0x33, 0x0, 0x01},
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"MULH": {0x33, 0x1, 0x01},
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"MULHSU": {0x33, 0x2, 0x01},
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"MULHU": {0x33, 0x3, 0x01},
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"DIV": {0x33, 0x4, 0x01},
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"DIVU": {0x33, 0x5, 0x01},
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"REM": {0x33, 0x6, 0x01},
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"REMU": {0x33, 0x7, 0x01},
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// RV64M — 32-bit variants.
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"MULW": {0x3B, 0x0, 0x01},
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"DIVW": {0x3B, 0x4, 0x01},
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"DIVUW": {0x3B, 0x5, 0x01},
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"REMW": {0x3B, 0x6, 0x01},
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"REMUW": {0x3B, 0x7, 0x01},
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// RV64I — I-type arithmetic.
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"ADDI": {0x13, 0x0, 0x00},
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"ADDIW": {0x1B, 0x0, 0x00},
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"SLTI": {0x13, 0x2, 0x00},
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"SLTIU": {0x13, 0x3, 0x00},
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"XORI": {0x13, 0x4, 0x00},
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"ORI": {0x13, 0x6, 0x00},
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"ANDI": {0x13, 0x7, 0x00},
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// Loads (I-type).
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"LB": {0x03, 0x0, 0x00},
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"LH": {0x03, 0x1, 0x00},
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"LW": {0x03, 0x2, 0x00},
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"LD": {0x03, 0x3, 0x00},
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"LBU": {0x03, 0x4, 0x00},
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"LHU": {0x03, 0x5, 0x00},
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"LWU": {0x03, 0x6, 0x00},
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// Stores (S-type).
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"SB": {0x23, 0x0, 0x00},
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"SH": {0x23, 0x1, 0x00},
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"SW": {0x23, 0x2, 0x00},
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"SD": {0x23, 0x3, 0x00},
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// Branches (B-type).
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"BEQ": {0x63, 0x0, 0x00},
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"BNE": {0x63, 0x1, 0x00},
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"BLT": {0x63, 0x4, 0x00},
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"BGE": {0x63, 0x5, 0x00},
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"BLTU": {0x63, 0x6, 0x00},
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"BGEU": {0x63, 0x7, 0x00},
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// U-type.
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"LUI": {0x37, 0x0, 0x00},
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"AUIPC": {0x17, 0x0, 0x00},
|
||||
// System.
|
||||
"ECALL": {0x73, 0x0, 0x00},
|
||||
"EBREAK": {0x73, 0x0, 0x00},
|
||||
"FENCE": {0x0F, 0x0, 0x00},
|
||||
}
|
||||
|
||||
// riscvRType encodes an R-type instruction: funct7 | rs2 | rs1 | funct3 | rd | opcode.
|
||||
func riscvRType(enc riscvEnc, rd, rs1, rs2 int) uint32 {
|
||||
return (enc.funct7 << 25) | (uint32(rs2) << 20) | (uint32(rs1) << 15) |
|
||||
(enc.funct3 << 12) | (uint32(rd) << 7) | enc.opcode
|
||||
}
|
||||
|
||||
// riscvIType encodes an I-type instruction: imm[11:0] | rs1 | funct3 | rd | opcode.
|
||||
func riscvIType(enc riscvEnc, rd, rs1 int, imm int32) uint32 {
|
||||
return (uint32(imm&0xFFF) << 20) | (uint32(rs1) << 15) |
|
||||
(enc.funct3 << 12) | (uint32(rd) << 7) | enc.opcode
|
||||
}
|
||||
|
||||
// riscvSType encodes an S-type instruction: imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode.
|
||||
func riscvSType(enc riscvEnc, rs1, rs2 int, imm int32) uint32 {
|
||||
immU := uint32(imm) & 0xFFF
|
||||
return ((immU >> 5) << 25) | (uint32(rs2) << 20) | (uint32(rs1) << 15) |
|
||||
(enc.funct3 << 12) | ((immU & 0x1F) << 7) | enc.opcode
|
||||
}
|
||||
|
||||
// riscvBType encodes a B-type instruction (branches).
|
||||
func riscvBType(enc riscvEnc, rs1, rs2 int, offset int32) uint32 {
|
||||
imm := uint32(offset) & 0x1FFE // bits [12:1], bit 0 is always 0
|
||||
return (((imm >> 12) & 1) << 31) | // imm[12]
|
||||
(((imm >> 5) & 0x3F) << 25) | // imm[10:5]
|
||||
(uint32(rs2) << 20) | (uint32(rs1) << 15) |
|
||||
(enc.funct3 << 12) |
|
||||
(((imm >> 1) & 0xF) << 8) | // imm[4:1]
|
||||
(((imm >> 11) & 1) << 7) | // imm[11]
|
||||
enc.opcode
|
||||
}
|
||||
|
||||
// riscvUType encodes a U-type instruction: imm[31:12] | rd | opcode.
|
||||
func riscvUType(enc riscvEnc, rd int, imm int32) uint32 {
|
||||
return (uint32(imm) & 0xFFFFF000) | (uint32(rd) << 7) | enc.opcode
|
||||
}
|
||||
|
||||
// riscvJType encodes a J-type instruction (JAL).
|
||||
func riscvJType(rd int, offset int32) uint32 {
|
||||
imm := uint32(offset) & 0x1FFFFE // bits [20:1]
|
||||
return (((imm >> 20) & 1) << 31) | // imm[20]
|
||||
(((imm >> 1) & 0x3FF) << 21) | // imm[10:1]
|
||||
(((imm >> 11) & 1) << 20) | // imm[11]
|
||||
(((imm >> 12) & 0xFF) << 12) | // imm[19:12]
|
||||
(uint32(rd) << 7) |
|
||||
0x6F // JAL opcode
|
||||
}
|
||||
Reference in New Issue
Block a user