fix(asm): match the toolchain's bytes across the corpus sweep

A line-for-line byte comparison of the whole amd64enc.s corpus against
go tool asm surfaced divergences the pass-only accounting never showed:
PEXTRW's GPR form swapped its fields, PUSHW took an imm32 where the
toolchain bounds the immediate to 16 bits, the double shift wrote the
unmasked register number into the reg field, VCOMISS carried a 0x66
prefix, RORX dropped the destination's R bit, and the variable bit
shifts used the manual's per-width opcodes where the toolchain
consolidates each row on one opcode with the W bit.  The VEX forms the
toolchain prefers for plain vector registers (the SSE2/SSSE3/SSE4.1
AVX twins, the compare-with-predicate family, VMOVUPS, VSHUFPS, the
variable shifts) now encode under VEX, with EVEX left to the ZMM,
opmask and index-16+ spellings, and the mnemonics whose rows never
offer the 2-byte prefix force it.  Every line is pinned through the new
corpus parity test (793 lines); the whole corpus file now assembles to
the toolchain's bytes at every commented line (10022 of 10022).

Assisted-by: GLM 5.3 Flash

asm/vex_test.go

@@ -79,6 +79,7 @@ var x86asmUnrecognised = map[string]bool{
 	// The register-only half move the decoder's AVX tables lack; its
 	// bytes are pinned against go tool asm through the corpus test.
 	"VMOVHLPS": true,
+	"VMOVLHPS": true,
 }
 
 // TestVexNDS3 encodes `mnem Y0, Y1, Y2` for every three-operand NDS