feat(asm): encode the remaining amd64 VEX families
The SSE3 horizontal and add-subtract pairs, the SSSE3 sign and horizontal integers, the masked moves in both directions, the reciprocity and test pairs, the AVX imm8 tail (blends, dot products, inserts, rounds, MPSADBW, the string compares), the four-operand variable blends with their /is4 mask byte, the scalar three-operand moves, the MXCSR accessors, the VPERMIL register controls and the variable word shifts, plus the BMI2 count forms over memory. Every encoding is pinned byte for byte against go tool asm through every corpus line the toolchain's own amd64enc.s carries for the families (852 lines); the /is4 byte carries the mask register number in its high nibble, the layout the toolchain emits. Assisted-by: GLM 5.3 Flash
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import "testing"
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// amd64VexCorpus holds every line the Go toolchain's own
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// amd64enc.s carries for the VEX (AVX/AVX2) families and the general-register count forms, with the bytes go
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// tool asm emits for each: the differential ground truth the layer is
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// proven against, line for line.
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var amd64VexCorpus = []struct {
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line string
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want string
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}{
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{"BEXTRL R9, (BX), DX", "c4 e2 30 f7 13"},
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{"BEXTRL R9, (BX), R11", "c4 62 30 f7 1b"},
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{"BEXTRL R9, (R11), DX", "c4 c2 30 f7 13"},
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{"BEXTRL R9, (R11), R11", "c4 42 30 f7 1b"},
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{"BEXTRL R9, DX, DX", "c4 e2 30 f7 d2"},
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{"BEXTRL R9, DX, R11", "c4 62 30 f7 da"},
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{"BEXTRL R9, R11, DX", "c4 c2 30 f7 d3"},
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{"BEXTRL R9, R11, R11", "c4 42 30 f7 db"},
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{"BEXTRQ R14, (BX), DX", "c4 e2 88 f7 13"},
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{"BEXTRQ R14, (BX), R11", "c4 62 88 f7 1b"},
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{"BEXTRQ R14, (R11), DX", "c4 c2 88 f7 13"},
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{"BEXTRQ R14, (R11), R11", "c4 42 88 f7 1b"},
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{"BEXTRQ R14, DX, DX", "c4 e2 88 f7 d2"},
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{"BEXTRQ R14, DX, R11", "c4 62 88 f7 da"},
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{"BEXTRQ R14, R11, DX", "c4 c2 88 f7 d3"},
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{"BEXTRQ R14, R11, R11", "c4 42 88 f7 db"},
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{"BZHIL R9, (BX), DX", "c4 e2 30 f5 13"},
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{"BZHIL R9, (BX), R11", "c4 62 30 f5 1b"},
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{"BZHIL R9, (R11), DX", "c4 c2 30 f5 13"},
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{"BZHIL R9, (R11), R11", "c4 42 30 f5 1b"},
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{"BZHIL R9, DX, DX", "c4 e2 30 f5 d2"},
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{"BZHIL R9, DX, R11", "c4 62 30 f5 da"},
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{"BZHIL R9, R11, DX", "c4 c2 30 f5 d3"},
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{"BZHIL R9, R11, R11", "c4 42 30 f5 db"},
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{"BZHIQ R14, (BX), DX", "c4 e2 88 f5 13"},
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{"BZHIQ R14, (BX), R11", "c4 62 88 f5 1b"},
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{"BZHIQ R14, (R11), DX", "c4 c2 88 f5 13"},
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{"BZHIQ R14, (R11), R11", "c4 42 88 f5 1b"},
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{"BZHIQ R14, DX, DX", "c4 e2 88 f5 d2"},
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{"BZHIQ R14, DX, R11", "c4 62 88 f5 da"},
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{"BZHIQ R14, R11, DX", "c4 c2 88 f5 d3"},
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{"BZHIQ R14, R11, R11", "c4 42 88 f5 db"},
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{"SARXL R9, (BX), DX", "c4 e2 32 f7 13"},
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{"SARXL R9, (BX), R11", "c4 62 32 f7 1b"},
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{"SARXL R9, (R11), DX", "c4 c2 32 f7 13"},
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{"SARXL R9, (R11), R11", "c4 42 32 f7 1b"},
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{"SARXL R9, DX, DX", "c4 e2 32 f7 d2"},
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{"SARXL R9, DX, R11", "c4 62 32 f7 da"},
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{"SARXL R9, R11, DX", "c4 c2 32 f7 d3"},
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{"SARXL R9, R11, R11", "c4 42 32 f7 db"},
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{"SARXQ R14, (BX), DX", "c4 e2 8a f7 13"},
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{"SARXQ R14, (BX), R11", "c4 62 8a f7 1b"},
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{"SARXQ R14, (R11), DX", "c4 c2 8a f7 13"},
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{"SARXQ R14, (R11), R11", "c4 42 8a f7 1b"},
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{"SARXQ R14, DX, DX", "c4 e2 8a f7 d2"},
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{"SARXQ R14, DX, R11", "c4 62 8a f7 da"},
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{"SARXQ R14, R11, DX", "c4 c2 8a f7 d3"},
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{"SARXQ R14, R11, R11", "c4 42 8a f7 db"},
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{"SHLXL R9, (BX), DX", "c4 e2 31 f7 13"},
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{"SHLXL R9, (BX), R11", "c4 62 31 f7 1b"},
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{"SHLXL R9, (R11), DX", "c4 c2 31 f7 13"},
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{"SHLXL R9, (R11), R11", "c4 42 31 f7 1b"},
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{"SHLXL R9, DX, DX", "c4 e2 31 f7 d2"},
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{"SHLXL R9, DX, R11", "c4 62 31 f7 da"},
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{"SHLXL R9, R11, DX", "c4 c2 31 f7 d3"},
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{"SHLXL R9, R11, R11", "c4 42 31 f7 db"},
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{"SHLXQ R14, (BX), DX", "c4 e2 89 f7 13"},
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{"SHLXQ R14, (BX), R11", "c4 62 89 f7 1b"},
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{"SHLXQ R14, (R11), DX", "c4 c2 89 f7 13"},
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{"SHLXQ R14, (R11), R11", "c4 42 89 f7 1b"},
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{"SHLXQ R14, DX, DX", "c4 e2 89 f7 d2"},
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{"SHLXQ R14, DX, R11", "c4 62 89 f7 da"},
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{"SHLXQ R14, R11, DX", "c4 c2 89 f7 d3"},
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{"SHLXQ R14, R11, R11", "c4 42 89 f7 db"},
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{"SHRXL R9, (BX), DX", "c4 e2 33 f7 13"},
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{"SHRXL R9, (BX), R11", "c4 62 33 f7 1b"},
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{"SHRXL R9, (R11), DX", "c4 c2 33 f7 13"},
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{"SHRXL R9, (R11), R11", "c4 42 33 f7 1b"},
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{"SHRXL R9, DX, DX", "c4 e2 33 f7 d2"},
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{"SHRXL R9, DX, R11", "c4 62 33 f7 da"},
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{"SHRXL R9, R11, DX", "c4 c2 33 f7 d3"},
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{"SHRXL R9, R11, R11", "c4 42 33 f7 db"},
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{"SHRXQ R14, (BX), DX", "c4 e2 8b f7 13"},
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{"SHRXQ R14, (BX), R11", "c4 62 8b f7 1b"},
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{"SHRXQ R14, (R11), DX", "c4 c2 8b f7 13"},
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{"SHRXQ R14, (R11), R11", "c4 42 8b f7 1b"},
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{"SHRXQ R14, DX, DX", "c4 e2 8b f7 d2"},
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{"SHRXQ R14, DX, R11", "c4 62 8b f7 da"},
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{"SHRXQ R14, R11, DX", "c4 c2 8b f7 d3"},
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{"SHRXQ R14, R11, R11", "c4 42 8b f7 db"},
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{"VADDSUBPD (BX), X9, X11", "c5 31 d0 1b"},
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{"VADDSUBPD (BX), X9, X2", "c5 b1 d0 13"},
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{"VADDSUBPD (BX), Y15, Y11", "c5 05 d0 1b"},
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{"VADDSUBPD (BX), Y15, Y2", "c5 85 d0 13"},
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{"VADDSUBPD (R11), X9, X11", "c4 41 31 d0 1b"},
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{"VADDSUBPD (R11), X9, X2", "c4 c1 31 d0 13"},
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{"VADDSUBPD (R11), Y15, Y11", "c4 41 05 d0 1b"},
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{"VADDSUBPD (R11), Y15, Y2", "c4 c1 05 d0 13"},
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{"VADDSUBPD X11, X9, X11", "c4 41 31 d0 db"},
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{"VADDSUBPD X11, X9, X2", "c4 c1 31 d0 d3"},
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{"VADDSUBPD X2, X9, X11", "c5 31 d0 da"},
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{"VADDSUBPD X2, X9, X2", "c5 b1 d0 d2"},
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{"VADDSUBPD Y11, Y15, Y11", "c4 41 05 d0 db"},
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{"VADDSUBPD Y11, Y15, Y2", "c4 c1 05 d0 d3"},
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{"VADDSUBPD Y2, Y15, Y11", "c5 05 d0 da"},
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{"VADDSUBPD Y2, Y15, Y2", "c5 85 d0 d2"},
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{"VADDSUBPS (BX), X9, X11", "c5 33 d0 1b"},
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{"VADDSUBPS (BX), X9, X2", "c5 b3 d0 13"},
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{"VADDSUBPS (BX), Y15, Y11", "c5 07 d0 1b"},
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{"VADDSUBPS (BX), Y15, Y2", "c5 87 d0 13"},
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{"VADDSUBPS (R11), X9, X11", "c4 41 33 d0 1b"},
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{"VADDSUBPS (R11), X9, X2", "c4 c1 33 d0 13"},
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{"VADDSUBPS (R11), Y15, Y11", "c4 41 07 d0 1b"},
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{"VADDSUBPS (R11), Y15, Y2", "c4 c1 07 d0 13"},
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{"VADDSUBPS X11, X9, X11", "c4 41 33 d0 db"},
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{"VADDSUBPS X11, X9, X2", "c4 c1 33 d0 d3"},
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{"VADDSUBPS X2, X9, X11", "c5 33 d0 da"},
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{"VADDSUBPS X2, X9, X2", "c5 b3 d0 d2"},
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{"VADDSUBPS Y11, Y15, Y11", "c4 41 07 d0 db"},
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{"VADDSUBPS Y11, Y15, Y2", "c4 c1 07 d0 d3"},
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{"VADDSUBPS Y2, Y15, Y11", "c5 07 d0 da"},
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{"VADDSUBPS Y2, Y15, Y2", "c5 87 d0 d2"},
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{"VAESIMC (BX), X11", "c4 62 79 db 1b"},
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{"VAESIMC (BX), X2", "c4 e2 79 db 13"},
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{"VAESIMC (R11), X11", "c4 42 79 db 1b"},
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{"VAESIMC (R11), X2", "c4 c2 79 db 13"},
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{"VAESIMC X11, X11", "c4 42 79 db db"},
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{"VAESIMC X11, X2", "c4 c2 79 db d3"},
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{"VAESIMC X2, X11", "c4 62 79 db da"},
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{"VAESIMC X2, X2", "c4 e2 79 db d2"},
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{"VBLENDPD $7, (BX), X9, X11", "c4 63 31 0d 1b 07"},
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{"VBLENDPD $7, (BX), X9, X2", "c4 e3 31 0d 13 07"},
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{"VBLENDPD $7, (BX), Y15, Y11", "c4 63 05 0d 1b 07"},
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{"VBLENDPD $7, (BX), Y15, Y2", "c4 e3 05 0d 13 07"},
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{"VBLENDPD $7, (R11), X9, X11", "c4 43 31 0d 1b 07"},
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{"VBLENDPD $7, (R11), X9, X2", "c4 c3 31 0d 13 07"},
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{"VBLENDPD $7, (R11), Y15, Y11", "c4 43 05 0d 1b 07"},
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{"VBLENDPD $7, (R11), Y15, Y2", "c4 c3 05 0d 13 07"},
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{"VBLENDPD $7, X11, X9, X11", "c4 43 31 0d db 07"},
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{"VBLENDPD $7, X11, X9, X2", "c4 c3 31 0d d3 07"},
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{"VBLENDPD $7, X2, X9, X11", "c4 63 31 0d da 07"},
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{"VBLENDPD $7, X2, X9, X2", "c4 e3 31 0d d2 07"},
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{"VBLENDPD $7, Y11, Y15, Y11", "c4 43 05 0d db 07"},
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{"VBLENDPD $7, Y11, Y15, Y2", "c4 c3 05 0d d3 07"},
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{"VBLENDPD $7, Y2, Y15, Y11", "c4 63 05 0d da 07"},
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{"VBLENDPD $7, Y2, Y15, Y2", "c4 e3 05 0d d2 07"},
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{"VBLENDPS $7, (BX), X9, X11", "c4 63 31 0c 1b 07"},
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{"VBLENDPS $7, (BX), X9, X2", "c4 e3 31 0c 13 07"},
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{"VBLENDPS $7, (BX), Y15, Y11", "c4 63 05 0c 1b 07"},
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{"VBLENDPS $7, (BX), Y15, Y2", "c4 e3 05 0c 13 07"},
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{"VBLENDPS $7, (R11), X9, X11", "c4 43 31 0c 1b 07"},
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{"VBLENDPS $7, (R11), X9, X2", "c4 c3 31 0c 13 07"},
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{"VBLENDPS $7, (R11), Y15, Y11", "c4 43 05 0c 1b 07"},
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{"VBLENDPS $7, (R11), Y15, Y2", "c4 c3 05 0c 13 07"},
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{"VBLENDPS $7, X11, X9, X11", "c4 43 31 0c db 07"},
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{"VBLENDPS $7, X11, X9, X2", "c4 c3 31 0c d3 07"},
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{"VBLENDPS $7, X2, X9, X11", "c4 63 31 0c da 07"},
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{"VBLENDPS $7, X2, X9, X2", "c4 e3 31 0c d2 07"},
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{"VBLENDPS $7, Y11, Y15, Y11", "c4 43 05 0c db 07"},
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{"VBLENDPS $7, Y11, Y15, Y2", "c4 c3 05 0c d3 07"},
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{"VBLENDPS $7, Y2, Y15, Y11", "c4 63 05 0c da 07"},
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{"VBLENDPS $7, Y2, Y15, Y2", "c4 e3 05 0c d2 07"},
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{"VBLENDVPD X12, (BX), X9, X11", "c4 63 31 4b 1b c0"},
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{"VBLENDVPD X12, (BX), X9, X2", "c4 e3 31 4b 13 c0"},
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{"VBLENDVPD X12, (R11), X9, X11", "c4 43 31 4b 1b c0"},
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{"VBLENDVPD X12, (R11), X9, X2", "c4 c3 31 4b 13 c0"},
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{"VBLENDVPD X12, X11, X9, X11", "c4 43 31 4b db c0"},
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{"VBLENDVPD X12, X11, X9, X2", "c4 c3 31 4b d3 c0"},
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{"VBLENDVPD X12, X2, X9, X11", "c4 63 31 4b da c0"},
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{"VBLENDVPD X12, X2, X9, X2", "c4 e3 31 4b d2 c0"},
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{"VBLENDVPD Y13, (BX), Y15, Y11", "c4 63 05 4b 1b d0"},
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{"VBLENDVPD Y13, (BX), Y15, Y2", "c4 e3 05 4b 13 d0"},
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{"VBLENDVPD Y13, (R11), Y15, Y11", "c4 43 05 4b 1b d0"},
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{"VBLENDVPD Y13, (R11), Y15, Y2", "c4 c3 05 4b 13 d0"},
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{"VBLENDVPD Y13, Y11, Y15, Y11", "c4 43 05 4b db d0"},
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{"VBLENDVPD Y13, Y11, Y15, Y2", "c4 c3 05 4b d3 d0"},
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{"VBLENDVPD Y13, Y2, Y15, Y11", "c4 63 05 4b da d0"},
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{"VBLENDVPD Y13, Y2, Y15, Y2", "c4 e3 05 4b d2 d0"},
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{"VBLENDVPS X12, (BX), X9, X11", "c4 63 31 4a 1b c0"},
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{"VBLENDVPS X12, (BX), X9, X2", "c4 e3 31 4a 13 c0"},
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{"VBLENDVPS X12, (R11), X9, X11", "c4 43 31 4a 1b c0"},
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{"VBLENDVPS X12, (R11), X9, X2", "c4 c3 31 4a 13 c0"},
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{"VBLENDVPS X12, X11, X9, X11", "c4 43 31 4a db c0"},
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{"VBLENDVPS X12, X11, X9, X2", "c4 c3 31 4a d3 c0"},
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{"VBLENDVPS X12, X2, X9, X11", "c4 63 31 4a da c0"},
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{"VBLENDVPS X12, X2, X9, X2", "c4 e3 31 4a d2 c0"},
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{"VBLENDVPS Y13, (BX), Y15, Y11", "c4 63 05 4a 1b d0"},
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{"VBLENDVPS Y13, (BX), Y15, Y2", "c4 e3 05 4a 13 d0"},
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{"VBLENDVPS Y13, (R11), Y15, Y11", "c4 43 05 4a 1b d0"},
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{"VBLENDVPS Y13, (R11), Y15, Y2", "c4 c3 05 4a 13 d0"},
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{"VBLENDVPS Y13, Y11, Y15, Y11", "c4 43 05 4a db d0"},
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{"VBLENDVPS Y13, Y11, Y15, Y2", "c4 c3 05 4a d3 d0"},
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{"VBLENDVPS Y13, Y2, Y15, Y11", "c4 63 05 4a da d0"},
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{"VBLENDVPS Y13, Y2, Y15, Y2", "c4 e3 05 4a d2 d0"},
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{"VBROADCASTF128 (BX), Y11", "c4 62 7d 1a 1b"},
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{"VBROADCASTF128 (BX), Y2", "c4 e2 7d 1a 13"},
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{"VBROADCASTF128 (R11), Y11", "c4 42 7d 1a 1b"},
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{"VBROADCASTF128 (R11), Y2", "c4 c2 7d 1a 13"},
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{"VDPPD $7, (BX), X9, X11", "c4 63 31 41 1b 07"},
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{"VDPPD $7, (BX), X9, X2", "c4 e3 31 41 13 07"},
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{"VDPPD $7, (R11), X9, X11", "c4 43 31 41 1b 07"},
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{"VDPPD $7, (R11), X9, X2", "c4 c3 31 41 13 07"},
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{"VDPPD $7, X11, X9, X11", "c4 43 31 41 db 07"},
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{"VDPPD $7, X11, X9, X2", "c4 c3 31 41 d3 07"},
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{"VDPPD $7, X2, X9, X11", "c4 63 31 41 da 07"},
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{"VDPPD $7, X2, X9, X2", "c4 e3 31 41 d2 07"},
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{"VDPPS $7, (BX), X9, X11", "c4 63 31 40 1b 07"},
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{"VDPPS $7, (BX), X9, X2", "c4 e3 31 40 13 07"},
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{"VDPPS $7, (BX), Y15, Y11", "c4 63 05 40 1b 07"},
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{"VDPPS $7, (BX), Y15, Y2", "c4 e3 05 40 13 07"},
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{"VDPPS $7, (R11), X9, X11", "c4 43 31 40 1b 07"},
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{"VDPPS $7, (R11), X9, X2", "c4 c3 31 40 13 07"},
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{"VDPPS $7, (R11), Y15, Y11", "c4 43 05 40 1b 07"},
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{"VDPPS $7, (R11), Y15, Y2", "c4 c3 05 40 13 07"},
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{"VDPPS $7, X11, X9, X11", "c4 43 31 40 db 07"},
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{"VDPPS $7, X11, X9, X2", "c4 c3 31 40 d3 07"},
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{"VDPPS $7, X2, X9, X11", "c4 63 31 40 da 07"},
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{"VDPPS $7, X2, X9, X2", "c4 e3 31 40 d2 07"},
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{"VDPPS $7, Y11, Y15, Y11", "c4 43 05 40 db 07"},
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{"VDPPS $7, Y11, Y15, Y2", "c4 c3 05 40 d3 07"},
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{"VDPPS $7, Y2, Y15, Y11", "c4 63 05 40 da 07"},
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{"VDPPS $7, Y2, Y15, Y2", "c4 e3 05 40 d2 07"},
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{"VHADDPD (BX), X9, X11", "c5 31 7c 1b"},
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{"VHADDPD (BX), X9, X2", "c5 b1 7c 13"},
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{"VHADDPD (BX), Y15, Y11", "c5 05 7c 1b"},
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{"VHADDPD (BX), Y15, Y2", "c5 85 7c 13"},
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{"VHADDPD (R11), X9, X11", "c4 41 31 7c 1b"},
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{"VHADDPD (R11), X9, X2", "c4 c1 31 7c 13"},
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{"VHADDPD (R11), Y15, Y11", "c4 41 05 7c 1b"},
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{"VHADDPD (R11), Y15, Y2", "c4 c1 05 7c 13"},
|
||||
{"VHADDPD X11, X9, X11", "c4 41 31 7c db"},
|
||||
{"VHADDPD X11, X9, X2", "c4 c1 31 7c d3"},
|
||||
{"VHADDPD X2, X9, X11", "c5 31 7c da"},
|
||||
{"VHADDPD X2, X9, X2", "c5 b1 7c d2"},
|
||||
{"VHADDPD Y11, Y15, Y11", "c4 41 05 7c db"},
|
||||
{"VHADDPD Y11, Y15, Y2", "c4 c1 05 7c d3"},
|
||||
{"VHADDPD Y2, Y15, Y11", "c5 05 7c da"},
|
||||
{"VHADDPD Y2, Y15, Y2", "c5 85 7c d2"},
|
||||
{"VHADDPS (BX), X9, X11", "c5 33 7c 1b"},
|
||||
{"VHADDPS (BX), X9, X2", "c5 b3 7c 13"},
|
||||
{"VHADDPS (BX), Y15, Y11", "c5 07 7c 1b"},
|
||||
{"VHADDPS (BX), Y15, Y2", "c5 87 7c 13"},
|
||||
{"VHADDPS (R11), X9, X11", "c4 41 33 7c 1b"},
|
||||
{"VHADDPS (R11), X9, X2", "c4 c1 33 7c 13"},
|
||||
{"VHADDPS (R11), Y15, Y11", "c4 41 07 7c 1b"},
|
||||
{"VHADDPS (R11), Y15, Y2", "c4 c1 07 7c 13"},
|
||||
{"VHADDPS X11, X9, X11", "c4 41 33 7c db"},
|
||||
{"VHADDPS X11, X9, X2", "c4 c1 33 7c d3"},
|
||||
{"VHADDPS X2, X9, X11", "c5 33 7c da"},
|
||||
{"VHADDPS X2, X9, X2", "c5 b3 7c d2"},
|
||||
{"VHADDPS Y11, Y15, Y11", "c4 41 07 7c db"},
|
||||
{"VHADDPS Y11, Y15, Y2", "c4 c1 07 7c d3"},
|
||||
{"VHADDPS Y2, Y15, Y11", "c5 07 7c da"},
|
||||
{"VHADDPS Y2, Y15, Y2", "c5 87 7c d2"},
|
||||
{"VHSUBPD (BX), X9, X11", "c5 31 7d 1b"},
|
||||
{"VHSUBPD (BX), X9, X2", "c5 b1 7d 13"},
|
||||
{"VHSUBPD (BX), Y15, Y11", "c5 05 7d 1b"},
|
||||
{"VHSUBPD (BX), Y15, Y2", "c5 85 7d 13"},
|
||||
{"VHSUBPD (R11), X9, X11", "c4 41 31 7d 1b"},
|
||||
{"VHSUBPD (R11), X9, X2", "c4 c1 31 7d 13"},
|
||||
{"VHSUBPD (R11), Y15, Y11", "c4 41 05 7d 1b"},
|
||||
{"VHSUBPD (R11), Y15, Y2", "c4 c1 05 7d 13"},
|
||||
{"VHSUBPD X11, X9, X11", "c4 41 31 7d db"},
|
||||
{"VHSUBPD X11, X9, X2", "c4 c1 31 7d d3"},
|
||||
{"VHSUBPD X2, X9, X11", "c5 31 7d da"},
|
||||
{"VHSUBPD X2, X9, X2", "c5 b1 7d d2"},
|
||||
{"VHSUBPD Y11, Y15, Y11", "c4 41 05 7d db"},
|
||||
{"VHSUBPD Y11, Y15, Y2", "c4 c1 05 7d d3"},
|
||||
{"VHSUBPD Y2, Y15, Y11", "c5 05 7d da"},
|
||||
{"VHSUBPD Y2, Y15, Y2", "c5 85 7d d2"},
|
||||
{"VHSUBPS (BX), X9, X11", "c5 33 7d 1b"},
|
||||
{"VHSUBPS (BX), X9, X2", "c5 b3 7d 13"},
|
||||
{"VHSUBPS (BX), Y15, Y11", "c5 07 7d 1b"},
|
||||
{"VHSUBPS (BX), Y15, Y2", "c5 87 7d 13"},
|
||||
{"VHSUBPS (R11), X9, X11", "c4 41 33 7d 1b"},
|
||||
{"VHSUBPS (R11), X9, X2", "c4 c1 33 7d 13"},
|
||||
{"VHSUBPS (R11), Y15, Y11", "c4 41 07 7d 1b"},
|
||||
{"VHSUBPS (R11), Y15, Y2", "c4 c1 07 7d 13"},
|
||||
{"VHSUBPS X11, X9, X11", "c4 41 33 7d db"},
|
||||
{"VHSUBPS X11, X9, X2", "c4 c1 33 7d d3"},
|
||||
{"VHSUBPS X2, X9, X11", "c5 33 7d da"},
|
||||
{"VHSUBPS X2, X9, X2", "c5 b3 7d d2"},
|
||||
{"VHSUBPS Y11, Y15, Y11", "c4 41 07 7d db"},
|
||||
{"VHSUBPS Y11, Y15, Y2", "c4 c1 07 7d d3"},
|
||||
{"VHSUBPS Y2, Y15, Y11", "c5 07 7d da"},
|
||||
{"VHSUBPS Y2, Y15, Y2", "c5 87 7d d2"},
|
||||
{"VINSERTF128 $7, (BX), Y15, Y11", "c4 63 05 18 1b 07"},
|
||||
{"VINSERTF128 $7, (BX), Y15, Y2", "c4 e3 05 18 13 07"},
|
||||
{"VINSERTF128 $7, (R11), Y15, Y11", "c4 43 05 18 1b 07"},
|
||||
{"VINSERTF128 $7, (R11), Y15, Y2", "c4 c3 05 18 13 07"},
|
||||
{"VINSERTF128 $7, X11, Y15, Y11", "c4 43 05 18 db 07"},
|
||||
{"VINSERTF128 $7, X11, Y15, Y2", "c4 c3 05 18 d3 07"},
|
||||
{"VINSERTF128 $7, X2, Y15, Y11", "c4 63 05 18 da 07"},
|
||||
{"VINSERTF128 $7, X2, Y15, Y2", "c4 e3 05 18 d2 07"},
|
||||
{"VINSERTPS $7, (BX), X9, X11", "c4 63 31 21 1b 07"},
|
||||
{"VINSERTPS $7, (BX), X9, X2", "c4 e3 31 21 13 07"},
|
||||
{"VINSERTPS $7, (R11), X9, X11", "c4 43 31 21 1b 07"},
|
||||
{"VINSERTPS $7, (R11), X9, X2", "c4 c3 31 21 13 07"},
|
||||
{"VINSERTPS $7, X11, X9, X11", "c4 43 31 21 db 07"},
|
||||
{"VINSERTPS $7, X11, X9, X2", "c4 c3 31 21 d3 07"},
|
||||
{"VINSERTPS $7, X2, X9, X11", "c4 63 31 21 da 07"},
|
||||
{"VINSERTPS $7, X2, X9, X2", "c4 e3 31 21 d2 07"},
|
||||
{"VLDDQU (BX), X11", "c5 7b f0 1b"},
|
||||
{"VLDDQU (BX), X2", "c5 fb f0 13"},
|
||||
{"VLDDQU (BX), Y11", "c5 7f f0 1b"},
|
||||
{"VLDDQU (BX), Y2", "c5 ff f0 13"},
|
||||
{"VLDDQU (R11), X11", "c4 41 7b f0 1b"},
|
||||
{"VLDDQU (R11), X2", "c4 c1 7b f0 13"},
|
||||
{"VLDDQU (R11), Y11", "c4 41 7f f0 1b"},
|
||||
{"VLDDQU (R11), Y2", "c4 c1 7f f0 13"},
|
||||
{"VLDMXCSR (BX)", "c5 f8 ae 13"},
|
||||
{"VLDMXCSR (R11)", "c4 c1 78 ae 13"},
|
||||
{"VMASKMOVDQU X11, X11", "c4 41 79 f7 db"},
|
||||
{"VMASKMOVDQU X11, X2", "c4 c1 79 f7 d3"},
|
||||
{"VMASKMOVDQU X2, X11", "c5 79 f7 da"},
|
||||
{"VMASKMOVDQU X2, X2", "c5 f9 f7 d2"},
|
||||
{"VMASKMOVPD (BX), X9, X11", "c4 62 31 2d 1b"},
|
||||
{"VMASKMOVPD (BX), X9, X2", "c4 e2 31 2d 13"},
|
||||
{"VMASKMOVPD (BX), Y15, Y11", "c4 62 05 2d 1b"},
|
||||
{"VMASKMOVPD (BX), Y15, Y2", "c4 e2 05 2d 13"},
|
||||
{"VMASKMOVPD (R11), X9, X11", "c4 42 31 2d 1b"},
|
||||
{"VMASKMOVPD (R11), X9, X2", "c4 c2 31 2d 13"},
|
||||
{"VMASKMOVPD (R11), Y15, Y11", "c4 42 05 2d 1b"},
|
||||
{"VMASKMOVPD (R11), Y15, Y2", "c4 c2 05 2d 13"},
|
||||
{"VMASKMOVPD X11, X9, (BX)", "c4 62 31 2f 1b"},
|
||||
{"VMASKMOVPD X11, X9, (R11)", "c4 42 31 2f 1b"},
|
||||
{"VMASKMOVPD X2, X9, (BX)", "c4 e2 31 2f 13"},
|
||||
{"VMASKMOVPD X2, X9, (R11)", "c4 c2 31 2f 13"},
|
||||
{"VMASKMOVPD Y11, Y15, (BX)", "c4 62 05 2f 1b"},
|
||||
{"VMASKMOVPD Y11, Y15, (R11)", "c4 42 05 2f 1b"},
|
||||
{"VMASKMOVPD Y2, Y15, (BX)", "c4 e2 05 2f 13"},
|
||||
{"VMASKMOVPD Y2, Y15, (R11)", "c4 c2 05 2f 13"},
|
||||
{"VMASKMOVPS (BX), X9, X11", "c4 62 31 2c 1b"},
|
||||
{"VMASKMOVPS (BX), X9, X2", "c4 e2 31 2c 13"},
|
||||
{"VMASKMOVPS (BX), Y15, Y11", "c4 62 05 2c 1b"},
|
||||
{"VMASKMOVPS (BX), Y15, Y2", "c4 e2 05 2c 13"},
|
||||
{"VMASKMOVPS (R11), X9, X11", "c4 42 31 2c 1b"},
|
||||
{"VMASKMOVPS (R11), X9, X2", "c4 c2 31 2c 13"},
|
||||
{"VMASKMOVPS (R11), Y15, Y11", "c4 42 05 2c 1b"},
|
||||
{"VMASKMOVPS (R11), Y15, Y2", "c4 c2 05 2c 13"},
|
||||
{"VMASKMOVPS X11, X9, (BX)", "c4 62 31 2e 1b"},
|
||||
{"VMASKMOVPS X11, X9, (R11)", "c4 42 31 2e 1b"},
|
||||
{"VMASKMOVPS X2, X9, (BX)", "c4 e2 31 2e 13"},
|
||||
{"VMASKMOVPS X2, X9, (R11)", "c4 c2 31 2e 13"},
|
||||
{"VMASKMOVPS Y11, Y15, (BX)", "c4 62 05 2e 1b"},
|
||||
{"VMASKMOVPS Y11, Y15, (R11)", "c4 42 05 2e 1b"},
|
||||
{"VMASKMOVPS Y2, Y15, (BX)", "c4 e2 05 2e 13"},
|
||||
{"VMASKMOVPS Y2, Y15, (R11)", "c4 c2 05 2e 13"},
|
||||
{"VMOVHLPS X11, X9, X11", "c4 41 30 12 db"},
|
||||
{"VMOVHLPS X11, X9, X2", "c4 c1 30 12 d3"},
|
||||
{"VMOVHLPS X2, X9, X11", "c5 30 12 da"},
|
||||
{"VMOVHLPS X2, X9, X2", "c5 b0 12 d2"},
|
||||
{"VMOVLPS (BX), X9, X11", "c5 30 12 1b"},
|
||||
{"VMOVLPS (BX), X9, X2", "c5 b0 12 13"},
|
||||
{"VMOVLPS (R11), X9, X11", "c4 41 30 12 1b"},
|
||||
{"VMOVLPS (R11), X9, X2", "c4 c1 30 12 13"},
|
||||
{"VMOVLPS X11, (BX)", "c5 78 13 1b"},
|
||||
{"VMOVLPS X11, (R11)", "c4 41 78 13 1b"},
|
||||
{"VMOVLPS X2, (BX)", "c5 f8 13 13"},
|
||||
{"VMOVLPS X2, (R11)", "c4 c1 78 13 13"},
|
||||
{"VMOVMSKPD X11, DX", "c4 c1 79 50 d3"},
|
||||
{"VMOVMSKPD X11, R11", "c4 41 79 50 db"},
|
||||
{"VMOVMSKPD X2, DX", "c5 f9 50 d2"},
|
||||
{"VMOVMSKPD X2, R11", "c5 79 50 da"},
|
||||
{"VMOVMSKPD Y11, DX", "c4 c1 7d 50 d3"},
|
||||
{"VMOVMSKPD Y11, R11", "c4 41 7d 50 db"},
|
||||
{"VMOVMSKPD Y2, DX", "c5 fd 50 d2"},
|
||||
{"VMOVMSKPD Y2, R11", "c5 7d 50 da"},
|
||||
{"VMOVSD (BX), X11", "c5 7b 10 1b"},
|
||||
{"VMOVSD (BX), X2", "c5 fb 10 13"},
|
||||
{"VMOVSD (R11), X11", "c4 41 7b 10 1b"},
|
||||
{"VMOVSD (R11), X2", "c4 c1 7b 10 13"},
|
||||
{"VMOVSD X11, (BX)", "c5 7b 11 1b"},
|
||||
{"VMOVSD X11, (R11)", "c4 41 7b 11 1b"},
|
||||
{"VMOVSD X11, X9, X11", "c4 41 33 11 db"},
|
||||
{"VMOVSD X11, X9, X2", "c5 33 11 da"},
|
||||
{"VMOVSD X2, (BX)", "c5 fb 11 13"},
|
||||
{"VMOVSD X2, (R11)", "c4 c1 7b 11 13"},
|
||||
{"VMOVSD X2, X9, X11", "c4 c1 33 11 d3"},
|
||||
{"VMOVSD X2, X9, X2", "c5 b3 11 d2"},
|
||||
{"VMOVSS (BX), X11", "c5 7a 10 1b"},
|
||||
{"VMOVSS (BX), X2", "c5 fa 10 13"},
|
||||
{"VMOVSS (R11), X11", "c4 41 7a 10 1b"},
|
||||
{"VMOVSS (R11), X2", "c4 c1 7a 10 13"},
|
||||
{"VMOVSS X11, (BX)", "c5 7a 11 1b"},
|
||||
{"VMOVSS X11, (R11)", "c4 41 7a 11 1b"},
|
||||
{"VMOVSS X11, X9, X11", "c4 41 32 11 db"},
|
||||
{"VMOVSS X11, X9, X2", "c5 32 11 da"},
|
||||
{"VMOVSS X2, (BX)", "c5 fa 11 13"},
|
||||
{"VMOVSS X2, (R11)", "c4 c1 7a 11 13"},
|
||||
{"VMOVSS X2, X9, X11", "c4 c1 32 11 d3"},
|
||||
{"VMOVSS X2, X9, X2", "c5 b2 11 d2"},
|
||||
{"VMPSADBW $7, (BX), X9, X11", "c4 63 31 42 1b 07"},
|
||||
{"VMPSADBW $7, (BX), X9, X2", "c4 e3 31 42 13 07"},
|
||||
{"VMPSADBW $7, (BX), Y15, Y11", "c4 63 05 42 1b 07"},
|
||||
{"VMPSADBW $7, (BX), Y15, Y2", "c4 e3 05 42 13 07"},
|
||||
{"VMPSADBW $7, (R11), X9, X11", "c4 43 31 42 1b 07"},
|
||||
{"VMPSADBW $7, (R11), X9, X2", "c4 c3 31 42 13 07"},
|
||||
{"VMPSADBW $7, (R11), Y15, Y11", "c4 43 05 42 1b 07"},
|
||||
{"VMPSADBW $7, (R11), Y15, Y2", "c4 c3 05 42 13 07"},
|
||||
{"VMPSADBW $7, X11, X9, X11", "c4 43 31 42 db 07"},
|
||||
{"VMPSADBW $7, X11, X9, X2", "c4 c3 31 42 d3 07"},
|
||||
{"VMPSADBW $7, X2, X9, X11", "c4 63 31 42 da 07"},
|
||||
{"VMPSADBW $7, X2, X9, X2", "c4 e3 31 42 d2 07"},
|
||||
{"VMPSADBW $7, Y11, Y15, Y11", "c4 43 05 42 db 07"},
|
||||
{"VMPSADBW $7, Y11, Y15, Y2", "c4 c3 05 42 d3 07"},
|
||||
{"VMPSADBW $7, Y2, Y15, Y11", "c4 63 05 42 da 07"},
|
||||
{"VMPSADBW $7, Y2, Y15, Y2", "c4 e3 05 42 d2 07"},
|
||||
{"VPBLENDVB X12, (BX), X9, X11", "c4 63 31 4c 1b c0"},
|
||||
{"VPBLENDVB X12, (BX), X9, X2", "c4 e3 31 4c 13 c0"},
|
||||
{"VPBLENDVB X12, (R11), X9, X11", "c4 43 31 4c 1b c0"},
|
||||
{"VPBLENDVB X12, (R11), X9, X2", "c4 c3 31 4c 13 c0"},
|
||||
{"VPBLENDVB X12, X11, X9, X11", "c4 43 31 4c db c0"},
|
||||
{"VPBLENDVB X12, X11, X9, X2", "c4 c3 31 4c d3 c0"},
|
||||
{"VPBLENDVB X12, X2, X9, X11", "c4 63 31 4c da c0"},
|
||||
{"VPBLENDVB X12, X2, X9, X2", "c4 e3 31 4c d2 c0"},
|
||||
{"VPBLENDVB Y13, (BX), Y15, Y11", "c4 63 05 4c 1b d0"},
|
||||
{"VPBLENDVB Y13, (BX), Y15, Y2", "c4 e3 05 4c 13 d0"},
|
||||
{"VPBLENDVB Y13, (R11), Y15, Y11", "c4 43 05 4c 1b d0"},
|
||||
{"VPBLENDVB Y13, (R11), Y15, Y2", "c4 c3 05 4c 13 d0"},
|
||||
{"VPBLENDVB Y13, Y11, Y15, Y11", "c4 43 05 4c db d0"},
|
||||
{"VPBLENDVB Y13, Y11, Y15, Y2", "c4 c3 05 4c d3 d0"},
|
||||
{"VPBLENDVB Y13, Y2, Y15, Y11", "c4 63 05 4c da d0"},
|
||||
{"VPBLENDVB Y13, Y2, Y15, Y2", "c4 e3 05 4c d2 d0"},
|
||||
{"VPBLENDW $7, (BX), X9, X11", "c4 63 31 0e 1b 07"},
|
||||
{"VPBLENDW $7, (BX), X9, X2", "c4 e3 31 0e 13 07"},
|
||||
{"VPBLENDW $7, (BX), Y15, Y11", "c4 63 05 0e 1b 07"},
|
||||
{"VPBLENDW $7, (BX), Y15, Y2", "c4 e3 05 0e 13 07"},
|
||||
{"VPBLENDW $7, (R11), X9, X11", "c4 43 31 0e 1b 07"},
|
||||
{"VPBLENDW $7, (R11), X9, X2", "c4 c3 31 0e 13 07"},
|
||||
{"VPBLENDW $7, (R11), Y15, Y11", "c4 43 05 0e 1b 07"},
|
||||
{"VPBLENDW $7, (R11), Y15, Y2", "c4 c3 05 0e 13 07"},
|
||||
{"VPBLENDW $7, X11, X9, X11", "c4 43 31 0e db 07"},
|
||||
{"VPBLENDW $7, X11, X9, X2", "c4 c3 31 0e d3 07"},
|
||||
{"VPBLENDW $7, X2, X9, X11", "c4 63 31 0e da 07"},
|
||||
{"VPBLENDW $7, X2, X9, X2", "c4 e3 31 0e d2 07"},
|
||||
{"VPBLENDW $7, Y11, Y15, Y11", "c4 43 05 0e db 07"},
|
||||
{"VPBLENDW $7, Y11, Y15, Y2", "c4 c3 05 0e d3 07"},
|
||||
{"VPBLENDW $7, Y2, Y15, Y11", "c4 63 05 0e da 07"},
|
||||
{"VPBLENDW $7, Y2, Y15, Y2", "c4 e3 05 0e d2 07"},
|
||||
{"VPERMILPD $7, (BX), X11", "c4 63 79 05 1b 07"},
|
||||
{"VPERMILPD $7, (BX), X2", "c4 e3 79 05 13 07"},
|
||||
{"VPERMILPD $7, (BX), Y11", "c4 63 7d 05 1b 07"},
|
||||
{"VPERMILPD $7, (BX), Y2", "c4 e3 7d 05 13 07"},
|
||||
{"VPERMILPD $7, (R11), X11", "c4 43 79 05 1b 07"},
|
||||
{"VPERMILPD $7, (R11), X2", "c4 c3 79 05 13 07"},
|
||||
{"VPERMILPD $7, (R11), Y11", "c4 43 7d 05 1b 07"},
|
||||
{"VPERMILPD $7, (R11), Y2", "c4 c3 7d 05 13 07"},
|
||||
{"VPERMILPD $7, X11, X11", "c4 43 79 05 db 07"},
|
||||
{"VPERMILPD $7, X11, X2", "c4 c3 79 05 d3 07"},
|
||||
{"VPERMILPD $7, X2, X11", "c4 63 79 05 da 07"},
|
||||
{"VPERMILPD $7, X2, X2", "c4 e3 79 05 d2 07"},
|
||||
{"VPERMILPD $7, Y11, Y11", "c4 43 7d 05 db 07"},
|
||||
{"VPERMILPD $7, Y11, Y2", "c4 c3 7d 05 d3 07"},
|
||||
{"VPERMILPD $7, Y2, Y11", "c4 63 7d 05 da 07"},
|
||||
{"VPERMILPD $7, Y2, Y2", "c4 e3 7d 05 d2 07"},
|
||||
{"VPERMILPD (BX), X9, X11", "c4 62 31 0d 1b"},
|
||||
{"VPERMILPD (BX), X9, X2", "c4 e2 31 0d 13"},
|
||||
{"VPERMILPD (BX), Y15, Y11", "c4 62 05 0d 1b"},
|
||||
{"VPERMILPD (BX), Y15, Y2", "c4 e2 05 0d 13"},
|
||||
{"VPERMILPD (R11), X9, X11", "c4 42 31 0d 1b"},
|
||||
{"VPERMILPD (R11), X9, X2", "c4 c2 31 0d 13"},
|
||||
{"VPERMILPD (R11), Y15, Y11", "c4 42 05 0d 1b"},
|
||||
{"VPERMILPD (R11), Y15, Y2", "c4 c2 05 0d 13"},
|
||||
{"VPERMILPD X11, X9, X11", "c4 42 31 0d db"},
|
||||
{"VPERMILPD X11, X9, X2", "c4 c2 31 0d d3"},
|
||||
{"VPERMILPD X2, X9, X11", "c4 62 31 0d da"},
|
||||
{"VPERMILPD X2, X9, X2", "c4 e2 31 0d d2"},
|
||||
{"VPERMILPD Y11, Y15, Y11", "c4 42 05 0d db"},
|
||||
{"VPERMILPD Y11, Y15, Y2", "c4 c2 05 0d d3"},
|
||||
{"VPERMILPD Y2, Y15, Y11", "c4 62 05 0d da"},
|
||||
{"VPERMILPD Y2, Y15, Y2", "c4 e2 05 0d d2"},
|
||||
{"VPERMILPS $7, (BX), X11", "c4 63 79 04 1b 07"},
|
||||
{"VPERMILPS $7, (BX), X2", "c4 e3 79 04 13 07"},
|
||||
{"VPERMILPS $7, (BX), Y11", "c4 63 7d 04 1b 07"},
|
||||
{"VPERMILPS $7, (BX), Y2", "c4 e3 7d 04 13 07"},
|
||||
{"VPERMILPS $7, (R11), X11", "c4 43 79 04 1b 07"},
|
||||
{"VPERMILPS $7, (R11), X2", "c4 c3 79 04 13 07"},
|
||||
{"VPERMILPS $7, (R11), Y11", "c4 43 7d 04 1b 07"},
|
||||
{"VPERMILPS $7, (R11), Y2", "c4 c3 7d 04 13 07"},
|
||||
{"VPERMILPS $7, X11, X11", "c4 43 79 04 db 07"},
|
||||
{"VPERMILPS $7, X11, X2", "c4 c3 79 04 d3 07"},
|
||||
{"VPERMILPS $7, X2, X11", "c4 63 79 04 da 07"},
|
||||
{"VPERMILPS $7, X2, X2", "c4 e3 79 04 d2 07"},
|
||||
{"VPERMILPS $7, Y11, Y11", "c4 43 7d 04 db 07"},
|
||||
{"VPERMILPS $7, Y11, Y2", "c4 c3 7d 04 d3 07"},
|
||||
{"VPERMILPS $7, Y2, Y11", "c4 63 7d 04 da 07"},
|
||||
{"VPERMILPS $7, Y2, Y2", "c4 e3 7d 04 d2 07"},
|
||||
{"VPERMILPS (BX), X9, X11", "c4 62 31 0c 1b"},
|
||||
{"VPERMILPS (BX), X9, X2", "c4 e2 31 0c 13"},
|
||||
{"VPERMILPS (BX), Y15, Y11", "c4 62 05 0c 1b"},
|
||||
{"VPERMILPS (BX), Y15, Y2", "c4 e2 05 0c 13"},
|
||||
{"VPERMILPS (R11), X9, X11", "c4 42 31 0c 1b"},
|
||||
{"VPERMILPS (R11), X9, X2", "c4 c2 31 0c 13"},
|
||||
{"VPERMILPS (R11), Y15, Y11", "c4 42 05 0c 1b"},
|
||||
{"VPERMILPS (R11), Y15, Y2", "c4 c2 05 0c 13"},
|
||||
{"VPERMILPS X11, X9, X11", "c4 42 31 0c db"},
|
||||
{"VPERMILPS X11, X9, X2", "c4 c2 31 0c d3"},
|
||||
{"VPERMILPS X2, X9, X11", "c4 62 31 0c da"},
|
||||
{"VPERMILPS X2, X9, X2", "c4 e2 31 0c d2"},
|
||||
{"VPERMILPS Y11, Y15, Y11", "c4 42 05 0c db"},
|
||||
{"VPERMILPS Y11, Y15, Y2", "c4 c2 05 0c d3"},
|
||||
{"VPERMILPS Y2, Y15, Y11", "c4 62 05 0c da"},
|
||||
{"VPERMILPS Y2, Y15, Y2", "c4 e2 05 0c d2"},
|
||||
{"VPHADDD (BX), X9, X11", "c4 62 31 02 1b"},
|
||||
{"VPHADDD (BX), X9, X2", "c4 e2 31 02 13"},
|
||||
{"VPHADDD (BX), Y15, Y11", "c4 62 05 02 1b"},
|
||||
{"VPHADDD (BX), Y15, Y2", "c4 e2 05 02 13"},
|
||||
{"VPHADDD (R11), X9, X11", "c4 42 31 02 1b"},
|
||||
{"VPHADDD (R11), X9, X2", "c4 c2 31 02 13"},
|
||||
{"VPHADDD (R11), Y15, Y11", "c4 42 05 02 1b"},
|
||||
{"VPHADDD (R11), Y15, Y2", "c4 c2 05 02 13"},
|
||||
{"VPHADDD X11, X9, X11", "c4 42 31 02 db"},
|
||||
{"VPHADDD X11, X9, X2", "c4 c2 31 02 d3"},
|
||||
{"VPHADDD X2, X9, X11", "c4 62 31 02 da"},
|
||||
{"VPHADDD X2, X9, X2", "c4 e2 31 02 d2"},
|
||||
{"VPHADDD Y11, Y15, Y11", "c4 42 05 02 db"},
|
||||
{"VPHADDD Y11, Y15, Y2", "c4 c2 05 02 d3"},
|
||||
{"VPHADDD Y2, Y15, Y11", "c4 62 05 02 da"},
|
||||
{"VPHADDD Y2, Y15, Y2", "c4 e2 05 02 d2"},
|
||||
{"VPHADDSW (BX), X9, X11", "c4 62 31 03 1b"},
|
||||
{"VPHADDSW (BX), X9, X2", "c4 e2 31 03 13"},
|
||||
{"VPHADDSW (BX), Y15, Y11", "c4 62 05 03 1b"},
|
||||
{"VPHADDSW (BX), Y15, Y2", "c4 e2 05 03 13"},
|
||||
{"VPHADDSW (R11), X9, X11", "c4 42 31 03 1b"},
|
||||
{"VPHADDSW (R11), X9, X2", "c4 c2 31 03 13"},
|
||||
{"VPHADDSW (R11), Y15, Y11", "c4 42 05 03 1b"},
|
||||
{"VPHADDSW (R11), Y15, Y2", "c4 c2 05 03 13"},
|
||||
{"VPHADDSW X11, X9, X11", "c4 42 31 03 db"},
|
||||
{"VPHADDSW X11, X9, X2", "c4 c2 31 03 d3"},
|
||||
{"VPHADDSW X2, X9, X11", "c4 62 31 03 da"},
|
||||
{"VPHADDSW X2, X9, X2", "c4 e2 31 03 d2"},
|
||||
{"VPHADDSW Y11, Y15, Y11", "c4 42 05 03 db"},
|
||||
{"VPHADDSW Y11, Y15, Y2", "c4 c2 05 03 d3"},
|
||||
{"VPHADDSW Y2, Y15, Y11", "c4 62 05 03 da"},
|
||||
{"VPHADDSW Y2, Y15, Y2", "c4 e2 05 03 d2"},
|
||||
{"VPHADDW (BX), X9, X11", "c4 62 31 01 1b"},
|
||||
{"VPHADDW (BX), X9, X2", "c4 e2 31 01 13"},
|
||||
{"VPHADDW (BX), Y15, Y11", "c4 62 05 01 1b"},
|
||||
{"VPHADDW (BX), Y15, Y2", "c4 e2 05 01 13"},
|
||||
{"VPHADDW (R11), X9, X11", "c4 42 31 01 1b"},
|
||||
{"VPHADDW (R11), X9, X2", "c4 c2 31 01 13"},
|
||||
{"VPHADDW (R11), Y15, Y11", "c4 42 05 01 1b"},
|
||||
{"VPHADDW (R11), Y15, Y2", "c4 c2 05 01 13"},
|
||||
{"VPHADDW X11, X9, X11", "c4 42 31 01 db"},
|
||||
{"VPHADDW X11, X9, X2", "c4 c2 31 01 d3"},
|
||||
{"VPHADDW X2, X9, X11", "c4 62 31 01 da"},
|
||||
{"VPHADDW X2, X9, X2", "c4 e2 31 01 d2"},
|
||||
{"VPHADDW Y11, Y15, Y11", "c4 42 05 01 db"},
|
||||
{"VPHADDW Y11, Y15, Y2", "c4 c2 05 01 d3"},
|
||||
{"VPHADDW Y2, Y15, Y11", "c4 62 05 01 da"},
|
||||
{"VPHADDW Y2, Y15, Y2", "c4 e2 05 01 d2"},
|
||||
{"VPHMINPOSUW (BX), X11", "c4 62 79 41 1b"},
|
||||
{"VPHMINPOSUW (BX), X2", "c4 e2 79 41 13"},
|
||||
{"VPHMINPOSUW (R11), X11", "c4 42 79 41 1b"},
|
||||
{"VPHMINPOSUW (R11), X2", "c4 c2 79 41 13"},
|
||||
{"VPHMINPOSUW X11, X11", "c4 42 79 41 db"},
|
||||
{"VPHMINPOSUW X11, X2", "c4 c2 79 41 d3"},
|
||||
{"VPHMINPOSUW X2, X11", "c4 62 79 41 da"},
|
||||
{"VPHMINPOSUW X2, X2", "c4 e2 79 41 d2"},
|
||||
{"VPHSUBD (BX), X9, X11", "c4 62 31 06 1b"},
|
||||
{"VPHSUBD (BX), X9, X2", "c4 e2 31 06 13"},
|
||||
{"VPHSUBD (BX), Y15, Y11", "c4 62 05 06 1b"},
|
||||
{"VPHSUBD (BX), Y15, Y2", "c4 e2 05 06 13"},
|
||||
{"VPHSUBD (R11), X9, X11", "c4 42 31 06 1b"},
|
||||
{"VPHSUBD (R11), X9, X2", "c4 c2 31 06 13"},
|
||||
{"VPHSUBD (R11), Y15, Y11", "c4 42 05 06 1b"},
|
||||
{"VPHSUBD (R11), Y15, Y2", "c4 c2 05 06 13"},
|
||||
{"VPHSUBD X11, X9, X11", "c4 42 31 06 db"},
|
||||
{"VPHSUBD X11, X9, X2", "c4 c2 31 06 d3"},
|
||||
{"VPHSUBD X2, X9, X11", "c4 62 31 06 da"},
|
||||
{"VPHSUBD X2, X9, X2", "c4 e2 31 06 d2"},
|
||||
{"VPHSUBD Y11, Y15, Y11", "c4 42 05 06 db"},
|
||||
{"VPHSUBD Y11, Y15, Y2", "c4 c2 05 06 d3"},
|
||||
{"VPHSUBD Y2, Y15, Y11", "c4 62 05 06 da"},
|
||||
{"VPHSUBD Y2, Y15, Y2", "c4 e2 05 06 d2"},
|
||||
{"VPHSUBSW (BX), X9, X11", "c4 62 31 07 1b"},
|
||||
{"VPHSUBSW (BX), X9, X2", "c4 e2 31 07 13"},
|
||||
{"VPHSUBSW (BX), Y15, Y11", "c4 62 05 07 1b"},
|
||||
{"VPHSUBSW (BX), Y15, Y2", "c4 e2 05 07 13"},
|
||||
{"VPHSUBSW (R11), X9, X11", "c4 42 31 07 1b"},
|
||||
{"VPHSUBSW (R11), X9, X2", "c4 c2 31 07 13"},
|
||||
{"VPHSUBSW (R11), Y15, Y11", "c4 42 05 07 1b"},
|
||||
{"VPHSUBSW (R11), Y15, Y2", "c4 c2 05 07 13"},
|
||||
{"VPHSUBSW X11, X9, X11", "c4 42 31 07 db"},
|
||||
{"VPHSUBSW X11, X9, X2", "c4 c2 31 07 d3"},
|
||||
{"VPHSUBSW X2, X9, X11", "c4 62 31 07 da"},
|
||||
{"VPHSUBSW X2, X9, X2", "c4 e2 31 07 d2"},
|
||||
{"VPHSUBSW Y11, Y15, Y11", "c4 42 05 07 db"},
|
||||
{"VPHSUBSW Y11, Y15, Y2", "c4 c2 05 07 d3"},
|
||||
{"VPHSUBSW Y2, Y15, Y11", "c4 62 05 07 da"},
|
||||
{"VPHSUBSW Y2, Y15, Y2", "c4 e2 05 07 d2"},
|
||||
{"VPHSUBW (BX), X9, X11", "c4 62 31 05 1b"},
|
||||
{"VPHSUBW (BX), X9, X2", "c4 e2 31 05 13"},
|
||||
{"VPHSUBW (BX), Y15, Y11", "c4 62 05 05 1b"},
|
||||
{"VPHSUBW (BX), Y15, Y2", "c4 e2 05 05 13"},
|
||||
{"VPHSUBW (R11), X9, X11", "c4 42 31 05 1b"},
|
||||
{"VPHSUBW (R11), X9, X2", "c4 c2 31 05 13"},
|
||||
{"VPHSUBW (R11), Y15, Y11", "c4 42 05 05 1b"},
|
||||
{"VPHSUBW (R11), Y15, Y2", "c4 c2 05 05 13"},
|
||||
{"VPHSUBW X11, X9, X11", "c4 42 31 05 db"},
|
||||
{"VPHSUBW X11, X9, X2", "c4 c2 31 05 d3"},
|
||||
{"VPHSUBW X2, X9, X11", "c4 62 31 05 da"},
|
||||
{"VPHSUBW X2, X9, X2", "c4 e2 31 05 d2"},
|
||||
{"VPHSUBW Y11, Y15, Y11", "c4 42 05 05 db"},
|
||||
{"VPHSUBW Y11, Y15, Y2", "c4 c2 05 05 d3"},
|
||||
{"VPHSUBW Y2, Y15, Y11", "c4 62 05 05 da"},
|
||||
{"VPHSUBW Y2, Y15, Y2", "c4 e2 05 05 d2"},
|
||||
{"VPINSRB $7, (BX), X9, X11", "c4 63 31 20 1b 07"},
|
||||
{"VPINSRB $7, (BX), X9, X2", "c4 e3 31 20 13 07"},
|
||||
{"VPINSRB $7, (R11), X9, X11", "c4 43 31 20 1b 07"},
|
||||
{"VPINSRB $7, (R11), X9, X2", "c4 c3 31 20 13 07"},
|
||||
{"VPINSRB $7, DX, X9, X11", "c4 63 31 20 da 07"},
|
||||
{"VPINSRB $7, DX, X9, X2", "c4 e3 31 20 d2 07"},
|
||||
{"VPINSRB $7, R11, X9, X11", "c4 43 31 20 db 07"},
|
||||
{"VPINSRB $7, R11, X9, X2", "c4 c3 31 20 d3 07"},
|
||||
{"VPINSRW $7, (BX), X9, X11", "c5 31 c4 1b 07"},
|
||||
{"VPINSRW $7, (BX), X9, X2", "c5 b1 c4 13 07"},
|
||||
{"VPINSRW $7, (R11), X9, X11", "c4 41 31 c4 1b 07"},
|
||||
{"VPINSRW $7, (R11), X9, X2", "c4 c1 31 c4 13 07"},
|
||||
{"VPINSRW $7, DX, X9, X11", "c5 31 c4 da 07"},
|
||||
{"VPINSRW $7, DX, X9, X2", "c5 b1 c4 d2 07"},
|
||||
{"VPINSRW $7, R11, X9, X11", "c4 41 31 c4 db 07"},
|
||||
{"VPINSRW $7, R11, X9, X2", "c4 c1 31 c4 d3 07"},
|
||||
{"VPMASKMOVD (BX), X9, X11", "c4 62 31 8c 1b"},
|
||||
{"VPMASKMOVD (BX), X9, X2", "c4 e2 31 8c 13"},
|
||||
{"VPMASKMOVD (BX), Y15, Y11", "c4 62 05 8c 1b"},
|
||||
{"VPMASKMOVD (BX), Y15, Y2", "c4 e2 05 8c 13"},
|
||||
{"VPMASKMOVD (R11), X9, X11", "c4 42 31 8c 1b"},
|
||||
{"VPMASKMOVD (R11), X9, X2", "c4 c2 31 8c 13"},
|
||||
{"VPMASKMOVD (R11), Y15, Y11", "c4 42 05 8c 1b"},
|
||||
{"VPMASKMOVD (R11), Y15, Y2", "c4 c2 05 8c 13"},
|
||||
{"VPMASKMOVD X11, X9, (BX)", "c4 62 31 8e 1b"},
|
||||
{"VPMASKMOVD X11, X9, (R11)", "c4 42 31 8e 1b"},
|
||||
{"VPMASKMOVD X2, X9, (BX)", "c4 e2 31 8e 13"},
|
||||
{"VPMASKMOVD X2, X9, (R11)", "c4 c2 31 8e 13"},
|
||||
{"VPMASKMOVD Y11, Y15, (BX)", "c4 62 05 8e 1b"},
|
||||
{"VPMASKMOVD Y11, Y15, (R11)", "c4 42 05 8e 1b"},
|
||||
{"VPMASKMOVD Y2, Y15, (BX)", "c4 e2 05 8e 13"},
|
||||
{"VPMASKMOVD Y2, Y15, (R11)", "c4 c2 05 8e 13"},
|
||||
{"VPMASKMOVQ (BX), X9, X11", "c4 62 b1 8c 1b"},
|
||||
{"VPMASKMOVQ (BX), X9, X2", "c4 e2 b1 8c 13"},
|
||||
{"VPMASKMOVQ (BX), Y15, Y11", "c4 62 85 8c 1b"},
|
||||
{"VPMASKMOVQ (BX), Y15, Y2", "c4 e2 85 8c 13"},
|
||||
{"VPMASKMOVQ (R11), X9, X11", "c4 42 b1 8c 1b"},
|
||||
{"VPMASKMOVQ (R11), X9, X2", "c4 c2 b1 8c 13"},
|
||||
{"VPMASKMOVQ (R11), Y15, Y11", "c4 42 85 8c 1b"},
|
||||
{"VPMASKMOVQ (R11), Y15, Y2", "c4 c2 85 8c 13"},
|
||||
{"VPMASKMOVQ X11, X9, (BX)", "c4 62 b1 8e 1b"},
|
||||
{"VPMASKMOVQ X11, X9, (R11)", "c4 42 b1 8e 1b"},
|
||||
{"VPMASKMOVQ X2, X9, (BX)", "c4 e2 b1 8e 13"},
|
||||
{"VPMASKMOVQ X2, X9, (R11)", "c4 c2 b1 8e 13"},
|
||||
{"VPMASKMOVQ Y11, Y15, (BX)", "c4 62 85 8e 1b"},
|
||||
{"VPMASKMOVQ Y11, Y15, (R11)", "c4 42 85 8e 1b"},
|
||||
{"VPMASKMOVQ Y2, Y15, (BX)", "c4 e2 85 8e 13"},
|
||||
{"VPMASKMOVQ Y2, Y15, (R11)", "c4 c2 85 8e 13"},
|
||||
{"VPSIGNB (BX), X9, X11", "c4 62 31 08 1b"},
|
||||
{"VPSIGNB (BX), X9, X2", "c4 e2 31 08 13"},
|
||||
{"VPSIGNB (BX), Y15, Y11", "c4 62 05 08 1b"},
|
||||
{"VPSIGNB (BX), Y15, Y2", "c4 e2 05 08 13"},
|
||||
{"VPSIGNB (R11), X9, X11", "c4 42 31 08 1b"},
|
||||
{"VPSIGNB (R11), X9, X2", "c4 c2 31 08 13"},
|
||||
{"VPSIGNB (R11), Y15, Y11", "c4 42 05 08 1b"},
|
||||
{"VPSIGNB (R11), Y15, Y2", "c4 c2 05 08 13"},
|
||||
{"VPSIGNB X11, X9, X11", "c4 42 31 08 db"},
|
||||
{"VPSIGNB X11, X9, X2", "c4 c2 31 08 d3"},
|
||||
{"VPSIGNB X2, X9, X11", "c4 62 31 08 da"},
|
||||
{"VPSIGNB X2, X9, X2", "c4 e2 31 08 d2"},
|
||||
{"VPSIGNB Y11, Y15, Y11", "c4 42 05 08 db"},
|
||||
{"VPSIGNB Y11, Y15, Y2", "c4 c2 05 08 d3"},
|
||||
{"VPSIGNB Y2, Y15, Y11", "c4 62 05 08 da"},
|
||||
{"VPSIGNB Y2, Y15, Y2", "c4 e2 05 08 d2"},
|
||||
{"VPSIGND (BX), X9, X11", "c4 62 31 0a 1b"},
|
||||
{"VPSIGND (BX), X9, X2", "c4 e2 31 0a 13"},
|
||||
{"VPSIGND (BX), Y15, Y11", "c4 62 05 0a 1b"},
|
||||
{"VPSIGND (BX), Y15, Y2", "c4 e2 05 0a 13"},
|
||||
{"VPSIGND (R11), X9, X11", "c4 42 31 0a 1b"},
|
||||
{"VPSIGND (R11), X9, X2", "c4 c2 31 0a 13"},
|
||||
{"VPSIGND (R11), Y15, Y11", "c4 42 05 0a 1b"},
|
||||
{"VPSIGND (R11), Y15, Y2", "c4 c2 05 0a 13"},
|
||||
{"VPSIGND X11, X9, X11", "c4 42 31 0a db"},
|
||||
{"VPSIGND X11, X9, X2", "c4 c2 31 0a d3"},
|
||||
{"VPSIGND X2, X9, X11", "c4 62 31 0a da"},
|
||||
{"VPSIGND X2, X9, X2", "c4 e2 31 0a d2"},
|
||||
{"VPSIGND Y11, Y15, Y11", "c4 42 05 0a db"},
|
||||
{"VPSIGND Y11, Y15, Y2", "c4 c2 05 0a d3"},
|
||||
{"VPSIGND Y2, Y15, Y11", "c4 62 05 0a da"},
|
||||
{"VPSIGND Y2, Y15, Y2", "c4 e2 05 0a d2"},
|
||||
{"VPSIGNW (BX), X9, X11", "c4 62 31 09 1b"},
|
||||
{"VPSIGNW (BX), X9, X2", "c4 e2 31 09 13"},
|
||||
{"VPSIGNW (BX), Y15, Y11", "c4 62 05 09 1b"},
|
||||
{"VPSIGNW (BX), Y15, Y2", "c4 e2 05 09 13"},
|
||||
{"VPSIGNW (R11), X9, X11", "c4 42 31 09 1b"},
|
||||
{"VPSIGNW (R11), X9, X2", "c4 c2 31 09 13"},
|
||||
{"VPSIGNW (R11), Y15, Y11", "c4 42 05 09 1b"},
|
||||
{"VPSIGNW (R11), Y15, Y2", "c4 c2 05 09 13"},
|
||||
{"VPSIGNW X11, X9, X11", "c4 42 31 09 db"},
|
||||
{"VPSIGNW X11, X9, X2", "c4 c2 31 09 d3"},
|
||||
{"VPSIGNW X2, X9, X11", "c4 62 31 09 da"},
|
||||
{"VPSIGNW X2, X9, X2", "c4 e2 31 09 d2"},
|
||||
{"VPSIGNW Y11, Y15, Y11", "c4 42 05 09 db"},
|
||||
{"VPSIGNW Y11, Y15, Y2", "c4 c2 05 09 d3"},
|
||||
{"VPSIGNW Y2, Y15, Y11", "c4 62 05 09 da"},
|
||||
{"VPSIGNW Y2, Y15, Y2", "c4 e2 05 09 d2"},
|
||||
{"VPSLLW $7, X11, X9", "c4 c1 31 71 f3 07"},
|
||||
{"VPSLLW $7, X2, X9", "c5 b1 71 f2 07"},
|
||||
{"VPSLLW $7, Y11, Y15", "c4 c1 05 71 f3 07"},
|
||||
{"VPSLLW $7, Y2, Y15", "c5 85 71 f2 07"},
|
||||
{"VPSLLW (BX), X9, X11", "c5 31 f1 1b"},
|
||||
{"VPSLLW (BX), X9, X2", "c5 b1 f1 13"},
|
||||
{"VPSLLW (BX), Y15, Y11", "c5 05 f1 1b"},
|
||||
{"VPSLLW (BX), Y15, Y2", "c5 85 f1 13"},
|
||||
{"VPSLLW (R11), X9, X11", "c4 41 31 f1 1b"},
|
||||
{"VPSLLW (R11), X9, X2", "c4 c1 31 f1 13"},
|
||||
{"VPSLLW (R11), Y15, Y11", "c4 41 05 f1 1b"},
|
||||
{"VPSLLW (R11), Y15, Y2", "c4 c1 05 f1 13"},
|
||||
{"VPSLLW X11, X9, X11", "c4 41 31 f1 db"},
|
||||
{"VPSLLW X11, X9, X2", "c4 c1 31 f1 d3"},
|
||||
{"VPSLLW X11, Y15, Y11", "c4 41 05 f1 db"},
|
||||
{"VPSLLW X11, Y15, Y2", "c4 c1 05 f1 d3"},
|
||||
{"VPSLLW X2, X9, X11", "c5 31 f1 da"},
|
||||
{"VPSLLW X2, X9, X2", "c5 b1 f1 d2"},
|
||||
{"VPSLLW X2, Y15, Y11", "c5 05 f1 da"},
|
||||
{"VPSLLW X2, Y15, Y2", "c5 85 f1 d2"},
|
||||
{"VPSRAW $7, X11, X9", "c4 c1 31 71 e3 07"},
|
||||
{"VPSRAW $7, X2, X9", "c5 b1 71 e2 07"},
|
||||
{"VPSRAW $7, Y11, Y15", "c4 c1 05 71 e3 07"},
|
||||
{"VPSRAW $7, Y2, Y15", "c5 85 71 e2 07"},
|
||||
{"VPSRAW (BX), X9, X11", "c5 31 e1 1b"},
|
||||
{"VPSRAW (BX), X9, X2", "c5 b1 e1 13"},
|
||||
{"VPSRAW (BX), Y15, Y11", "c5 05 e1 1b"},
|
||||
{"VPSRAW (BX), Y15, Y2", "c5 85 e1 13"},
|
||||
{"VPSRAW (R11), X9, X11", "c4 41 31 e1 1b"},
|
||||
{"VPSRAW (R11), X9, X2", "c4 c1 31 e1 13"},
|
||||
{"VPSRAW (R11), Y15, Y11", "c4 41 05 e1 1b"},
|
||||
{"VPSRAW (R11), Y15, Y2", "c4 c1 05 e1 13"},
|
||||
{"VPSRAW X11, X9, X11", "c4 41 31 e1 db"},
|
||||
{"VPSRAW X11, X9, X2", "c4 c1 31 e1 d3"},
|
||||
{"VPSRAW X11, Y15, Y11", "c4 41 05 e1 db"},
|
||||
{"VPSRAW X11, Y15, Y2", "c4 c1 05 e1 d3"},
|
||||
{"VPSRAW X2, X9, X11", "c5 31 e1 da"},
|
||||
{"VPSRAW X2, X9, X2", "c5 b1 e1 d2"},
|
||||
{"VPSRAW X2, Y15, Y11", "c5 05 e1 da"},
|
||||
{"VPSRAW X2, Y15, Y2", "c5 85 e1 d2"},
|
||||
{"VPSRLW $7, X11, X9", "c4 c1 31 71 d3 07"},
|
||||
{"VPSRLW $7, X2, X9", "c5 b1 71 d2 07"},
|
||||
{"VPSRLW $7, Y11, Y15", "c4 c1 05 71 d3 07"},
|
||||
{"VPSRLW $7, Y2, Y15", "c5 85 71 d2 07"},
|
||||
{"VPSRLW (BX), X9, X11", "c5 31 d1 1b"},
|
||||
{"VPSRLW (BX), X9, X2", "c5 b1 d1 13"},
|
||||
{"VPSRLW (BX), Y15, Y11", "c5 05 d1 1b"},
|
||||
{"VPSRLW (BX), Y15, Y2", "c5 85 d1 13"},
|
||||
{"VPSRLW (R11), X9, X11", "c4 41 31 d1 1b"},
|
||||
{"VPSRLW (R11), X9, X2", "c4 c1 31 d1 13"},
|
||||
{"VPSRLW (R11), Y15, Y11", "c4 41 05 d1 1b"},
|
||||
{"VPSRLW (R11), Y15, Y2", "c4 c1 05 d1 13"},
|
||||
{"VPSRLW X11, X9, X11", "c4 41 31 d1 db"},
|
||||
{"VPSRLW X11, X9, X2", "c4 c1 31 d1 d3"},
|
||||
{"VPSRLW X11, Y15, Y11", "c4 41 05 d1 db"},
|
||||
{"VPSRLW X11, Y15, Y2", "c4 c1 05 d1 d3"},
|
||||
{"VPSRLW X2, X9, X11", "c5 31 d1 da"},
|
||||
{"VPSRLW X2, X9, X2", "c5 b1 d1 d2"},
|
||||
{"VPSRLW X2, Y15, Y11", "c5 05 d1 da"},
|
||||
{"VPSRLW X2, Y15, Y2", "c5 85 d1 d2"},
|
||||
{"VRCPPS (BX), X11", "c5 78 53 1b"},
|
||||
{"VRCPPS (BX), X2", "c5 f8 53 13"},
|
||||
{"VRCPPS (BX), Y11", "c5 7c 53 1b"},
|
||||
{"VRCPPS (BX), Y2", "c5 fc 53 13"},
|
||||
{"VRCPPS (R11), X11", "c4 41 78 53 1b"},
|
||||
{"VRCPPS (R11), X2", "c4 c1 78 53 13"},
|
||||
{"VRCPPS (R11), Y11", "c4 41 7c 53 1b"},
|
||||
{"VRCPPS (R11), Y2", "c4 c1 7c 53 13"},
|
||||
{"VRCPPS X11, X11", "c4 41 78 53 db"},
|
||||
{"VRCPPS X11, X2", "c4 c1 78 53 d3"},
|
||||
{"VRCPPS X2, X11", "c5 78 53 da"},
|
||||
{"VRCPPS X2, X2", "c5 f8 53 d2"},
|
||||
{"VRCPPS Y11, Y11", "c4 41 7c 53 db"},
|
||||
{"VRCPPS Y11, Y2", "c4 c1 7c 53 d3"},
|
||||
{"VRCPPS Y2, Y11", "c5 7c 53 da"},
|
||||
{"VRCPPS Y2, Y2", "c5 fc 53 d2"},
|
||||
{"VRCPSS (BX), X9, X11", "c5 32 53 1b"},
|
||||
{"VRCPSS (BX), X9, X2", "c5 b2 53 13"},
|
||||
{"VRCPSS (R11), X9, X11", "c4 41 32 53 1b"},
|
||||
{"VRCPSS (R11), X9, X2", "c4 c1 32 53 13"},
|
||||
{"VRCPSS X11, X9, X11", "c4 41 32 53 db"},
|
||||
{"VRCPSS X11, X9, X2", "c4 c1 32 53 d3"},
|
||||
{"VRCPSS X2, X9, X11", "c5 32 53 da"},
|
||||
{"VRCPSS X2, X9, X2", "c5 b2 53 d2"},
|
||||
{"VROUNDSD $7, (BX), X9, X11", "c4 63 31 0b 1b 07"},
|
||||
{"VROUNDSD $7, (BX), X9, X2", "c4 e3 31 0b 13 07"},
|
||||
{"VROUNDSD $7, (R11), X9, X11", "c4 43 31 0b 1b 07"},
|
||||
{"VROUNDSD $7, (R11), X9, X2", "c4 c3 31 0b 13 07"},
|
||||
{"VROUNDSD $7, X11, X9, X11", "c4 43 31 0b db 07"},
|
||||
{"VROUNDSD $7, X11, X9, X2", "c4 c3 31 0b d3 07"},
|
||||
{"VROUNDSD $7, X2, X9, X11", "c4 63 31 0b da 07"},
|
||||
{"VROUNDSD $7, X2, X9, X2", "c4 e3 31 0b d2 07"},
|
||||
{"VROUNDSS $7, (BX), X9, X11", "c4 63 31 0a 1b 07"},
|
||||
{"VROUNDSS $7, (BX), X9, X2", "c4 e3 31 0a 13 07"},
|
||||
{"VROUNDSS $7, (R11), X9, X11", "c4 43 31 0a 1b 07"},
|
||||
{"VROUNDSS $7, (R11), X9, X2", "c4 c3 31 0a 13 07"},
|
||||
{"VROUNDSS $7, X11, X9, X11", "c4 43 31 0a db 07"},
|
||||
{"VROUNDSS $7, X11, X9, X2", "c4 c3 31 0a d3 07"},
|
||||
{"VROUNDSS $7, X2, X9, X11", "c4 63 31 0a da 07"},
|
||||
{"VROUNDSS $7, X2, X9, X2", "c4 e3 31 0a d2 07"},
|
||||
{"VRSQRTPS (BX), X11", "c5 78 52 1b"},
|
||||
{"VRSQRTPS (BX), X2", "c5 f8 52 13"},
|
||||
{"VRSQRTPS (BX), Y11", "c5 7c 52 1b"},
|
||||
{"VRSQRTPS (BX), Y2", "c5 fc 52 13"},
|
||||
{"VRSQRTPS (R11), X11", "c4 41 78 52 1b"},
|
||||
{"VRSQRTPS (R11), X2", "c4 c1 78 52 13"},
|
||||
{"VRSQRTPS (R11), Y11", "c4 41 7c 52 1b"},
|
||||
{"VRSQRTPS (R11), Y2", "c4 c1 7c 52 13"},
|
||||
{"VRSQRTPS X11, X11", "c4 41 78 52 db"},
|
||||
{"VRSQRTPS X11, X2", "c4 c1 78 52 d3"},
|
||||
{"VRSQRTPS X2, X11", "c5 78 52 da"},
|
||||
{"VRSQRTPS X2, X2", "c5 f8 52 d2"},
|
||||
{"VRSQRTPS Y11, Y11", "c4 41 7c 52 db"},
|
||||
{"VRSQRTPS Y11, Y2", "c4 c1 7c 52 d3"},
|
||||
{"VRSQRTPS Y2, Y11", "c5 7c 52 da"},
|
||||
{"VRSQRTPS Y2, Y2", "c5 fc 52 d2"},
|
||||
{"VRSQRTSS (BX), X9, X11", "c5 32 52 1b"},
|
||||
{"VRSQRTSS (BX), X9, X2", "c5 b2 52 13"},
|
||||
{"VRSQRTSS (R11), X9, X11", "c4 41 32 52 1b"},
|
||||
{"VRSQRTSS (R11), X9, X2", "c4 c1 32 52 13"},
|
||||
{"VRSQRTSS X11, X9, X11", "c4 41 32 52 db"},
|
||||
{"VRSQRTSS X11, X9, X2", "c4 c1 32 52 d3"},
|
||||
{"VRSQRTSS X2, X9, X11", "c5 32 52 da"},
|
||||
{"VRSQRTSS X2, X9, X2", "c5 b2 52 d2"},
|
||||
{"VSTMXCSR (BX)", "c5 f8 ae 1b"},
|
||||
{"VSTMXCSR (R11)", "c4 c1 78 ae 1b"},
|
||||
{"VTESTPD (BX), X11", "c4 62 79 0f 1b"},
|
||||
{"VTESTPD (BX), X2", "c4 e2 79 0f 13"},
|
||||
{"VTESTPD (BX), Y11", "c4 62 7d 0f 1b"},
|
||||
{"VTESTPD (BX), Y2", "c4 e2 7d 0f 13"},
|
||||
{"VTESTPD (R11), X11", "c4 42 79 0f 1b"},
|
||||
{"VTESTPD (R11), X2", "c4 c2 79 0f 13"},
|
||||
{"VTESTPD (R11), Y11", "c4 42 7d 0f 1b"},
|
||||
{"VTESTPD (R11), Y2", "c4 c2 7d 0f 13"},
|
||||
{"VTESTPD X11, X11", "c4 42 79 0f db"},
|
||||
{"VTESTPD X11, X2", "c4 c2 79 0f d3"},
|
||||
{"VTESTPD X2, X11", "c4 62 79 0f da"},
|
||||
{"VTESTPD X2, X2", "c4 e2 79 0f d2"},
|
||||
{"VTESTPD Y11, Y11", "c4 42 7d 0f db"},
|
||||
{"VTESTPD Y11, Y2", "c4 c2 7d 0f d3"},
|
||||
{"VTESTPD Y2, Y11", "c4 62 7d 0f da"},
|
||||
{"VTESTPD Y2, Y2", "c4 e2 7d 0f d2"},
|
||||
{"VTESTPS (BX), X11", "c4 62 79 0e 1b"},
|
||||
{"VTESTPS (BX), X2", "c4 e2 79 0e 13"},
|
||||
{"VTESTPS (BX), Y11", "c4 62 7d 0e 1b"},
|
||||
{"VTESTPS (BX), Y2", "c4 e2 7d 0e 13"},
|
||||
{"VTESTPS (R11), X11", "c4 42 79 0e 1b"},
|
||||
{"VTESTPS (R11), X2", "c4 c2 79 0e 13"},
|
||||
{"VTESTPS (R11), Y11", "c4 42 7d 0e 1b"},
|
||||
{"VTESTPS (R11), Y2", "c4 c2 7d 0e 13"},
|
||||
{"VTESTPS X11, X11", "c4 42 79 0e db"},
|
||||
{"VTESTPS X11, X2", "c4 c2 79 0e d3"},
|
||||
{"VTESTPS X2, X11", "c4 62 79 0e da"},
|
||||
{"VTESTPS X2, X2", "c4 e2 79 0e d2"},
|
||||
{"VTESTPS Y11, Y11", "c4 42 7d 0e db"},
|
||||
{"VTESTPS Y11, Y2", "c4 c2 7d 0e d3"},
|
||||
{"VTESTPS Y2, Y11", "c4 62 7d 0e da"},
|
||||
{"VTESTPS Y2, Y2", "c4 e2 7d 0e d2"},
|
||||
}
|
||||
|
||||
// TestAmd64VexCorpus assembles every corpus line and requires the same bytes
|
||||
// go tool asm emits for it.
|
||||
func TestAmd64VexCorpus(t *testing.T) {
|
||||
for _, tc := range amd64VexCorpus {
|
||||
fn := firstText(t, "TEXT ·p(SB), 4, $0\n\t"+tc.line+"\n")
|
||||
code, _, err := Assemble(fn)
|
||||
if err != nil {
|
||||
t.Errorf("%s: %v", tc.line, err)
|
||||
continue
|
||||
}
|
||||
if got := hexBytes(code); got != tc.want {
|
||||
t.Errorf("%s: got %s, want %s", tc.line, got, tc.want)
|
||||
}
|
||||
}
|
||||
}
|
||||
+1
-1
@@ -921,7 +921,7 @@ func evexRequired(upper string, ops []Operand) bool {
|
||||
// The dual-shape moves pick their VEX form by operand count, so
|
||||
// they are not EVEX-only either.
|
||||
switch upper {
|
||||
case "VMOVHPD", "VMOVLPD":
|
||||
case "VMOVHPD", "VMOVLPD", "VMOVHPS", "VMOVLPS":
|
||||
default:
|
||||
return true // EVEX-only mnemonic
|
||||
}
|
||||
|
||||
+208
-24
@@ -80,6 +80,13 @@ const (
|
||||
// dst` (VPBLENDVB): ModRM.reg = dst (op3), VEX.vvvv = src1 (op2),
|
||||
// ModRM.rm = src2 (op1) and the mask register in the /is4 byte (op0).
|
||||
vexBlend4
|
||||
// vexNDS3Dst is the destination-first NDS form `OP dst, src1, src2`
|
||||
// (VMASKMOVPS, VPMASKMOVD): ModRM.reg = dst (op0), VEX.vvvv = the mask
|
||||
// source (op1), ModRM.rm = memory (op2).
|
||||
vexNDS3Dst
|
||||
// vexRMOpDigit is the two-operand /digit form over memory (VLDMXCSR,
|
||||
// VSTMXCSR): ModRM.reg = /digit, ModRM.rm = the memory operand.
|
||||
vexRMOpDigit
|
||||
)
|
||||
|
||||
// vexSpec describes one VEX instruction's encoding parameters.
|
||||
@@ -347,7 +354,6 @@ var vexTable = map[string]vexSpec{
|
||||
"VPSRLW": {1, 0x71, 0, 1, 2, vexShiftImm},
|
||||
"VPSRAW": {1, 0x71, 0, 1, 4, vexShiftImm},
|
||||
"VPSLLW": {1, 0x71, 0, 1, 6, vexShiftImm},
|
||||
|
||||
// VEX.F2.0F, packed double to packed dword conversions, truncating and
|
||||
// non-truncating. The destination is always XMM; the X/Y spellings fix
|
||||
// the source length (XMM/YMM), and VEX.L follows it, see vexSrcLen.
|
||||
@@ -477,6 +483,82 @@ var vexTable = map[string]vexSpec{
|
||||
// VEX.128.0F.F3/F2.W0, the high/low word shuffles ($imm, src, dst).
|
||||
"VPSHUFHW": {1, 0x70, 0, 2, -1, vexImmRM},
|
||||
"VPSHUFLW": {1, 0x70, 0, 3, -1, vexImmRM},
|
||||
|
||||
// --- the corpus families from amd64enc.s: the SSE3 horizontal and
|
||||
// add-subtract pairs, the SSSE3 sign and horizontal integers, the AVX
|
||||
// reciprocity and test pairs, the masked and non-temporal oddities ---
|
||||
|
||||
// VEX.128/256, the horizontal and add-subtract float pairs: PD carries
|
||||
// 66, PS carries F2 (0F 7C/7D and 0F D0).
|
||||
"VHADDPD": {1, 0x7C, 0, 1, -1, vexNDS3},
|
||||
"VHADDPS": {1, 0x7C, 0, 3, -1, vexNDS3},
|
||||
"VHSUBPD": {1, 0x7D, 0, 1, -1, vexNDS3},
|
||||
"VHSUBPS": {1, 0x7D, 0, 3, -1, vexNDS3},
|
||||
"VADDSUBPD": {1, 0xD0, 0, 1, -1, vexNDS3},
|
||||
"VADDSUBPS": {1, 0xD0, 0, 3, -1, vexNDS3},
|
||||
// VEX.128/256.0F38.W0, the SSSE3 horizontal integer family and the sign
|
||||
// controls, all NDS over 66.
|
||||
"VPHADDW": {2, 0x01, 0, 1, -1, vexNDS3},
|
||||
"VPHADDD": {2, 0x02, 0, 1, -1, vexNDS3},
|
||||
"VPHADDSW": {2, 0x03, 0, 1, -1, vexNDS3},
|
||||
"VPHSUBW": {2, 0x05, 0, 1, -1, vexNDS3},
|
||||
"VPHSUBD": {2, 0x06, 0, 1, -1, vexNDS3},
|
||||
"VPHSUBSW": {2, 0x07, 0, 1, -1, vexNDS3},
|
||||
"VPSIGNB": {2, 0x08, 0, 1, -1, vexNDS3},
|
||||
"VPSIGNW": {2, 0x09, 0, 1, -1, vexNDS3},
|
||||
"VPSIGND": {2, 0x0A, 0, 1, -1, vexNDS3},
|
||||
// VEX.128/256.0F38.W0, the masked loads/stores whose mask source rides
|
||||
// vvvv, memory in r/m: the Plan 9 order puts the destination first
|
||||
// (dst, mask, src), its own form below. VMOVHLPS is the plain NDS
|
||||
// register move under 0F 12, and the test pair and the AES inverse cube
|
||||
// root are two-operand.
|
||||
"VMOVHLPS": {1, 0x12, 0, 0, -1, vexNDS3},
|
||||
"VMASKMOVPD": {2, 0x2F, 0, 1, -1, vexNDS3Dst},
|
||||
"VMASKMOVPS": {2, 0x2E, 0, 1, -1, vexNDS3Dst},
|
||||
"VPMASKMOVD": {2, 0x8E, 0, 1, -1, vexNDS3Dst},
|
||||
"VPMASKMOVQ": {2, 0x8E, 1, 1, -1, vexNDS3Dst},
|
||||
"VTESTPD": {2, 0x0F, 0, 1, -1, vexRM},
|
||||
"VTESTPS": {2, 0x0E, 0, 1, -1, vexRM},
|
||||
"VAESIMC": {2, 0xDB, 0, 1, -1, vexRM},
|
||||
"VPHMINPOSUW": {2, 0x41, 0, 1, -1, vexRM},
|
||||
// VEX.128/256.66.0F38.W0, broadcast a 128-bit lane into a YMM.
|
||||
"VBROADCASTF128": {2, 0x1A, 0, 1, -1, vexRM},
|
||||
// VEX.128/256, the reciprocal square root estimates: PS bare (two-op
|
||||
// RM), SS F3-prefixed NDS (the scalar preserved source).
|
||||
"VRCPPS": {1, 0x53, 0, 0, -1, vexRM},
|
||||
"VRSQRTPS": {1, 0x52, 0, 0, -1, vexRM},
|
||||
"VRCPSS": {1, 0x53, 0, 2, -1, vexNDS3},
|
||||
"VRSQRTSS": {1, 0x52, 0, 2, -1, vexNDS3},
|
||||
// VEX.128/256.F2.0F.WIG, the unaligned load with cache hints and the
|
||||
// duplicated low double, F3 for the singles replica.
|
||||
"VLDDQU": {1, 0xF0, 0, 3, -1, vexRM},
|
||||
// VEX.128/256.66.0F, the move-mask twin of VMOVMSKPS and the masked
|
||||
// store over the integer bank.
|
||||
"VMOVMSKPD": {1, 0x50, 0, 1, -1, vexRM},
|
||||
"VMASKMOVDQU": {1, 0xF7, 0, 1, -1, vexRM},
|
||||
// VEX.128/256.0F3A.W0, the imm8 tail the legacy set carries and its
|
||||
// variable blends over the is4 byte.
|
||||
"VBLENDPD": {3, 0x0D, 0, 1, -1, vexNDS3Imm},
|
||||
"VBLENDPS": {3, 0x0C, 0, 1, -1, vexNDS3Imm},
|
||||
"VPBLENDW": {3, 0x0E, 0, 1, -1, vexNDS3Imm},
|
||||
"VDPPD": {3, 0x41, 0, 1, -1, vexNDS3Imm},
|
||||
"VDPPS": {3, 0x40, 0, 1, -1, vexNDS3Imm},
|
||||
"VINSERTPS": {3, 0x21, 0, 1, -1, vexNDS3Imm},
|
||||
"VMPSADBW": {3, 0x42, 0, 1, -1, vexNDS3Imm},
|
||||
"VROUNDSD": {3, 0x0B, 0, 1, -1, vexNDS3Imm},
|
||||
"VROUNDSS": {3, 0x0A, 0, 1, -1, vexNDS3Imm},
|
||||
"VPINSRB": {3, 0x20, 0, 1, -1, vexNDS3Imm},
|
||||
// VEX.128.66.0F3A.W0, the four-operand variable blends over the /is4
|
||||
// byte (the mask rides is4[7:4], the raw register number times 16).
|
||||
"VBLENDVPS": {3, 0x4A, 0, 1, -1, vexBlend4},
|
||||
"VBLENDVPD": {3, 0x4B, 0, 1, -1, vexBlend4},
|
||||
// VEX.256.66.0F3A.W0, the lane insert, and the GPR insert the legacy
|
||||
// set spells: VPINSRW rides plain 0F C4 with 66.
|
||||
"VINSERTF128": {3, 0x18, 0, 1, -1, vexNDS3Imm},
|
||||
"VPINSRW": {1, 0xC4, 0, 1, -1, vexNDS3Imm},
|
||||
// VEX.128/256.0F, the MXCSR accessors, memory alone, no prefix.
|
||||
"VLDMXCSR": {1, 0xAE, 0, 0, 2, vexRMOpDigit},
|
||||
"VSTMXCSR": {1, 0xAE, 0, 0, 3, vexRMOpDigit},
|
||||
}
|
||||
|
||||
// vexSrcLen maps a source-length conversion mnemonic (the X/Y spellings of
|
||||
@@ -498,9 +580,20 @@ var vexSrcLen = map[string]int{
|
||||
var vexVarShift = map[string]byte{
|
||||
"VPSLLD": 0xF2,
|
||||
"VPSLLQ": 0xF3,
|
||||
"VPSLLW": 0xF1,
|
||||
"VPSRAD": 0xE2,
|
||||
"VPSRAW": 0xE1,
|
||||
"VPSRLD": 0xD2,
|
||||
"VPSRLQ": 0xD3,
|
||||
"VPSRLW": 0xD1,
|
||||
}
|
||||
|
||||
// vexPermilReg maps the VPERMIL register-control spellings to their 0F38
|
||||
// NDS opcodes: the control rides vvvv, the immediate form the main table
|
||||
// carries never enters this path.
|
||||
var vexPermilReg = map[string]vexSpec{
|
||||
"VPERMILPS": {2, 0x0C, 0, 1, -1, vexNDS3},
|
||||
"VPERMILPD": {2, 0x0D, 0, 1, -1, vexNDS3},
|
||||
}
|
||||
|
||||
// vexMoveSpec describes a VEX move, which takes different opcodes (and
|
||||
@@ -533,10 +626,10 @@ var vexMoveTable = map[string]vexMoveSpec{
|
||||
"VMOVD": {1, 1, 0x6E, 0x7E, 0, 0, 0, 0, false, true, true},
|
||||
// VMOVQ, 66 6E W1 (r/m→xmm), 66 7E W1 (xmm→r/m), 66 D6 W0 (xmm→xmm).
|
||||
"VMOVQ": {1, 1, 0x6E, 0x7E, 1, 1, 0xD6, 0, true, true, true},
|
||||
// VEX.128.F2.0F.WIG, scalar double move, memory operands only (the
|
||||
// register form takes three operands and is not supported yet).
|
||||
// VEX.128.F2.0F.WIG, scalar double move: two operands move against
|
||||
// memory, three operands the NDS store-opcode form (see encodeVexMove).
|
||||
"VMOVSD": {1, 3, 0x10, 0x11, 0, 0, 0, 0, false, false, true},
|
||||
// VEX.128.F3.0F.WIG, scalar single move, memory operands only.
|
||||
// VEX.128.F3.0F.WIG, scalar single move, the same two shapes.
|
||||
"VMOVSS": {1, 2, 0x10, 0x11, 0, 0, 0, 0, false, false, true},
|
||||
// VEX.128/256, aligned packed moves.
|
||||
"VMOVAPS": {1, 0, 0x28, 0x29, 0, 0, 0, 0, true, false, false},
|
||||
@@ -551,10 +644,10 @@ func isVex(mnemUpper string) bool {
|
||||
if _, ok := vexMoveTable[mnemUpper]; ok {
|
||||
return true
|
||||
}
|
||||
// The dual-shape moves (VMOVHPD/VMOVLPD) pick their VEX form by operand
|
||||
// count in encodeVex.
|
||||
// The dual-shape moves (VMOVHPD/VMOVLPD and the single-precision twins)
|
||||
// pick their VEX form by operand count in encodeVex.
|
||||
switch mnemUpper {
|
||||
case "VMOVHPD", "VMOVLPD":
|
||||
case "VMOVHPD", "VMOVLPD", "VMOVHPS", "VMOVLPS":
|
||||
return true
|
||||
}
|
||||
return false
|
||||
@@ -591,19 +684,30 @@ func (e *enc) encodeVex(mnemUpper string, ops []Operand) error {
|
||||
return e.encodeVexNDS3(vexSpec{mapSel: 1, opcode: op, pp: 1, opdigit: -1, form: vexNDS3}, ops)
|
||||
}
|
||||
}
|
||||
// The VPERMIL register-control form: the control rides vvvv (an NDS
|
||||
// encoding under 0F38), the immediate form the main table carries.
|
||||
if spec, ok := vexPermilReg[mnemUpper]; ok && len(ops) == 3 {
|
||||
if _, isImm := ops[0].(Imm); !isImm {
|
||||
return e.encodeVexNDS3(spec, ops)
|
||||
}
|
||||
}
|
||||
// The high/low double moves split by operand count: three operands
|
||||
// load-and-insert (mem, src, dst, an NDS form), two store (xmm, m64,
|
||||
// the reversed store layout).
|
||||
if mnemUpper == "VMOVHPD" || mnemUpper == "VMOVLPD" {
|
||||
if mnemUpper == "VMOVHPD" || mnemUpper == "VMOVLPD" || mnemUpper == "VMOVHPS" || mnemUpper == "VMOVLPS" {
|
||||
loadOp, storeOp := byte(0x16), byte(0x17)
|
||||
if mnemUpper == "VMOVLPD" {
|
||||
if mnemUpper == "VMOVLPD" || mnemUpper == "VMOVLPS" {
|
||||
loadOp, storeOp = 0x12, 0x13
|
||||
}
|
||||
pp := 1
|
||||
if mnemUpper == "VMOVHPS" || mnemUpper == "VMOVLPS" {
|
||||
pp = 0
|
||||
}
|
||||
switch len(ops) {
|
||||
case 3:
|
||||
return e.encodeVexNDS3(vexSpec{mapSel: 1, opcode: loadOp, w: 0, pp: 1, opdigit: -1, form: vexNDS3}, ops)
|
||||
return e.encodeVexNDS3(vexSpec{mapSel: 1, opcode: loadOp, w: 0, pp: pp, opdigit: -1, form: vexNDS3}, ops)
|
||||
case 2:
|
||||
return e.encodeVexRMRev(vexSpec{mapSel: 1, opcode: storeOp, w: 0, pp: 1, opdigit: -1, form: vexRMRev}, ops)
|
||||
return e.encodeVexRMRev(vexSpec{mapSel: 1, opcode: storeOp, w: 0, pp: pp, opdigit: -1, form: vexRMRev}, ops)
|
||||
}
|
||||
return fmt.Errorf("%s expects 2 or 3 operands, got %d", mnemUpper, len(ops))
|
||||
}
|
||||
@@ -641,10 +745,62 @@ func (e *enc) encodeVex(mnemUpper string, ops []Operand) error {
|
||||
return e.encodeVexCountGPR(spec, ops)
|
||||
case vexRMRev:
|
||||
return e.encodeVexRMRev(spec, ops)
|
||||
case vexNDS3Dst:
|
||||
return e.encodeVexNDS3Dst(spec, ops)
|
||||
case vexRMOpDigit:
|
||||
return e.encodeVexRMOpDigit(mnemUpper, spec, ops)
|
||||
}
|
||||
return fmt.Errorf("unhandled VEX form for %s", mnemUpper)
|
||||
}
|
||||
|
||||
// encodeVexNDS3Dst encodes the destination-first NDS forms (VMASKMOVPS,
|
||||
// VPMASKMOVD): ModRM.reg = the vector register, VEX.vvvv = the mask source,
|
||||
// ModRM.rm = memory. Both directions exist: (dst, mask, mem) stores under
|
||||
// the table opcode, (mem, mask, dst) loads under its twin two lower (the
|
||||
// opcode rows pair 2E/2C, 2F/2D and 8E/8C).
|
||||
func (e *enc) encodeVexNDS3Dst(spec vexSpec, ops []Operand) error {
|
||||
if len(ops) != 3 {
|
||||
return fmt.Errorf("VEX NDS instruction expects 3 operands, got %d", len(ops))
|
||||
}
|
||||
opcode := spec.opcode
|
||||
first, second, third := ops[0], ops[1], ops[2]
|
||||
if isX86Mem(first) {
|
||||
first, third = third, first
|
||||
opcode -= 2
|
||||
}
|
||||
dstReg, ok := first.(Reg)
|
||||
if !ok || !dstReg.isVec() {
|
||||
return fmt.Errorf("VEX destination must be a vector register")
|
||||
}
|
||||
vvvvReg, ok := second.(Reg)
|
||||
if !ok || !vvvvReg.isVec() {
|
||||
return fmt.Errorf("VEX mask source must be a vector register")
|
||||
}
|
||||
if !vecOrMem(third) {
|
||||
return fmt.Errorf("VEX memory source expected")
|
||||
}
|
||||
regField := dstReg.idx & 7
|
||||
rBit := 0
|
||||
if dstReg.idx >= 8 {
|
||||
rBit = 1
|
||||
}
|
||||
enc := spec
|
||||
enc.opcode = opcode
|
||||
return e.emitVexFields(enc, dstReg.vecLenBit(), regField, rBit, 15-(vvvvReg.idx&15), third)
|
||||
}
|
||||
|
||||
// encodeVexRMOpDigit encodes the MXCSR accessors: the single memory operand
|
||||
// rides r/m under the fixed /digit, the way the legacy 0F AE pair does.
|
||||
func (e *enc) encodeVexRMOpDigit(mnem string, spec vexSpec, ops []Operand) error {
|
||||
if len(ops) != 1 {
|
||||
return fmt.Errorf("%s expects 1 memory operand, got %d", mnem, len(ops))
|
||||
}
|
||||
if !isX86Mem(ops[0]) {
|
||||
return fmt.Errorf("%s requires a memory operand", mnem)
|
||||
}
|
||||
return e.emitVexFields(spec, 0, spec.opdigit, 0, 15, ops[0])
|
||||
}
|
||||
|
||||
// encodeVexNDS3 encodes the three-operand NDS form: OP src2, src1, dst.
|
||||
func (e *enc) encodeVexNDS3(spec vexSpec, ops []Operand) error {
|
||||
if len(ops) != 3 {
|
||||
@@ -970,7 +1126,8 @@ func (e *enc) encodeVexRMOpGPR(spec vexSpec, ops []Operand) error {
|
||||
|
||||
// encodeVexCountGPR encodes the three-operand count form over general-purpose
|
||||
// registers (SHLX, SHRX, SARX, BEXTR, BZHI): OP src, count, dst with
|
||||
// VEX.vvvv = src (op0), ModRM.rm = count (op1), ModRM.reg = dst (op2).
|
||||
// VEX.vvvv = src (op0), ModRM.rm = count (op1, register or memory),
|
||||
// ModRM.reg = dst (op2).
|
||||
func (e *enc) encodeVexCountGPR(spec vexSpec, ops []Operand) error {
|
||||
if len(ops) != 3 {
|
||||
return fmt.Errorf("VEX count instruction expects 3 operands, got %d", len(ops))
|
||||
@@ -980,9 +1137,13 @@ func (e *enc) encodeVexCountGPR(spec vexSpec, ops []Operand) error {
|
||||
if !ok || dstReg.isVec() {
|
||||
return fmt.Errorf("VEX destination must be a general-purpose register")
|
||||
}
|
||||
countReg, ok := count.(Reg)
|
||||
if !ok || countReg.isVec() {
|
||||
return fmt.Errorf("VEX count operand must be a general-purpose register")
|
||||
switch count.(type) {
|
||||
case Reg, Mem, sbMem:
|
||||
default:
|
||||
return fmt.Errorf("VEX count operand must be a general-purpose register or memory")
|
||||
}
|
||||
if r, ok := count.(Reg); ok && r.isVec() {
|
||||
return fmt.Errorf("VEX count operand must be a general-purpose register or memory")
|
||||
}
|
||||
srcReg, ok := src.(Reg)
|
||||
if !ok || srcReg.isVec() {
|
||||
@@ -1050,17 +1211,18 @@ func (e *enc) encodeVexExtractGPR(spec vexSpec, ops []Operand) error {
|
||||
return nil
|
||||
}
|
||||
|
||||
// encodeVexBlend4 encodes the four-operand variable blend (VPBLENDVB):
|
||||
// OP mask, src2, src1, dst with ModRM.reg = dst, VEX.vvvv = src1, r/m =
|
||||
// src2 and the mask XMM register in the trailing /is4 byte.
|
||||
// encodeVexBlend4 encodes the four-operand variable blend (VPBLENDVB and the
|
||||
// VBLENDV pair): OP mask, src2, src1, dst with ModRM.reg = dst, VEX.vvvv =
|
||||
// src1, r/m = src2 and the mask register in the trailing /is4 byte, whose
|
||||
// high nibble carries the mask's register number raw.
|
||||
func (e *enc) encodeVexBlend4(spec vexSpec, ops []Operand) error {
|
||||
if len(ops) != 4 {
|
||||
return fmt.Errorf("blend expects 4 operands (mask, src2, src1, dst), got %d", len(ops))
|
||||
}
|
||||
mask, src2, src1, dst := ops[0], ops[1], ops[2], ops[3]
|
||||
maskReg, ok := mask.(Reg)
|
||||
if !ok || !maskReg.isVec() || maskReg.size != 16 {
|
||||
return fmt.Errorf("blend mask must be an XMM register")
|
||||
if !ok || !maskReg.isVec() {
|
||||
return fmt.Errorf("blend mask must be a vector register")
|
||||
}
|
||||
vvvvReg, ok := src1.(Reg)
|
||||
if !ok || !vvvvReg.isVec() {
|
||||
@@ -1077,17 +1239,39 @@ func (e *enc) encodeVexBlend4(spec vexSpec, ops []Operand) error {
|
||||
if err := e.emitVexFields(spec, dstReg.vecLenBit(), dstReg.idx&7, rBit, 15-(vvvvReg.idx&15), src2); err != nil {
|
||||
return err
|
||||
}
|
||||
// The /is4 byte names the mask register: bits [3:0] its low nibble,
|
||||
// bit 7 the fourth register bit (X8-X15).
|
||||
e.out = append(e.out, byte(maskReg.idx&7)|byte((maskReg.idx&8)<<4))
|
||||
// The /is4 byte names the mask register: its number in the high nibble,
|
||||
// the layout the Go assembler and the hardware agree on for X0-X15.
|
||||
e.out = append(e.out, byte(maskReg.idx)<<4)
|
||||
return nil
|
||||
}
|
||||
|
||||
// encodeVexMove encodes a two-operand move (VMOVDQU, VMOVUPD, VMOVD, VMOVQ,
|
||||
// VMOVSD), picking the direction-specific opcode and VEX.W. A vector→vector
|
||||
// move uses the store-form layout (reg = source, rm = destination), matching
|
||||
// the Go assembler.
|
||||
// the Go assembler. The scalar moves (VMOVSD, VMOVSS) also carry a
|
||||
// three-operand form, which the toolchain encodes with the store opcode:
|
||||
// reg = the Plan 9 first operand, vvvv = the second, rm = the third.
|
||||
func (e *enc) encodeVexMove(mnem string, ms vexMoveSpec, ops []Operand) error {
|
||||
if len(ops) == 3 {
|
||||
if !ms.xmmOnly {
|
||||
return fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
op0, ok0 := ops[0].(Reg)
|
||||
op1, ok1 := ops[1].(Reg)
|
||||
op2, ok2 := ops[2].(Reg)
|
||||
if !ok0 || !ok1 || !ok2 || !op0.isVec() || !op1.isVec() || !op2.isVec() {
|
||||
return fmt.Errorf("%s three-operand form takes three vector registers", mnem)
|
||||
}
|
||||
if ms.xmmOnly && (op0.size != 16 || op1.size != 16 || op2.size != 16) {
|
||||
return fmt.Errorf("%s operates on XMM registers only", mnem)
|
||||
}
|
||||
rBit := 0
|
||||
if op0.idx >= 8 {
|
||||
rBit = 1
|
||||
}
|
||||
spec := vexSpec{mapSel: ms.mapSel, opcode: ms.store, w: ms.storeW, pp: ms.pp, opdigit: -1}
|
||||
return e.emitVexFields(spec, 0, op0.idx&7, rBit, 15-(op1.idx&15), op2)
|
||||
}
|
||||
if len(ops) != 2 {
|
||||
return fmt.Errorf("VEX move expects 2 operands, got %d", len(ops))
|
||||
}
|
||||
|
||||
@@ -76,6 +76,9 @@ var x86asmUnrecognised = map[string]bool{
|
||||
"SHLXQ": true,
|
||||
"SHRXL": true,
|
||||
"SHRXQ": true,
|
||||
// The register-only half move the decoder's AVX tables lack; its
|
||||
// bytes are pinned against go tool asm through the corpus test.
|
||||
"VMOVHLPS": true,
|
||||
}
|
||||
|
||||
// TestVexNDS3 encodes `mnem Y0, Y1, Y2` for every three-operand NDS
|
||||
|
||||
Reference in new issue
Block a user