feat(arch): the SVE2.1 pairwise and quadword-reduction families
Assisted-by: GLM 5.3 Flash
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@@ -2597,8 +2597,19 @@ func (in ExtInstr) encodeQuadReduce(ops []ExtOperand) ([]byte, error) {
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if err := in.barePredicate(pg, 2, 0, 7); err != nil {
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return nil, err
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}
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if err := in.simdReg(vn, 3); err != nil {
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return nil, err
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if vn.Kind != ExtVReg {
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return nil, fmt.Errorf("%s: operand 3 wants a SIMD register, got %s",
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in.Name, vn.Kind)
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}
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if vn.Reg < 0 || vn.Reg > 31 {
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return nil, fmt.Errorf("%s: operand 3 is V%d, outside V0-V31", in.Name, vn.Reg)
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}
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if vn.Qual != ExtQualNone {
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return nil, fmt.Errorf("%s: operand 3 takes no qualifier, got %q", in.Name, vn.Qual)
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}
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if vn.Arr == ExtArrNone {
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return nil, fmt.Errorf("%s: operand 3 carries no quadword suffix, want .B16, .H8, .S4 or .D2",
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in.Name)
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}
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if vn.Arr != zdn.Arr {
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return nil, fmt.Errorf("%s: operand 3 carries arrangement %s, want %s",
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@@ -3189,6 +3200,65 @@ var arm64Extensions = []ExtInstr{
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Word: 0x45207400, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZSUBHNT; inst_gen.go + arm64sveenc.s"},
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// --- the SVE2.1 pairwise and quadword-reduction families ------------------
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//
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// ADDP sums the halves of two vectors pairwise under a governing
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// predicate, ADDPT the top halves of 128-bit pairs (predicated and
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// unpredicated), and the QV class reduces a quadword vector into a
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// scalable accumulator. The QV vector operand carries the counted
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// quadword spelling the corpus writes, V5.S4 and friends. Provenance
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// as above: the toolchain encoding table and its generated corpus, both
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// produced from Arm's official ISA description, and the golden test
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// pins every corpus line of each class.
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{Name: "ZADDP", Summary: "Add vector halves pairwise, merging",
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Word: 0x4411a000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZADDP; inst_gen.go + arm64sveenc.s"},
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{Name: "ZADDPT", Summary: "Add the top halves of 128-bit pairs, merging",
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Word: 0x04c40000, Form: ExtFormZPredicatedSource, Arr: ExtArrD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZADDPT; inst_gen.go + arm64sveenc.s"},
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{Name: "ZADDPT", Summary: "Add the top halves of 128-bit pairs, unpredicated",
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Word: 0x04e00800, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZADDPT; inst_gen.go + arm64sveenc.s"},
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{Name: "ZADDQV", Summary: "Add a quadword vector into a scalable accumulator",
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Word: 0x04052000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZADDQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZANDQV", Summary: "And a quadword vector into a scalable accumulator",
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Word: 0x041e2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZANDQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZEORQV", Summary: "Exclusive-or a quadword vector into a scalable accumulator",
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Word: 0x041d2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZEORQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZFADDQV", Summary: "Add floating-point a quadword vector into a scalable accumulator",
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Word: 0x6410a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZFADDQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZFMAXNMQV", Summary: "Maximum number of a quadword vector into a scalable accumulator",
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Word: 0x6414a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZFMAXNMQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZFMAXQV", Summary: "Maximum of a quadword vector into a scalable accumulator",
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Word: 0x6416a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZFMAXQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZFMINNMQV", Summary: "Minimum number of a quadword vector into a scalable accumulator",
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Word: 0x6415a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZFMINNMQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZFMINQV", Summary: "Minimum of a quadword vector into a scalable accumulator",
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Word: 0x6417a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZFMINQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZORQV", Summary: "Or a quadword vector into a scalable accumulator",
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Word: 0x041c2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZORQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZSMAXQV", Summary: "Signed maximum of a quadword vector into a scalable accumulator",
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Word: 0x040c2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZSMAXQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZSMINQV", Summary: "Signed minimum of a quadword vector into a scalable accumulator",
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Word: 0x040e2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZSMINQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZUMAXQV", Summary: "Unsigned maximum of a quadword vector into a scalable accumulator",
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Word: 0x040d2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZUMAXQV; inst_gen.go + arm64sveenc.s"},
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{Name: "ZUMINQV", Summary: "Unsigned minimum of a quadword vector into a scalable accumulator",
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Word: 0x040f2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
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Ref: "ARM DDI 0487J SVE2.1: ZUMINQV; inst_gen.go + arm64sveenc.s"},
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// --- the SVE2 crypto family ----------------------------------------------
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//
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// The multi-precision carry steps (ADCLB, ADCLT, SBCLB, SBCLT), the SHA3
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+70
-11
@@ -1348,41 +1348,100 @@ func TestArm64ExtStage4Golden(t *testing.T) {
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name string
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mnem string
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form ExtForm
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qual ExtQualifier
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arr ExtArrangement
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ops []ExtOperand
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want uint32
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}{
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{"ZADDHNB Z22.S, Z10.S, Z8.H", "ZADDHNB", ExtFormNarrow,
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{"ZADDHNB Z22.S, Z10.S, Z8.H", "ZADDHNB", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b66148},
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{"ZADDHNT Z22.S, Z10.S, Z8.H", "ZADDHNT", ExtFormNarrow,
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{"ZADDHNT Z22.S, Z10.S, Z8.H", "ZADDHNT", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b66548},
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{"ZRADDHNB Z22.S, Z10.S, Z8.H", "ZRADDHNB", ExtFormNarrow,
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{"ZRADDHNB Z22.S, Z10.S, Z8.H", "ZRADDHNB", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b66948},
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{"ZRADDHNT Z22.S, Z10.S, Z8.H", "ZRADDHNT", ExtFormNarrow,
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{"ZRADDHNT Z22.S, Z10.S, Z8.H", "ZRADDHNT", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b66d48},
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{"ZRSUBHNB Z22.S, Z10.S, Z8.H", "ZRSUBHNB", ExtFormNarrow,
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{"ZRSUBHNB Z22.S, Z10.S, Z8.H", "ZRSUBHNB", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b67948},
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{"ZRSUBHNT Z22.S, Z10.S, Z8.H", "ZRSUBHNT", ExtFormNarrow,
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{"ZRSUBHNT Z22.S, Z10.S, Z8.H", "ZRSUBHNT", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b67d48},
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{"ZSUBHNB Z22.S, Z10.S, Z8.H", "ZSUBHNB", ExtFormNarrow,
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{"ZSUBHNB Z22.S, Z10.S, Z8.H", "ZSUBHNB", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b67148},
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{"ZSUBHNT Z22.S, Z10.S, Z8.H", "ZSUBHNT", ExtFormNarrow,
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{"ZSUBHNT Z22.S, Z10.S, Z8.H", "ZSUBHNT", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(22, ExtArrS), ExtVector(10, ExtArrS), ExtVector(8, ExtArrH)},
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0x45b67548},
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{"ZADDHNB Z8.H, Z10.H, Z11.B", "ZADDHNB", ExtFormNarrow,
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{"ZADDHNB Z8.H, Z10.H, Z11.B", "ZADDHNB", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(8, ExtArrH), ExtVector(10, ExtArrH), ExtVector(11, ExtArrB)},
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0x4568614b},
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{"ZSUBHNT Z26.D, Z4.D, Z13.S", "ZSUBHNT", ExtFormNarrow,
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{"ZSUBHNT Z26.D, Z4.D, Z13.S", "ZSUBHNT", ExtFormNarrow, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(26, ExtArrD), ExtVector(4, ExtArrD), ExtVector(13, ExtArrS)},
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0x45fa748d},
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// The pairwise and quadword-reduction classes.
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{"ZADDP Z15.B, Z0.B, P3.M, Z0.B", "ZADDP", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
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0x4411ade0},
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{"ZADDP Z9.S, Z2.S, P5.M, Z2.S", "ZADDP", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
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[]ExtOperand{ExtVector(9, ExtArrS), ExtVector(2, ExtArrS), ExtPredicate(5, ExtQualMerging), ExtVector(2, ExtArrS)},
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0x4491b522},
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{"ZADDPT Z23.D, Z13.D, P1.M, Z13.D", "ZADDPT", ExtFormZPredicatedSource, ExtQualMerging, ExtArrD,
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[]ExtOperand{ExtVector(23, ExtArrD), ExtVector(13, ExtArrD), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrD)},
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0x04c406ed},
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{"ZADDPT Z7.D, Z6.D, Z23.D", "ZADDPT", ExtFormVectorsZm, ExtQualNone, ExtArrD,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrD), ExtVector(23, ExtArrD)},
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0x04e708d7},
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// The quadword reductions, one vector per class word, the corpus
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// line shared, plus a .D width the corpus line does not show.
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{"ZADDQV Z25.S, P3, V5.S4", "ZADDQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x04852f25},
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{"ZADDQV Z9.D, P1, V7.D2", "ZADDQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(9, ExtArrD), ExtPredicateSized(1, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 7, Arr: ExtArrD}},
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0x04c52527},
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{"ZANDQV Z25.S, P3, V5.S4", "ZANDQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x049e2f25},
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{"ZEORQV Z25.S, P3, V5.S4", "ZEORQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x049d2f25},
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{"ZORQV Z25.S, P3, V5.S4", "ZORQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x049c2f25},
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{"ZSMAXQV Z25.S, P3, V5.S4", "ZSMAXQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x048c2f25},
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{"ZSMINQV Z25.S, P3, V5.S4", "ZSMINQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x048e2f25},
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{"ZUMAXQV Z25.S, P3, V5.S4", "ZUMAXQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x048d2f25},
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{"ZUMINQV Z25.S, P3, V5.S4", "ZUMINQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x048f2f25},
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{"ZFADDQV Z25.S, P3, V5.S4", "ZFADDQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x6490af25},
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{"ZFMAXNMQV Z25.S, P3, V5.S4", "ZFMAXNMQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x6494af25},
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{"ZFMAXQV Z25.S, P3, V5.S4", "ZFMAXQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x6496af25},
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{"ZFMINNMQV Z25.S, P3, V5.S4", "ZFMINNMQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x6495af25},
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{"ZFMINQV Z25.S, P3, V5.S4", "ZFMINQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
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0x6497af25},
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} {
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in := extInstructionMeta(t, tt.mnem, tt.form, ExtQualNone, ExtArrNone)
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in := extInstructionMeta(t, tt.mnem, tt.form, tt.qual, tt.arr)
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got, err := in.Encode(tt.ops)
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if err != nil {
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t.Errorf("%s: encode: %v", tt.name, err)
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+22
-4
@@ -286,17 +286,35 @@ func arm64ExtGeneral(text string) (arch.ExtOperand, bool) {
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// arm64ExtSIMD parses a 128-bit SIMD register operand: V0..V31, written
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// bare, the scalar destination the reductions and the crypto read-back
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// forms take. The register range is left to the encoding.
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// forms take, or with the counted quadword suffix of the SVE2.1 QV class,
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// V5.S4 reading four 32-bit lanes (the spellings .B16, .H8, .S4 and .D2;
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// no other suffix parses). The register range is left to the encoding.
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func arm64ExtSIMD(text string) (arch.ExtOperand, bool) {
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rest, ok := strings.CutPrefix(text, "V")
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if !ok {
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return arch.ExtOperand{}, false
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}
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reg, arr, ok := arm64ExtRegDigits(rest)
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if !ok || arr != arch.ExtArrNone {
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arr := arch.ExtArrNone
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for _, q := range []struct {
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suffix string
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arr arch.ExtArrangement
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}{
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{"B16", arch.ExtArrB},
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{"H8", arch.ExtArrH},
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{"S4", arch.ExtArrS},
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{"D2", arch.ExtArrD},
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} {
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if s := "." + q.suffix; strings.HasSuffix(rest, s) {
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arr = q.arr
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rest = rest[:len(rest)-len(s)]
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break
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}
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}
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reg, bare, ok := arm64ExtRegDigits(rest)
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if !ok || bare != arch.ExtArrNone {
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return arch.ExtOperand{}, false
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}
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return arch.ExtOperand{Kind: arch.ExtVReg, Reg: reg}, true
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return arch.ExtOperand{Kind: arch.ExtVReg, Reg: reg, Arr: arr}, true
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}
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// arm64ExtSveMem parses the gather/scatter memory operand off a normalised
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@@ -763,6 +763,26 @@ func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
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{"ZSUBHNT Z22.S, Z10.S, Z8.H", 0x45b67548},
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{"ZADDHNB Z8.H, Z10.H, Z11.B", 0x4568614b},
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{"ZSUBHNT Z26.D, Z4.D, Z13.S", 0x45fa748d},
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// The pairwise and quadword-reduction classes: corpus lines plus a
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// width extension each.
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{"ZADDP Z15.B, Z0.B, P3.M, Z0.B", 0x4411ade0},
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{"ZADDP Z9.S, Z2.S, P5.M, Z2.S", 0x4491b522},
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{"ZADDPT Z23.D, Z13.D, P1.M, Z13.D", 0x04c406ed},
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{"ZADDPT Z7.D, Z6.D, Z23.D", 0x04e708d7},
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{"ZADDQV Z25.S, P3, V5.S4", 0x04852f25},
|
||||
{"ZADDQV Z9.D, P1, V7.D2", 0x04c52527},
|
||||
{"ZANDQV Z25.S, P3, V5.S4", 0x049e2f25},
|
||||
{"ZEORQV Z25.S, P3, V5.S4", 0x049d2f25},
|
||||
{"ZORQV Z25.S, P3, V5.S4", 0x049c2f25},
|
||||
{"ZSMAXQV Z25.S, P3, V5.S4", 0x048c2f25},
|
||||
{"ZSMINQV Z25.S, P3, V5.S4", 0x048e2f25},
|
||||
{"ZUMAXQV Z25.S, P3, V5.S4", 0x048d2f25},
|
||||
{"ZUMINQV Z25.S, P3, V5.S4", 0x048f2f25},
|
||||
{"ZFADDQV Z25.S, P3, V5.S4", 0x6490af25},
|
||||
{"ZFMAXNMQV Z25.S, P3, V5.S4", 0x6494af25},
|
||||
{"ZFMAXQV Z25.S, P3, V5.S4", 0x6496af25},
|
||||
{"ZFMINNMQV Z25.S, P3, V5.S4", 0x6495af25},
|
||||
{"ZFMINQV Z25.S, P3, V5.S4", 0x6497af25},
|
||||
}
|
||||
for _, tt := range tests {
|
||||
words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
|
||||
@@ -779,8 +799,9 @@ func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
|
||||
}
|
||||
|
||||
// TestArm64AssembleExtensionStage4Refusals pins the diagnostics the
|
||||
// narrowing statements get from the layer: the arrangement pair the single
|
||||
// size field over-determines.
|
||||
// narrowing, pairwise and quadword-reduction statements get from the layer:
|
||||
// the arrangement pair the single size field over-determines, the locked
|
||||
// pairwise top arrangement and the accumulator's bare predicate.
|
||||
func TestArm64AssembleExtensionStage4Refusals(t *testing.T) {
|
||||
tests := []struct {
|
||||
stmt string
|
||||
@@ -792,6 +813,12 @@ func TestArm64AssembleExtensionStage4Refusals(t *testing.T) {
|
||||
{"ZADDHNB Z22.D, Z10.D, Z8.H", "want .S"},
|
||||
{"ZADDHNB Z22.Q, Z10.Q, Z8.D", "want .H, .S or .D"},
|
||||
{"ZADDHNB Z22.S, Z10.S, Z8", "carries no arrangement suffix"},
|
||||
{"ZADDP Z15.B, Z0.B, P3.Z, Z0.B", "merging qualifier"},
|
||||
{"ZADDPT Z7.S, Z6.S, Z23.S", "want .D"},
|
||||
{"ZADDQV Z25.S, P9, V5.S4", "outside P0-P7"},
|
||||
{"ZADDQV Z25.S, P3/M, V5.S4", "takes no qualifier"},
|
||||
{"ZADDQV Z25.S, P3, V5", "no quadword suffix"},
|
||||
{"ZADDQV Z25.S, P3, V5.D2", "carries arrangement .D, want .S"},
|
||||
}
|
||||
for _, tt := range tests {
|
||||
got := assembleArm64SrcError(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
|
||||
|
||||
+19
-3
@@ -273,7 +273,8 @@ func TestExtensionNamesARM64(t *testing.T) {
|
||||
"ZZIP2",
|
||||
"ZZIPQ1",
|
||||
"ZZIPQ2",
|
||||
// The stage-four families: the SVE2.1 narrowing two-to-one set.
|
||||
// The stage-four families: the SVE2.1 narrowing two-to-one set, the
|
||||
// pairwise forms and the quadword reductions.
|
||||
"ZADDHNB",
|
||||
"ZADDHNT",
|
||||
"ZRADDHNB",
|
||||
@@ -282,6 +283,21 @@ func TestExtensionNamesARM64(t *testing.T) {
|
||||
"ZRSUBHNT",
|
||||
"ZSUBHNB",
|
||||
"ZSUBHNT",
|
||||
"ZADDP",
|
||||
"ZADDPT",
|
||||
"ZADDQV",
|
||||
"ZANDQV",
|
||||
"ZEORQV",
|
||||
"ZFADDQV",
|
||||
"ZFMAXNMQV",
|
||||
"ZFMAXQV",
|
||||
"ZFMINNMQV",
|
||||
"ZFMINQV",
|
||||
"ZORQV",
|
||||
"ZSMAXQV",
|
||||
"ZSMINQV",
|
||||
"ZUMAXQV",
|
||||
"ZUMINQV",
|
||||
// The stage-three families: the SVE2 crypto group, the predicate
|
||||
// counters and loop terminators with the 32-bit while compares, and
|
||||
// the reductions into a SIMD register.
|
||||
@@ -394,7 +410,7 @@ func TestExtensionNamesARM64(t *testing.T) {
|
||||
if strings.Join(got, ",") != strings.Join(want, ",") {
|
||||
t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
|
||||
}
|
||||
if n := len(arch.Extensions(arch.ARM64)); n != 389 {
|
||||
t.Errorf("the family registers %d instructions, want 389", n)
|
||||
if n := len(arch.Extensions(arch.ARM64)); n != 405 {
|
||||
t.Errorf("the family registers %d instructions, want 405", n)
|
||||
}
|
||||
}
|
||||
Reference in new issue
Block a user