petrbalvin/gasm-sdk
0
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 37 Wiki Activity

feat(arch): the SVE2.1 pairwise and quadword-reduction families

Browse Source 
Assisted-by: GLM 5.3 Flash
This commit is contained in:
petrbalvin committed 2026-10-07 20:35:41 +02:00
1 parent 31ab584eee
commit b93fccc075
5 files changed
+212 -22
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

arch/arm64_ext.go
+72 -2
View File
@@ -2597,8 +2597,19 @@ func (in ExtInstr) encodeQuadReduce(ops []ExtOperand) ([]byte, error) {
if err := in.barePredicate(pg, 2, 0, 7); err != nil {
return nil, err
}
if err := in.simdReg(vn, 3); err != nil {
return nil, err
if vn.Kind != ExtVReg {
return nil, fmt.Errorf("%s: operand 3 wants a SIMD register, got %s",
in.Name, vn.Kind)
}
if vn.Reg < 0 || vn.Reg > 31 {
return nil, fmt.Errorf("%s: operand 3 is V%d, outside V0-V31", in.Name, vn.Reg)
}
if vn.Qual != ExtQualNone {
return nil, fmt.Errorf("%s: operand 3 takes no qualifier, got %q", in.Name, vn.Qual)
}
if vn.Arr == ExtArrNone {
return nil, fmt.Errorf("%s: operand 3 carries no quadword suffix, want .B16, .H8, .S4 or .D2",
in.Name)
}
if vn.Arr != zdn.Arr {
return nil, fmt.Errorf("%s: operand 3 carries arrangement %s, want %s",
@@ -3189,6 +3200,65 @@ var arm64Extensions = []ExtInstr{
Word: 0x45207400, Form: ExtFormNarrow, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZSUBHNT; inst_gen.go + arm64sveenc.s"},
// --- the SVE2.1 pairwise and quadword-reduction families ------------------
//
// ADDP sums the halves of two vectors pairwise under a governing
// predicate, ADDPT the top halves of 128-bit pairs (predicated and
// unpredicated), and the QV class reduces a quadword vector into a
// scalable accumulator. The QV vector operand carries the counted
// quadword spelling the corpus writes, V5.S4 and friends. Provenance
// as above: the toolchain encoding table and its generated corpus, both
// produced from Arm's official ISA description, and the golden test
// pins every corpus line of each class.
{Name: "ZADDP", Summary: "Add vector halves pairwise, merging",
Word: 0x4411a000, Form: ExtFormZPredicatedSource, Size: extSizeBHSD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZADDP; inst_gen.go + arm64sveenc.s"},
{Name: "ZADDPT", Summary: "Add the top halves of 128-bit pairs, merging",
Word: 0x04c40000, Form: ExtFormZPredicatedSource, Arr: ExtArrD, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZADDPT; inst_gen.go + arm64sveenc.s"},
{Name: "ZADDPT", Summary: "Add the top halves of 128-bit pairs, unpredicated",
Word: 0x04e00800, Form: ExtFormVectorsZm, Arr: ExtArrD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZADDPT; inst_gen.go + arm64sveenc.s"},
{Name: "ZADDQV", Summary: "Add a quadword vector into a scalable accumulator",
Word: 0x04052000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZADDQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZANDQV", Summary: "And a quadword vector into a scalable accumulator",
Word: 0x041e2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZANDQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZEORQV", Summary: "Exclusive-or a quadword vector into a scalable accumulator",
Word: 0x041d2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZEORQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZFADDQV", Summary: "Add floating-point a quadword vector into a scalable accumulator",
Word: 0x6410a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZFADDQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZFMAXNMQV", Summary: "Maximum number of a quadword vector into a scalable accumulator",
Word: 0x6414a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZFMAXNMQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZFMAXQV", Summary: "Maximum of a quadword vector into a scalable accumulator",
Word: 0x6416a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZFMAXQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZFMINNMQV", Summary: "Minimum number of a quadword vector into a scalable accumulator",
Word: 0x6415a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZFMINNMQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZFMINQV", Summary: "Minimum of a quadword vector into a scalable accumulator",
Word: 0x6417a000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZFMINQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZORQV", Summary: "Or a quadword vector into a scalable accumulator",
Word: 0x041c2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZORQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZSMAXQV", Summary: "Signed maximum of a quadword vector into a scalable accumulator",
Word: 0x040c2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZSMAXQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZSMINQV", Summary: "Signed minimum of a quadword vector into a scalable accumulator",
Word: 0x040e2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZSMINQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZUMAXQV", Summary: "Unsigned maximum of a quadword vector into a scalable accumulator",
Word: 0x040d2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZUMAXQV; inst_gen.go + arm64sveenc.s"},
{Name: "ZUMINQV", Summary: "Unsigned minimum of a quadword vector into a scalable accumulator",
Word: 0x040f2000, Form: ExtFormQuadReduce, Size: extSizeBHSD, Feature: ExtFeatureSVE2p1,
Ref: "ARM DDI 0487J SVE2.1: ZUMINQV; inst_gen.go + arm64sveenc.s"},
// --- the SVE2 crypto family ----------------------------------------------
//
// The multi-precision carry steps (ADCLB, ADCLT, SBCLB, SBCLT), the SHA3