feat(arch): the SVE2.1 pairwise and quadword-reduction families

Assisted-by: GLM 5.3 Flash

asm/arm64_ext.go

@@ -286,17 +286,35 @@ func arm64ExtGeneral(text string) (arch.ExtOperand, bool) {
 
 // arm64ExtSIMD parses a 128-bit SIMD register operand: V0..V31, written
 // bare, the scalar destination the reductions and the crypto read-back
-// forms take.  The register range is left to the encoding.
+// forms take, or with the counted quadword suffix of the SVE2.1 QV class,
+// V5.S4 reading four 32-bit lanes (the spellings .B16, .H8, .S4 and .D2;
+// no other suffix parses).  The register range is left to the encoding.
 func arm64ExtSIMD(text string) (arch.ExtOperand, bool) {
 	rest, ok := strings.CutPrefix(text, "V")
 	if !ok {
 		return arch.ExtOperand{}, false
 	}
-	reg, arr, ok := arm64ExtRegDigits(rest)
-	if !ok || arr != arch.ExtArrNone {
+	arr := arch.ExtArrNone
+	for _, q := range []struct {
+		suffix string
+		arr    arch.ExtArrangement
+	}{
+		{"B16", arch.ExtArrB},
+		{"H8", arch.ExtArrH},
+		{"S4", arch.ExtArrS},
+		{"D2", arch.ExtArrD},
+	} {
+		if s := "." + q.suffix; strings.HasSuffix(rest, s) {
+			arr = q.arr
+			rest = rest[:len(rest)-len(s)]
+			break
+		}
+	}
+	reg, bare, ok := arm64ExtRegDigits(rest)
+	if !ok || bare != arch.ExtArrNone {
 		return arch.ExtOperand{}, false
 	}
-	return arch.ExtOperand{Kind: arch.ExtVReg, Reg: reg}, true
+	return arch.ExtOperand{Kind: arch.ExtVReg, Reg: reg, Arr: arr}, true
 }
 
 // arm64ExtSveMem parses the gather/scatter memory operand off a normalised