feat(arch): the SVE2.1 pairwise and quadword-reduction families
Assisted-by: GLM 5.3 Flash
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@@ -273,7 +273,8 @@ func TestExtensionNamesARM64(t *testing.T) {
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"ZZIP2",
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"ZZIPQ1",
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"ZZIPQ2",
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// The stage-four families: the SVE2.1 narrowing two-to-one set.
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// The stage-four families: the SVE2.1 narrowing two-to-one set, the
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// pairwise forms and the quadword reductions.
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"ZADDHNB",
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"ZADDHNT",
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"ZRADDHNB",
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@@ -282,6 +283,21 @@ func TestExtensionNamesARM64(t *testing.T) {
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"ZRSUBHNT",
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"ZSUBHNB",
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"ZSUBHNT",
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"ZADDP",
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"ZADDPT",
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"ZADDQV",
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"ZANDQV",
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"ZEORQV",
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"ZFADDQV",
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"ZFMAXNMQV",
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"ZFMAXQV",
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"ZFMINNMQV",
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"ZFMINQV",
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"ZORQV",
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"ZSMAXQV",
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"ZSMINQV",
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"ZUMAXQV",
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"ZUMINQV",
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// The stage-three families: the SVE2 crypto group, the predicate
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// counters and loop terminators with the 32-bit while compares, and
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// the reductions into a SIMD register.
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@@ -394,7 +410,7 @@ func TestExtensionNamesARM64(t *testing.T) {
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if strings.Join(got, ",") != strings.Join(want, ",") {
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t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
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}
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if n := len(arch.Extensions(arch.ARM64)); n != 389 {
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t.Errorf("the family registers %d instructions, want 389", n)
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if n := len(arch.Extensions(arch.ARM64)); n != 405 {
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t.Errorf("the family registers %d instructions, want 405", n)
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}
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}
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