fix(asm): route the arm64 logical immediates to ZR through REGTMP
Assisted-by: GLM 5.3 Flash
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petrbalvin committed
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@@ -311,6 +311,37 @@ func arm64InstrSize(instr *ast.Instr, fi arm64FrameInfo, pos int) int {
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case "MOV", "MOVD", "MOVW", "MOVWU", "MOVH", "MOVHU", "MOVB", "MOVBU",
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"FMOVS", "FMOVD", "FMOVQ":
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return arm64MovSize(mnem, ops, fi)
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}
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// The logical-immediate family: one word on the bitmask fast path (a
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// real destination, or the flags-only TST spellings), two words for the
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// materialisation the ZR destinations and the non-bitmask immediates
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// take. Mirrors encodeARM64DPSR's decision exactly.
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if len(ops) >= 2 && len(ops) <= 3 && isImmOperand(ops[0]) {
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switch mnem {
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case "AND", "ANDW", "ANDS", "ANDSW", "ORR", "ORRW", "EOR", "EORW",
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"BIC", "BICW", "BICS", "BICSW", "ORN", "ORNW", "EON", "EONW",
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"TST", "TSTW":
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if v, ok := arm64ImmOperandValue(ops[0]); ok {
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switch mnem {
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case "BIC", "BICW", "BICS", "BICSW", "ORN", "ORNW", "EON", "EONW":
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v = ^v
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}
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width := 64
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if strings.HasSuffix(mnem, "W") {
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width = 32
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}
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rd := 31
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if mnem != "TST" && mnem != "TSTW" {
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rd = arm64RegNum(operandRegName(ops[len(ops)-1]))
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}
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if _, _, _, bc := a64LogicalImm(v, width); bc && (rd != 31 || strings.HasPrefix(mnem, "TST")) {
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return 4
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}
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return 8
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}
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}
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}
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switch mnem {
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case "ADD", "ADDW", "SUB", "SUBW", "CMP", "CMPW", "CMN", "CMNW",
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"ADDS", "ADDSW", "SUBS", "SUBSW":
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if len(ops) >= 2 && isImmOperand(ops[0]) {
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@@ -839,48 +870,6 @@ func encodeARM64DPSR(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, er
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if strings.HasSuffix(mnem, "W") {
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width = 32
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}
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n, immr, imms, ok := a64LogicalImm(v, width)
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if !ok {
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// Beyond the bitmask immediates the toolchain materialises
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// the constant into REGTMP (R27) and uses the register form
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// (asm7.go cases 62 and 13). BIC/ORN/EON read the written
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// value, so the materialisation uses v before any inversion.
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written := v
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if inverted {
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written = ^v
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}
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width := mnem
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if strings.HasSuffix(mnem, "W") {
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width = "MOVW"
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} else {
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width = "MOVD"
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}
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mw, merr := encodeARM64LoadImm(27, written, width)
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var rn, rd int
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switch len(ops) {
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case 3:
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rn = arm64RegNum(operandRegName(ops[1]))
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rd = arm64RegNum(operandRegName(ops[2]))
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default:
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rd = arm64RegNum(operandRegName(ops[1]))
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rn = rd
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}
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if isCmp {
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rd = 31
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}
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if merr != nil || rn < 0 || rd < 0 {
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return nil, fmt.Errorf("%s: immediate %q is not a logical (bitmask) immediate", mnem, strings.Join(strings.Fields(ops[0].Raw), " "))
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}
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// The register tail against SP takes the extended form, like the
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// plain register path below.
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tail := baseOp | 27<<16 | uint32(rn)<<5 | uint32(rd)
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if opt, spok := arm64SpExtendOpt(mnem, ops[1:]); spok {
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tail = baseOp | 1<<21 | opt<<13 | 27<<16 | uint32(rn)<<5 | uint32(rd)
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}
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return append(mw, a64wordLE(tail)...), nil
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}
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opc := (baseOp >> 29) & 7
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sf := (baseOp >> 31) & 1
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var rn, rd int
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switch len(ops) {
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case 3:
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@@ -890,11 +879,50 @@ func encodeARM64DPSR(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, er
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rd = arm64RegNum(operandRegName(ops[1]))
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rn = rd
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}
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if isCmp {
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// CMP/CMN/TST write the flags alone: the destination is ZR
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// whatever the spelling says.
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rd = 31
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}
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if rn < 0 || rd < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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return a64wordLE(sf<<31 | opc<<29 | 0x24<<23 | n<<22 | immr<<16 | imms<<10 |
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uint32(rn)<<5 | uint32(rd)), nil
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n, immr, imms, ok := a64LogicalImm(v, width)
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// The toolchain's logical-immediate rows take a real destination
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// only (omovconst guards the bitmask path with rt != REGZERO): a
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// non-flag-setting logical to ZR materialises the constant into
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// REGTMP (R27) and takes the register form. The flags-only TST
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// spellings keep the fast path: ANDS ZR, Rn, #imm is their form.
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if ok && (rd != 31 || isCmp) {
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opc := (baseOp >> 29) & 7
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sf := (baseOp >> 31) & 1
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return a64wordLE(sf<<31 | opc<<29 | 0x24<<23 | n<<22 | immr<<16 | imms<<10 |
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uint32(rn)<<5 | uint32(rd)), nil
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}
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// Beyond the bitmask immediates, and for the ZR destinations, the
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// toolchain materialises the constant into REGTMP and uses the
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// register form (asm7.go cases 62 and 13). BIC/ORN/EON read the
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// written value, so the materialisation uses v before any
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// inversion.
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written := v
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if inverted {
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written = ^v
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}
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mwMnem := "MOVD"
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if strings.HasSuffix(mnem, "W") {
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mwMnem = "MOVW"
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}
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mw, merr := encodeARM64LoadImm(27, written, mwMnem)
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if merr != nil {
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return nil, fmt.Errorf("%s: immediate %q is not a logical (bitmask) immediate", mnem, strings.Join(strings.Fields(ops[0].Raw), " "))
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}
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// The register tail against SP takes the extended form, like the
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// plain register path below.
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tail := baseOp | 27<<16 | uint32(rn)<<5 | uint32(rd)
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if opt, spok := arm64SpExtendOpt(mnem, ops[1:]); spok {
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tail = baseOp | 1<<21 | opt<<13 | 27<<16 | uint32(rn)<<5 | uint32(rd)
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}
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return append(mw, a64wordLE(tail)...), nil
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}
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}
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@@ -2119,3 +2119,41 @@ func TestArm64FPImmediate(t *testing.T) {
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}
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}
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}
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// TestArm64LogicalImmZR pins the logical-immediate spellings the destination
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// changes, against `go tool asm` words: TST keeps the fast ANDS-to-ZR form
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// while a non-flag-setting logical to ZR materialises the constant into
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// REGTMP and takes the register form (omovconst's rt != REGZERO guard).
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func TestArm64LogicalImmZR(t *testing.T) {
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got := arm64Words(t,
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"\tTSTW $0x600000006, R1\n"+
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"\tTST $15, R2\n"+
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"\tAND $1, ZR\n"+
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"\tANDW $1, ZR\n"+
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"\tEOR $1, ZR\n"+
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"\tAND $15, R2, R3\n"+
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"\tANDS $0xff, R2, R3\n"+
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"\tORR $0x10, R2, R3\n")
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want := []uint32{
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0x721f043f, // ANDS W31, W1, #bitmask (TSTW)
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0xf2400c5f, // ANDS X31, X2, #15 (TST)
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0xb24003fb, // ORR X27, XZR, #1
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0x8a1b03ff, // AND X31, X31, R27
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0x320003fb, // ORR W27, WZR, #1 (ANDW to ZR)
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0x0a1b03ff, // AND W31, W31, W27
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0xb24003fb, // ORR X27, XZR, #1 (EOR to ZR)
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0xca1b03ff, // EOR X31, X31, R27
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0x92400c43, // AND X3, X2, #15
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0xf2401c43, // ANDS X3, X2, #0xff
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0xb27c0043, // ORR X3, X2, #0x10
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0xd65f03c0, // RET
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}
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if len(got) != len(want) {
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t.Fatalf("word count = %d, want %d", len(got), len(want))
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}
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for i := range want {
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if got[i] != want[i] {
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t.Errorf("word %d = %08x, want %08x", i, got[i], want[i])
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}
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}
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}
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