fix(asm): route the arm64 logical immediates to ZR through REGTMP

Assisted-by: GLM 5.3 Flash

asm/arm64_encode_test.go

@@ -2119,3 +2119,41 @@ func TestArm64FPImmediate(t *testing.T) {
 		}
 	}
 }
+
+// TestArm64LogicalImmZR pins the logical-immediate spellings the destination
+// changes, against `go tool asm` words: TST keeps the fast ANDS-to-ZR form
+// while a non-flag-setting logical to ZR materialises the constant into
+// REGTMP and takes the register form (omovconst's rt != REGZERO guard).
+func TestArm64LogicalImmZR(t *testing.T) {
+	got := arm64Words(t,
+		"\tTSTW $0x600000006, R1\n"+
+			"\tTST $15, R2\n"+
+			"\tAND $1, ZR\n"+
+			"\tANDW $1, ZR\n"+
+			"\tEOR $1, ZR\n"+
+			"\tAND $15, R2, R3\n"+
+			"\tANDS $0xff, R2, R3\n"+
+			"\tORR $0x10, R2, R3\n")
+	want := []uint32{
+		0x721f043f, // ANDS W31, W1, #bitmask (TSTW)
+		0xf2400c5f, // ANDS X31, X2, #15 (TST)
+		0xb24003fb, // ORR X27, XZR, #1
+		0x8a1b03ff, // AND X31, X31, R27
+		0x320003fb, // ORR W27, WZR, #1 (ANDW to ZR)
+		0x0a1b03ff, // AND W31, W31, W27
+		0xb24003fb, // ORR X27, XZR, #1 (EOR to ZR)
+		0xca1b03ff, // EOR X31, X31, R27
+		0x92400c43, // AND X3, X2, #15
+		0xf2401c43, // ANDS X3, X2, #0xff
+		0xb27c0043, // ORR X3, X2, #0x10
+		0xd65f03c0, // RET
+	}
+	if len(got) != len(want) {
+		t.Fatalf("word count = %d, want %d", len(got), len(want))
+	}
+	for i := range want {
+		if got[i] != want[i] {
+			t.Errorf("word %d = %08x, want %08x", i, got[i], want[i])
+		}
+	}
+}