fix(asm): reject the operand shapes the toolchain rejects on riscv64
Assisted-by: GLM 5.3 Flash
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@@ -3,153 +3,192 @@
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package asm
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import "strings"
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// RISC-V register encoding: maps register names to their 5-bit numbers.
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// The Go assembler uses the standard RISC-V ABI naming.
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// riscvRegNum returns the 5-bit register number for a RISC-V register name.
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// Returns -1 if the register is not recognized.
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func riscvRegNum(name string) int {
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n, _ := riscvBankedRegNum(name)
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return n
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}
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// riscvRegBank classifies a RISC-V register name by its bank: the integer
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// file (X0-X31 with the ABI aliases), the floating-point file (F0-F31 with
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// the FP aliases) and the vector file (V0-V31). The toolchain's validate
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// stage checks every operand against its instruction's bank and rejects the
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// wrong one; the bank is what makes "F1" and "X1" different operands even
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// though both encode as the number 1.
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type riscvRegBank uint8
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const (
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riscvBankNone riscvRegBank = iota // not a register name
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riscvBankInt // X0-X31, ZERO, RA, SP, ...
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riscvBankFloat // F0-F31, FT0-FT11, FS0-FS11, FA0-FA7
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riscvBankVec // V0-V31
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)
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// String names the bank the way the bank-mismatch diagnostics spell it.
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func (b riscvRegBank) String() string {
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switch b {
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case riscvBankInt:
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return "integer"
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case riscvBankFloat:
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return "float"
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case riscvBankVec:
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return "vector"
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}
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return "none"
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}
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// riscvBankedRegNum returns the 5-bit register number for a name together
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// with the bank the name belongs to. riscvBankNone with a negative number
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// names no register at all.
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func riscvBankedRegNum(name string) (int, riscvRegBank) {
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switch name {
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// Floating-point registers (F0-F31).
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case "F0", "FT0":
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return 0, riscvBankFloat
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case "F1", "FT1":
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return 1, riscvBankFloat
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case "F2", "FT2":
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return 2, riscvBankFloat
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case "F3", "FT3":
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return 3, riscvBankFloat
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case "F4", "FT4":
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return 4, riscvBankFloat
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case "F5", "FT5":
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return 5, riscvBankFloat
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case "F6", "FT6":
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return 6, riscvBankFloat
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case "F7", "FT7":
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return 7, riscvBankFloat
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case "F8", "FS0":
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return 8, riscvBankFloat
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case "F9", "FS1":
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return 9, riscvBankFloat
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case "F10", "FA0":
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return 10, riscvBankFloat
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case "F11", "FA1":
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return 11, riscvBankFloat
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case "F12", "FA2":
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return 12, riscvBankFloat
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case "F13", "FA3":
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return 13, riscvBankFloat
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case "F14", "FA4":
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return 14, riscvBankFloat
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case "F15", "FA5":
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return 15, riscvBankFloat
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case "F16", "FA6":
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return 16, riscvBankFloat
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case "F17", "FA7":
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return 17, riscvBankFloat
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case "F18", "FS2":
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return 18, riscvBankFloat
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case "F19", "FS3":
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return 19, riscvBankFloat
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case "F20", "FS4":
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return 20, riscvBankFloat
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case "F21", "FS5":
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return 21, riscvBankFloat
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case "F22", "FS6":
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return 22, riscvBankFloat
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case "F23", "FS7":
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return 23, riscvBankFloat
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case "F24", "FS8":
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return 24, riscvBankFloat
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case "F25", "FS9":
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return 25, riscvBankFloat
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case "F26", "FS10":
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return 26, riscvBankFloat
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case "F27", "FS11":
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return 27, riscvBankFloat
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case "F28", "FT8":
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return 28, riscvBankFloat
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case "F29", "FT9":
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return 29, riscvBankFloat
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case "F30", "FT10":
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return 30, riscvBankFloat
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case "F31", "FT11":
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return 31, riscvBankFloat
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}
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// Vector registers V0-V31 (the "V" extension). They share the
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// register numbering with the integer file: a bare number 0-31.
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if len(name) >= 2 && name[0] == 'V' {
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if n, ok := parseRegDigits(name[1:], 31); ok {
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return n, riscvBankVec
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}
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}
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switch name {
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// Numbered integer registers.
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case "X0", "ZERO":
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return 0
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return 0, riscvBankInt
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case "X1", "RA", "LR":
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return 1
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return 1, riscvBankInt
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case "X2", "SP":
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return 2
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return 2, riscvBankInt
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case "X3", "GP":
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return 3
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return 3, riscvBankInt
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case "X4", "TP":
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return 4
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return 4, riscvBankInt
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case "X5", "T0":
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return 5
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return 5, riscvBankInt
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case "X6", "T1":
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return 6
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return 6, riscvBankInt
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case "X7", "T2":
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return 7
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return 7, riscvBankInt
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case "X8", "S0", "FP":
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return 8
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return 8, riscvBankInt
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case "X9", "S1":
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return 9
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return 9, riscvBankInt
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case "X10", "A0":
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return 10
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return 10, riscvBankInt
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case "X11", "A1":
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return 11
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return 11, riscvBankInt
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case "X12", "A2":
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return 12
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return 12, riscvBankInt
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case "X13", "A3":
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return 13
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return 13, riscvBankInt
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case "X14", "A4":
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return 14
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return 14, riscvBankInt
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case "X15", "A5":
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return 15
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return 15, riscvBankInt
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case "X16", "A6":
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return 16
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return 16, riscvBankInt
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case "X17", "A7":
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return 17
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return 17, riscvBankInt
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case "X18", "S2":
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return 18
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return 18, riscvBankInt
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case "X19", "S3":
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return 19
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return 19, riscvBankInt
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case "X20", "S4":
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return 20
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return 20, riscvBankInt
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case "X21", "S5":
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return 21
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return 21, riscvBankInt
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case "X22", "S6":
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return 22
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return 22, riscvBankInt
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case "X23", "S7":
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return 23
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return 23, riscvBankInt
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case "X24", "S8":
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return 24
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return 24, riscvBankInt
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case "X25", "S9":
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return 25
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return 25, riscvBankInt
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case "X26", "S10", "CTXT":
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return 26
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return 26, riscvBankInt
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case "X27", "S11", "g":
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return 27
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return 27, riscvBankInt
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case "X28", "T3":
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return 28
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return 28, riscvBankInt
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case "X29", "T4":
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return 29
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return 29, riscvBankInt
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case "X30", "T5":
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return 30
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return 30, riscvBankInt
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case "X31", "T6", "TMP":
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return 31
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// Floating-point registers (F0-F31).
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case "F0", "FT0":
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return 0
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case "F1", "FT1":
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return 1
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case "F2", "FT2":
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return 2
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case "F3", "FT3":
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return 3
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case "F4", "FT4":
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return 4
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case "F5", "FT5":
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return 5
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case "F6", "FT6":
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return 6
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case "F7", "FT7":
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return 7
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case "F8", "FS0":
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return 8
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case "F9", "FS1":
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return 9
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case "F10", "FA0":
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return 10
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case "F11", "FA1":
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return 11
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case "F12", "FA2":
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return 12
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case "F13", "FA3":
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return 13
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case "F14", "FA4":
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return 14
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case "F15", "FA5":
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return 15
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case "F16", "FA6":
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return 16
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case "F17", "FA7":
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return 17
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case "F18", "FS2":
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return 18
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case "F19", "FS3":
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return 19
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case "F20", "FS4":
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return 20
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case "F21", "FS5":
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return 21
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case "F22", "FS6":
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return 22
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case "F23", "FS7":
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return 23
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case "F24", "FS8":
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return 24
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case "F25", "FS9":
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return 25
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case "F26", "FS10":
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return 26
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case "F27", "FS11":
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return 27
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case "F28", "FT8":
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return 28
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case "F29", "FT9":
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return 29
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case "F30", "FT10":
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return 30
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case "F31", "FT11":
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return 31
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default:
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// Vector registers V0-V31 (the "V" extension). They share the
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// register numbering with the integer file: a bare number 0-31.
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if len(name) >= 2 && name[0] == 'V' {
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if n, ok := parseRegDigits(name[1:], 31); ok {
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return n
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}
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}
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return -1
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return 31, riscvBankInt
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}
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return -1, riscvBankNone
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}
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// parseRegDigits parses a decimal register suffix and reports whether it is
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@@ -472,6 +511,56 @@ var riscvCvtTable = map[string]riscvCvtEnc{
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"FMVSX": {0x78, 0x0, 0x0, 0x53},
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}
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// riscvCvtBanks answers which register bank each operand of an FP
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// conversion or move carries, read from the mnemonic's direction: FCVTWS
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// moves float32 into an integer register (rd integer, rs1 float), FCVTSW
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// the reverse, FCLASS reads a float into an integer mask and the FMV
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// spellings follow their X position. The rd bank comes first.
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func riscvCvtBanks(mnem string) (riscvRegBank, riscvRegBank) {
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// The classify and bit-move forms.
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switch {
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case strings.HasPrefix(mnem, "FCLASS"):
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return riscvBankInt, riscvBankFloat
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case strings.HasPrefix(mnem, "FMV"):
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if len(mnem) > 3 && mnem[3] == 'X' {
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return riscvBankInt, riscvBankFloat // FMVXD, FMVXW, FMVXS
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}
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return riscvBankFloat, riscvBankInt // FMVDX, FMVWX, FMVFS, FMVSX
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}
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if !strings.HasPrefix(mnem, "FCVT") || len(mnem) < 6 {
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return riscvBankNone, riscvBankNone
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}
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rest := mnem[4:]
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// intWU/LU + floatSDQ: float → integer.
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switch rest[:2] {
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case "WU", "LU":
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if isRiscvWidthLetter(rest[2]) {
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return riscvBankInt, riscvBankFloat
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}
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}
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switch rest[0] {
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case 'W', 'L':
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if isRiscvWidthLetter(rest[1]) {
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return riscvBankInt, riscvBankFloat
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}
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}
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// floatSDQ + intWU/LU: integer → float.
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if isRiscvWidthLetter(rest[0]) {
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switch rest[1:] {
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case "W", "WU", "L", "LU":
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return riscvBankFloat, riscvBankInt
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}
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// float → float width conversion.
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return riscvBankFloat, riscvBankFloat
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}
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return riscvBankNone, riscvBankNone
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}
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// isRiscvWidthLetter reports whether c names a float width (S, D or Q).
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func isRiscvWidthLetter(c byte) bool {
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return c == 'S' || c == 'D' || c == 'Q'
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}
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// riscvCvtType encodes an FP conversion instruction.
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// Layout: funct7 | rs2(convtype) | rs1 | funct3(rm) | rd | opcode.
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func riscvCvtType(enc riscvCvtEnc, rd, rs1 int) uint32 {
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@@ -209,12 +209,12 @@ func TestRISCVToolchainRejections(t *testing.T) {
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{
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name: "fence predecessor",
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src: "\tFENCE X, W\n",
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want: "FENCE: invalid predecessor operand",
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want: "invalid FENCE predecessor operand",
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},
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{
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name: "fence successor",
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src: "\tFENCE W, Q\n",
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want: "FENCE: invalid successor operand",
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want: "invalid FENCE successor operand",
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},
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{
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name: "immediate CSR pseudo with register",
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