petrbalvin
9b751f6e58
feat(asm): encode the riscv64 quad-precision family and fix the fp cvt paths
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Assisted-by: GLM 5.3 Flash
2026-10-07 00:47:27 +02:00
petrbalvin
778c297214
feat(asm): encode the riscv64 vector arithmetic families
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Assisted-by: GLM 5.3 Flash
2026-10-07 00:47:27 +02:00
petrbalvin
ddfa33ccc1
feat(asm): encode the riscv64 bit-manipulation families
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The Zba address generation, Zbb unary bit operations, Zbc carry-less
multiplication and Zbs single-bit families were names the table carried
and the encoder refused: thirty spellings plus RORI and XNOR fell over.
The register and immediate forms now encode as the toolchain does, the
unary operations carry their fixed rs2 constant, RORI lowers to ROR's
expansion (its reverse shift compressing like ROR's), XNOR XORs and
inverts in place, and ROL/ROLW rotate left through the same temporary
the toolchain uses, taking a register amount only as its own expansion
requires. The toolchain's whole testdata block for these families is
now a differential test: every word must agree byte for byte.
Assisted-by: GLM 5.3 Flash
2026-10-07 00:47:27 +02:00
petrbalvin
1456907000
feat(riscv64,loong64): operand tail, float DATA and honest port classification
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Assisted-by: GLM 5.3 Flash
2026-09-21 00:44:47 +02:00
petrbalvin
9dc3987e02
feat(riscv64,loong64): PCALIGN, branch relaxation and operand shapes
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Assisted-by: GLM 5.3 Flash
2026-09-20 14:25:47 +02:00
petrbalvin
de5d9f358e
feat(riscv64,loong64): encode AMO atomics, vector slices and bit ops
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Assisted-by: GLM 5.3 Flash
2026-09-20 06:44:51 +02:00
petrbalvin
f15ff66fb1
fix(riscv64): accept the g spelling of the goroutine register
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Assisted-by: GLM 5.3
2026-09-20 00:38:24 +02:00
petrbalvin
79a2c16bac
fix(riscv64): compressed store offsets, FENCE and branch range checks
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Assisted-by: GLM 5.3
2026-09-19 23:49:13 +02:00
petrbalvin
f37f183577
feat(riscv64): GOROOT instruction shapes, DATA order and offset expressions
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Assisted-by: GLM 5.3 Flash
2026-09-19 19:58:43 +02:00
petrbalvin
1691c81095
style: replace em and en dashes across sources
2026-09-14 18:22:18 +02:00
petrbalvin
681a449c01
fix(asm): match RISC-V branch and jump encodings
2026-08-13 17:57:10 +02:00
petrbalvin
f0512a4e1c
fix(asm): complete RISC-V compressed loads/stores and word arithmetic
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Assisted-by: DeepSeek V4 Pro
2026-08-13 15:42:38 +02:00
petrbalvin
373c09f725
fix(asm): correct RISC-V operand order and complete RVC compression
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Assisted-by: DeepSeek V4 Pro
2026-08-13 15:13:31 +02:00
petrbalvin
b78b6c5004
fix(asm): correct RISC-V frame layout and RVC encodings
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Assisted-by: GLM 5.2
2026-08-13 14:41:57 +02:00
petrbalvin
f41a86b660
feat(asm): add RISC-V ELF relocatable object emission and SB relocation
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support
2026-08-03 08:51:00 +02:00
petrbalvin
7721353d44
feat(asm): add RVC compression for branches, arithmetic, and FP
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Assisted-by: DeepSeek V4 Pro
2026-08-03 01:08:00 +02:00
petrbalvin
243b087116
feat(riscv): add MOV pseudo-instruction and RVC compressed encoding
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Assisted-by: DeepSeek V4 Pro
2026-08-02 18:22:00 +02:00
petrbalvin
eee7a6d4a4
feat(riscv): add RISC-V RV64A, FP and CSR instruction support
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Assisted-by: Kimi K3
2026-08-02 11:45:00 +02:00
petrbalvin
f860bf8ce6
feat(asm): add RISC-V encoder with RV64I/RV64M instruction formats
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Assisted-by: Kimi K3
2026-08-01 19:51:00 +02:00
petrbalvin