17 Commits

Include renames

Author	SHA1	Message	Date
petrbalvin	56ad158772	fix: restore iota blocks, asm --format flag and prose after the syntax pass	2026-08-29 17:12:53 +02:00
petrbalvin	eacf33d0f7	fix: staticcheck and deadcode findings repo-wide, modernize counting loops	2026-08-29 15:25:15 +02:00
petrbalvin	c05c53452f	fix(asm): encode RISC-V CALL sym(SB) as JAL ... Assisted-by: DeepSeek V4 Pro	2026-08-13 18:12:22 +02:00
petrbalvin	681a449c01	fix(asm): match RISC-V branch and jump encodings	2026-08-13 17:57:10 +02:00
petrbalvin	31a2cee382	fix(asm): materialise RISC-V MOV immediates	2026-08-13 17:41:16 +02:00
petrbalvin	3bc7c18bc3	fix(asm): materialise large RISC-V immediates ... Assisted-by: DeepSeek V4 Pro	2026-08-13 16:04:08 +02:00
petrbalvin	f0512a4e1c	fix(asm): complete RISC-V compressed loads/stores and word arithmetic ... Assisted-by: DeepSeek V4 Pro	2026-08-13 15:42:38 +02:00
petrbalvin	373c09f725	fix(asm): correct RISC-V operand order and complete RVC compression ... Assisted-by: DeepSeek V4 Pro	2026-08-13 15:13:31 +02:00
petrbalvin	b78b6c5004	fix(asm): correct RISC-V frame layout and RVC encodings ... Assisted-by: GLM 5.2	2026-08-13 14:41:57 +02:00
petrbalvin	9b5c878f9e	feat(asm): emit RISC-V GOOBJ with the shared emitter ... Assisted-by: DeepSeek V4 Pro	2026-08-13 12:07:29 +02:00
petrbalvin	49566de7fb	feat(asm): add did-you-mean suggestions for undefined labels ... Assisted-by: DeepSeek V4 Pro	2026-08-05 18:52:00 +02:00
petrbalvin	f41a86b660	feat(asm): add RISC-V ELF relocatable object emission and SB relocation ... support	2026-08-03 08:51:00 +02:00
petrbalvin	7721353d44	feat(asm): add RVC compression for branches, arithmetic, and FP ... Assisted-by: DeepSeek V4 Pro	2026-08-03 01:08:00 +02:00
petrbalvin	243b087116	feat(riscv): add MOV pseudo-instruction and RVC compressed encoding ... Assisted-by: DeepSeek V4 Pro	2026-08-02 18:22:00 +02:00
petrbalvin	eee7a6d4a4	feat(riscv): add RISC-V RV64A, FP and CSR instruction support ... Assisted-by: Kimi K3	2026-08-02 11:45:00 +02:00
petrbalvin	a2acc9b5a3	feat(riscv): add prologue, epilogue and frame pseudo-register support ... Assisted-by: Kimi K3	2026-08-02 00:18:00 +02:00
petrbalvin	f860bf8ce6	feat(asm): add RISC-V encoder with RV64I/RV64M instruction formats ... Assisted-by: Kimi K3	2026-08-01 19:51:00 +02:00