 petrbalvin
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79a2c16bac
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fix(riscv64): compressed store offsets, FENCE and branch range checks
Assisted-by: GLM 5.3
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2026-09-19 23:49:13 +02:00 |
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petrbalvin
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f37f183577
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feat(riscv64): GOROOT instruction shapes, DATA order and offset expressions
Assisted-by: GLM 5.3 Flash
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2026-09-19 19:58:43 +02:00 |
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petrbalvin
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1691c81095
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style: replace em and en dashes across sources
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2026-09-14 18:22:18 +02:00 |
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petrbalvin
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681a449c01
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fix(asm): match RISC-V branch and jump encodings
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2026-08-13 17:57:10 +02:00 |
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petrbalvin
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f0512a4e1c
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fix(asm): complete RISC-V compressed loads/stores and word arithmetic
Assisted-by: DeepSeek V4 Pro
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2026-08-13 15:42:38 +02:00 |
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petrbalvin
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373c09f725
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fix(asm): correct RISC-V operand order and complete RVC compression
Assisted-by: DeepSeek V4 Pro
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2026-08-13 15:13:31 +02:00 |
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petrbalvin
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b78b6c5004
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fix(asm): correct RISC-V frame layout and RVC encodings
Assisted-by: GLM 5.2
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2026-08-13 14:41:57 +02:00 |
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petrbalvin
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f41a86b660
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feat(asm): add RISC-V ELF relocatable object emission and SB relocation
support
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2026-08-03 08:51:00 +02:00 |
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petrbalvin
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7721353d44
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feat(asm): add RVC compression for branches, arithmetic, and FP
Assisted-by: DeepSeek V4 Pro
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2026-08-03 01:08:00 +02:00 |
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petrbalvin
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243b087116
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feat(riscv): add MOV pseudo-instruction and RVC compressed encoding
Assisted-by: DeepSeek V4 Pro
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2026-08-02 18:22:00 +02:00 |
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petrbalvin
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eee7a6d4a4
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feat(riscv): add RISC-V RV64A, FP and CSR instruction support
Assisted-by: Kimi K3
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2026-08-02 11:45:00 +02:00 |
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petrbalvin
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f860bf8ce6
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feat(asm): add RISC-V encoder with RV64I/RV64M instruction formats
Assisted-by: Kimi K3
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2026-08-01 19:51:00 +02:00 |
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