petrbalvin
bffe408afa
feat(asm): resolve every CSR name the toolchain knows
...
The riscv64 assembler carried fourteen hand-picked CSR names where the
toolchain resolves three hundred and twenty-nine: a CSRR/CSRW family
instruction naming any privileged register beyond the few base ones came
out as unknown CSR. The table now carries the RISC-V privileged
specification's register set exactly as go tool asm spells it, and a
differential test assembles every name through both assemblers and
requires the words to agree byte for byte.
Assisted-by: GLM 5.3 Flash
2026-10-07 00:47:27 +02:00
petrbalvin
4d01bb3ecf
build: rename the module to sourcedock.dev/petrbalvin/gasm-sdk
Test / test (push) Successful in 4m18s
2026-09-26 11:08:43 +02:00
petrbalvin
1456907000
feat(riscv64,loong64): operand tail, float DATA and honest port classification
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Assisted-by: GLM 5.3 Flash
2026-09-21 00:44:47 +02:00
petrbalvin
9dc3987e02
feat(riscv64,loong64): PCALIGN, branch relaxation and operand shapes
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Assisted-by: GLM 5.3 Flash
2026-09-20 14:25:47 +02:00
petrbalvin
de5d9f358e
feat(riscv64,loong64): encode AMO atomics, vector slices and bit ops
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Assisted-by: GLM 5.3 Flash
2026-09-20 06:44:51 +02:00
petrbalvin
79a2c16bac
fix(riscv64): compressed store offsets, FENCE and branch range checks
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Assisted-by: GLM 5.3
2026-09-19 23:49:13 +02:00
petrbalvin
f37f183577
feat(riscv64): GOROOT instruction shapes, DATA order and offset expressions
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Assisted-by: GLM 5.3 Flash
2026-09-19 19:58:43 +02:00
petrbalvin
23c001be51
feat(asm): encode indirect JMP and CALL on all four architectures
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Assisted-by: GLM 5.3 Flash
2026-09-19 19:17:07 +02:00
petrbalvin
40476546df
fix(asm): close the oracle parity gaps in frame addressing and calls
2026-09-14 23:25:14 +02:00
petrbalvin
2e2c0b82a0
feat(asm): emit the riscv64 stack-split guard and fix large-frame addressing
2026-09-14 21:09:13 +02:00
petrbalvin
1691c81095
style: replace em and en dashes across sources
2026-09-14 18:22:18 +02:00
petrbalvin
56ad158772
fix: restore iota blocks, asm --format flag and prose after the syntax pass
Test / vet (push) Successful in 48s
Test / test (push) Successful in 2m35s
Test / build (push) Successful in 40s
2026-08-29 17:12:53 +02:00
petrbalvin
eacf33d0f7
fix: staticcheck and deadcode findings repo-wide, modernize counting loops
2026-08-29 15:25:15 +02:00
petrbalvin
c05c53452f
fix(asm): encode RISC-V CALL sym(SB) as JAL
...
Test / vet (push) Successful in 47s
Test / test (push) Failing after 2m9s
Test / build (push) Skipped
Assisted-by: DeepSeek V4 Pro
2026-08-13 18:12:22 +02:00
petrbalvin
681a449c01
fix(asm): match RISC-V branch and jump encodings
2026-08-13 17:57:10 +02:00
petrbalvin
31a2cee382
fix(asm): materialise RISC-V MOV immediates
Test / vet (push) Successful in 44s
Test / test (push) Failing after 1m56s
Test / build (push) Skipped
2026-08-13 17:41:16 +02:00
petrbalvin
3bc7c18bc3
fix(asm): materialise large RISC-V immediates
...
Assisted-by: DeepSeek V4 Pro
2026-08-13 16:04:08 +02:00
petrbalvin
f0512a4e1c
fix(asm): complete RISC-V compressed loads/stores and word arithmetic
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Assisted-by: DeepSeek V4 Pro
2026-08-13 15:42:38 +02:00
petrbalvin
373c09f725
fix(asm): correct RISC-V operand order and complete RVC compression
...
Assisted-by: DeepSeek V4 Pro
2026-08-13 15:13:31 +02:00
petrbalvin
b78b6c5004
fix(asm): correct RISC-V frame layout and RVC encodings
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Assisted-by: GLM 5.2
2026-08-13 14:41:57 +02:00
petrbalvin
9b5c878f9e
feat(asm): emit RISC-V GOOBJ with the shared emitter
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Assisted-by: DeepSeek V4 Pro
2026-08-13 12:07:29 +02:00
petrbalvin
49566de7fb
feat(asm): add did-you-mean suggestions for undefined labels
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Assisted-by: DeepSeek V4 Pro
2026-08-05 18:52:00 +02:00
petrbalvin
f41a86b660
feat(asm): add RISC-V ELF relocatable object emission and SB relocation
...
support
2026-08-03 08:51:00 +02:00
petrbalvin
7721353d44
feat(asm): add RVC compression for branches, arithmetic, and FP
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Assisted-by: DeepSeek V4 Pro
2026-08-03 01:08:00 +02:00
petrbalvin
243b087116
feat(riscv): add MOV pseudo-instruction and RVC compressed encoding
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Assisted-by: DeepSeek V4 Pro
2026-08-02 18:22:00 +02:00
petrbalvin
eee7a6d4a4
feat(riscv): add RISC-V RV64A, FP and CSR instruction support
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Assisted-by: Kimi K3
2026-08-02 11:45:00 +02:00
petrbalvin
a2acc9b5a3
feat(riscv): add prologue, epilogue and frame pseudo-register support
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Assisted-by: Kimi K3
2026-08-02 00:18:00 +02:00
petrbalvin
f860bf8ce6
feat(asm): add RISC-V encoder with RV64I/RV64M instruction formats
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Assisted-by: Kimi K3
2026-08-01 19:51:00 +02:00