265 lines
7.4 KiB
Go
265 lines
7.4 KiB
Go
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import (
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"fmt"
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"sourcedock.dev/petrbalvin/gasm-devkit/ast"
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)
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// assembleRISCV assembles a RISC-V TEXT function body into machine code.
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// It handles the core RV64I/RV64M instruction set with fixed 32-bit encoding.
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func assembleRISCV(t *ast.Text) ([]byte, map[string]int, error) {
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fi := riscvComputeFrame(t)
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prologue := riscvPrologue(fi)
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// First pass: compute label offsets (all RISC-V instructions are 4 bytes).
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// Labels are offset by the prologue length.
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offsets := map[string]int{}
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var instrs []*ast.Instr
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pos := len(prologue)
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for _, stmt := range t.Body {
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switch s := stmt.(type) {
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case *ast.Label:
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offsets[s.Name.Text] = pos
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case *ast.Instr:
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instrs = append(instrs, s)
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pos += 4 // all RISC-V instructions are 4 bytes
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}
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}
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// Second pass: encode instructions.
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out := append([]byte(nil), prologue...)
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for _, instr := range instrs {
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code, err := encodeRISCVInstr(instr, pos, offsets, fi)
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if err != nil {
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return nil, nil, fmt.Errorf("%s: %w", instr.Mnemonic.Text, err)
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}
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out = append(out, code...)
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pos -= 4 // track remaining
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}
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return out, offsets, nil
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}
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// encodeRISCVInstr encodes a single RISC-V instruction.
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func encodeRISCVInstr(instr *ast.Instr, pc int, offsets map[string]int, fi riscvFrameInfo) ([]byte, error) {
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mnem := instr.Mnemonic.Text
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ops := instr.Operands
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var word uint32
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// Handle pseudo-instructions and special cases first.
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switch mnem {
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case "RET":
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// RET = JALR X0, 0(X1)
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word = riscvIType(riscvEnc{0x67, 0x0, 0x00}, 0, 1, 0)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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case "CALL":
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// CALL is a pseudo-instruction; encode as NOP placeholder.
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word = riscvIType(riscvEnc{0x13, 0x0, 0x00}, 0, 0, 0)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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case "JMP":
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// JMP = JAL X0, target
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var target string
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if len(ops) >= 1 {
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target = labelFromOperand(ops[0])
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}
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targetOff, ok := offsets[target]
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if !ok {
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return nil, fmt.Errorf("undefined label %q", target)
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}
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offset := int32(targetOff - pc)
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word = riscvJType(0, offset)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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case "JAL":
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rd := 0
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var target string
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if len(ops) >= 2 {
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rd = regFromOperand(ops[0])
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target = labelFromOperand(ops[1])
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} else if len(ops) == 1 {
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target = labelFromOperand(ops[0])
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}
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targetOff, ok := offsets[target]
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if !ok {
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return nil, fmt.Errorf("undefined label %q", target)
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}
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offset := int32(targetOff - pc)
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word = riscvJType(rd, offset)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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}
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enc, ok := riscvInstrTable[mnem]
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if !ok {
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return nil, fmt.Errorf("unsupported RISC-V instruction %q", mnem)
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}
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switch {
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// R-type: Plan 9 order is INSTR src1, src2, dst (destination last).
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case len(ops) == 3 && isRTypeInstr(mnem):
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rs1 := regFromOperand(ops[0]) // source 1 (first operand)
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rs2 := regFromOperand(ops[1]) // source 2 (second operand)
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rd := regFromOperand(ops[2]) // destination (last operand)
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if rd < 0 || rs1 < 0 || rs2 < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvRType(enc, rd, rs1, rs2)
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// I-type with immediate: Plan 9 order is INSTR src, imm, dst.
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case len(ops) == 3 && isITypeInstr(mnem):
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rs1 := regFromOperand(ops[0]) // source register
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imm := immFromOperand(ops[1]) // immediate
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rd := regFromOperand(ops[2]) // destination
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if rd < 0 || rs1 < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvIType(enc, rd, rs1, imm)
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// Loads: rd, offset(rs1) — Plan 9 order is LD src, dst.
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case len(ops) == 2 && isLoadInstr(mnem):
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rd := regFromOperand(ops[1]) // destination (last operand)
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rs1, imm := memFromOperandWithFrame(ops[0], fi) // memory source (first operand)
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if rd < 0 || rs1 < 0 {
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return nil, fmt.Errorf("invalid operand in %s", mnem)
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}
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word = riscvIType(enc, rd, rs1, imm)
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// Stores: Plan 9 order is SD src, dst (src=register, dst=memory).
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case len(ops) == 2 && isStoreInstr(mnem):
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rs2 := regFromOperand(ops[0]) // source register (first operand)
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rs1, imm := memFromOperandWithFrame(ops[1], fi) // memory dest (last operand)
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if rs2 < 0 || rs1 < 0 {
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return nil, fmt.Errorf("invalid operand in %s", mnem)
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}
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word = riscvSType(enc, rs1, rs2, imm)
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// Branches: rs1, rs2, label.
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case len(ops) == 3 && isBranchInstr(mnem):
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rs1 := regFromOperand(ops[0])
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rs2 := regFromOperand(ops[1])
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target := labelFromOperand(ops[2])
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targetOff, ok := offsets[target]
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if !ok {
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return nil, fmt.Errorf("undefined label %q", target)
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}
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rs1Off := 0 // placeholder
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_ = rs1Off
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offset := int32(targetOff - pc)
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if rs1 < 0 || rs2 < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvBType(enc, rs1, rs2, offset)
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// U-type: rd, imm.
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case len(ops) == 2 && isUTypeInstr(mnem):
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rd := regFromOperand(ops[0])
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imm := immFromOperand(ops[1])
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if rd < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvUType(enc, rd, imm)
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default:
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return nil, fmt.Errorf("cannot encode %s with %d operands", mnem, len(ops))
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}
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// Emit as little-endian 32-bit word.
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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}
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// Instruction type classifiers.
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func isRTypeInstr(m string) bool {
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switch m {
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case "ADD", "SUB", "SLL", "SLT", "SLTU", "XOR", "SRL", "SRA", "OR", "AND",
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"ADDW", "SUBW", "SLLW", "SRLW", "SRAW",
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"MUL", "MULH", "MULHSU", "MULHU", "DIV", "DIVU", "REM", "REMU",
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"MULW", "DIVW", "DIVUW", "REMW", "REMUW":
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return true
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}
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return false
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}
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func isITypeInstr(m string) bool {
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switch m {
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case "ADDI", "ADDIW", "SLTI", "SLTIU", "XORI", "ORI", "ANDI", "JALR":
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return true
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}
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return false
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}
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func isLoadInstr(m string) bool {
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switch m {
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case "LB", "LH", "LW", "LD", "LBU", "LHU", "LWU":
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return true
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}
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return false
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}
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func isStoreInstr(m string) bool {
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switch m {
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case "SB", "SH", "SW", "SD":
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return true
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}
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return false
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}
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func isBranchInstr(m string) bool {
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switch m {
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case "BEQ", "BNE", "BLT", "BGE", "BLTU", "BGEU":
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return true
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}
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return false
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}
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func isUTypeInstr(m string) bool {
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return m == "LUI" || m == "AUIPC"
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}
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// Operand helpers.
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func regFromOperand(op *ast.Operand) int {
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// Register is in Addr.Base (from (base) syntax) or Addr.Sym.Name (bare ident).
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if op.Addr.Base != "" {
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return riscvRegNum(op.Addr.Base)
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}
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if op.Addr.Sym != nil && op.Addr.Sym.Name != "" {
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return riscvRegNum(op.Addr.Sym.Name)
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}
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return -1
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}
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func immFromOperand(op *ast.Operand) int32 {
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if op.Imm.HasVal {
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v := op.Imm.Val
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if op.Imm.Neg {
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v = -v
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}
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return int32(v)
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}
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return 0
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}
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func memFromOperand(op *ast.Operand) (rs1 int, imm int32) {
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rs1 = riscvRegNum(op.Addr.Base)
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imm = int32(op.Addr.Offset)
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return
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}
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// memFromOperandWithFrame resolves a memory operand, handling FP/SP
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// pseudo-registers via the frame mapping.
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func memFromOperandWithFrame(op *ast.Operand, fi riscvFrameInfo) (rs1 int, imm int32) {
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// Check for a pseudo-register reference (name+offset(FP) or name+offset(SP)).
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if op.Addr.Sym != nil && op.Addr.Sym.Pseudo != "" {
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return riscvResolvePseudo(op.Addr.Sym, fi)
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}
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// Plain register+offset memory reference.
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return memFromOperand(op)
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}
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func labelFromOperand(op *ast.Operand) string {
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if op.Addr.Sym != nil {
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return op.Addr.Sym.Name
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}
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return op.Raw
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}
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