105 lines
4.8 KiB
Markdown
105 lines
4.8 KiB
Markdown
# RISC-V 64
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Layer 1, target page. Verified against `go tool asm` of Go 1.27.1, against
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the toolchain's own riscv64 assembler manual (`cmd/internal/obj/riscv/doc.go`)
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and against gasm's encoder, whose output is compared byte for byte with the
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toolchain's. The complete mnemonic inventory lives in the generated appendix
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[INSTRUCTIONS-RISCV64.md](INSTRUCTIONS-RISCV64.md).
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## Registers
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- Integer: `X0` to `X31`. `X0` is hardwired zero. Three names the toolchain
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constrains: `X4` must be written through its ABI name `TP`; `X27`, the
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goroutine pointer, must be written `g` and may not be written `S11`; in
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shared builds `X3` is off limits and must be written `GP`.
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- The other integer registers may be written `Xn` or by their ABI names
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(`A0`, `T0`, `S1`, and so on).
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- Floating point: `F0` to `F31`. Vector: `V0` to `V31`.
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- `X26` is the closure pointer and `X31` is the assembler's own scratch
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register: its value may be clobbered by instruction sequences the
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assembler inserts, so hand-written code must not rely on it.
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- There is no reserved frame pointer register on this target.
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## Operand order
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The ordering differs from the ISA manual, and per instruction class:
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- **R-type** is reversed: `ADD X10, X11, X12` is `add x12, x11, x10`.
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- **I-type arithmetic** keeps that shape with the immediate first:
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`ADDI $1, X11, X12`.
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- **Loads and stores** are source first, like every Plan 9 dialect:
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`MOV 16(X2), X10` loads and `MOV X10, (X2)` stores. The MOV series hides
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the width; `MOVB` through `MOVD` spell it out.
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- **Branches** keep the ISA order: `BLT X12, X23, loop1`, which jumps when
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X12 < X23, the reverse of the SLT operand order.
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- **FMA** is rotated one place left so the destination comes last:
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`FMADDS F1, F2, F3, F4`.
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- **AMO** is likewise rotated: `AMOSWAPW X5, (X6), X7`.
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- **Ternary abbreviation** is supported and encouraged: `ADD X10, X12` means
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`ADD X10, X12, X12`.
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Where an R-type instruction has an I-type sibling, the assembler picks the
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immediate form from the operand: `AND $3, X12, X13` assembles as `ANDI`.
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## Names, suffixes and rounding
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Dots are removed and suffixes are upper-cased: the ISA's `fmv.w.x` is
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`FMVWX`. Floating-point rounding modes become suffixes, `FCVTLUS.RNE F0,
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X5`, with RTZ assumed when the suffix is omitted; the toolchain never sets
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the FCSR.
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## Constants
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- `MOV` materialises any 64-bit integer constant, synthesising it from a
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few arithmetic instructions where possible and otherwise loading it from
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a literal pool in the binary.
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- A 32-bit constant is accepted by `ADDI`, `ANDI`, `ORI` and `XORI`, and
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the assembler synthesises values that exceed the 12-bit encoding window.
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- `MOVF` and `MOVD` materialise floating-point constants, encoding them as
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`FLW` and `FLD` from a pool location unless the constant is exactly 0.0.
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## Extensions and profiles
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The default target profile is rva20u64, selected or raised with the
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GORISCV64 environment variable. A short list of instructions outside the
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default profile is synthesised by the assembler when the profile does not
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provide them, so they are safe without guards: `ANDN`, `MAX`, `MAXU`, `MIN`,
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`MINU`, `MOVB`, `MOVH`, `MOVHU`, `MOVWU`, `ORN`, `ROL`, `ROLW`, `ROR`,
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`RORI`, `RORIW`, `RORW`, `XNOR`. The header `asm_riscv64.h` defines the
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`hasZba`, `hasZbb`, `hasZbs` and `hasV` macros for guarding everything else.
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## Fences and atomics
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`FENCE` takes predecessor and successor sets in that order, uppercase
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letters, `FENCE R, RW`; a bare `FENCE` is a full fence, as is
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`FENCE IORW, IORW`. `FENCE.TSO` exists. The ordering bits of `LR`, `SC`
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and the AMO instructions are not specifiable in source: the assembler sets
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acquire and release on the AMO instructions, acquire on `LR` and release on
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`SC`, always.
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## Compressed instructions
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The assembler converts 32-bit instructions to their compressed encodings
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automatically; the conversion is a property of the emitted machine code, not
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of the source, and register choice influences how much compresses.
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Hand-writing compressed instructions in source is accepted but discouraged.
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The debug flag `compressinstructions=0` turns the automatic conversion off.
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## Vector extension
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`VSETVLI` writes its vtype components in uppercase with the destination
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last: `VSETVLI X10, E8, M1, TU, MU, X12`. Vector loads and stores are
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source first like the scalar ones, with an optional stride or index register
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second and the mask register, when present, always penultimate:
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`VLE8V (X10), V3`, `VLE8V (X10), V0, V3` for the masked form. Vector
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arithmetic reverses its operands, `VADDVV V1, V2, V3`, with the mask again
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penultimate.
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## Relocations
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`R_RISCV_JAL`, `R_RISCV_CALL`, the `R_RISCV_PCREL_ITYPE` and `STYPE` pairs,
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`R_RISCV_BRANCH`, the compressed branch and jump forms, the TLS and GOT
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families and `R_RISCV_ADD32` and `SUB32`, all specified in
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[GOOBJ.md](../GOOBJ.md). The assembler always emits the four-byte
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`R_DWTXTADDR_U4` flavour inside its DWARF records.
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