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petrbalvin 8a36af7c7d docs(asm): generate the instruction appendices

Assisted-by: GLM 5.3 Flash

2026-09-21 20:15:55 +02:00

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ARM64: instruction inventory

Generated by gasm-devkit's _gen from the Go toolchain's instruction table (cmd/internal/obj/arm64/anames.go, go1.27.1); DO NOT EDIT. This page lists every mnemonic go tool asm accepts on this target, which is the upper bound of the language on it: a name absent here is not an instruction of the target, and a name present here may still be one gasm's encoder cannot emit yet.

The inventory carries no per-mnemonic encoder column: on this target encodability is decided per operand shape, and the live measured coverage is reported by gasm audit-instructions.

Mnemonic	Notes
`CALL`
`DUFFCOPY`
`DUFFZERO`
`END`
`FUNCDATA`
`GETCALLERPC`
`JMP`
`NOP`	No operation
`PCALIGN`
`PCALIGNMAX`
`PCDATA`
`RET`	Return
`TEXT`
`UNDEF`
`ADC`	ADC (64-bit)
`ADCS`	ADCS (64-bit)
`ADCSW`	ADCS (32-bit)
`ADCW`	ADC (32-bit)
`ADD`	ADD (64-bit)
`ADDS`	ADDS (64-bit)
`ADDSW`	ADDS (32-bit)
`ADDW`	ADD (32-bit)
`ADR`	Address of label/page
`ADRP`	Address of label/page
`AESD`	AES round
`AESE`	AES round
`AESIMC`	AES round
`AESMC`	AES round
`AND`	AND (64-bit)
`ANDS`	ANDS (64-bit)
`ANDSW`	ANDS (32-bit)
`ANDW`	AND (32-bit)
`ASR`	ASR shift
`ASRW`	ASR shift (32-bit)
`AT`
`AUTIA1716`
`AUTIASP`
`AUTIB1716`
`AUTIBSP`
`BCC`	Conditional branch
`BCS`	Conditional branch
`BEQ`	Conditional branch
`BFI`
`BFIW`
`BFM`
`BFMW`
`BFXIL`	Bitfield extract
`BFXILW`
`BGE`	Conditional branch
`BGT`	Conditional branch
`BHI`	Conditional branch
`BHS`	Conditional branch
`BIC`	BIC (64-bit)
`BICS`	BICS (64-bit)
`BICSW`	BICS (32-bit)
`BICW`	BIC (32-bit)
`BLE`	Conditional branch
`BLO`	Conditional branch
`BLS`	Conditional branch
`BLT`	Conditional branch
`BMI`	Conditional branch
`BNE`	Conditional branch
`BPL`	Conditional branch
`BRK`	Breakpoint
`BTI`
`BVC`	Conditional branch
`BVS`	Conditional branch
`CASAD`
`CASALB`
`CASALD`
`CASALH`
`CASALW`
`CASAW`
`CASB`
`CASD`
`CASH`
`CASLD`
`CASLW`
`CASPD`
`CASPW`
`CASW`
`CBNZ`	Compare/test and branch
`CBNZW`	Compare/test and branch (32-bit)
`CBZ`	Compare/test and branch
`CBZW`	Compare/test and branch (32-bit)
`CCMN`	Conditional compare
`CCMNW`	Conditional compare
`CCMP`	Conditional compare
`CCMPW`	Conditional compare
`CINC`	Conditional select
`CINCW`	Conditional select (32-bit)
`CINV`	Conditional select
`CINVW`	Conditional select (32-bit)
`CLREX`
`CLS`	Bit manipulation
`CLSW`	Bit manipulation
`CLZ`	Bit manipulation
`CLZW`	Bit manipulation
`CMN`	CMN (64-bit)
`CMNW`	CMN (32-bit)
`CMP`	CMP (64-bit)
`CMPW`	CMP (32-bit)
`CNEG`	Conditional select
`CNEGW`	Conditional select (32-bit)
`CRC32B`
`CRC32CB`
`CRC32CH`
`CRC32CW`
`CRC32CX`
`CRC32H`
`CRC32W`
`CRC32X`
`CSEL`	Conditional select
`CSELW`	Conditional select (32-bit)
`CSET`	Conditional select
`CSETM`	Conditional select
`CSETMW`	Conditional select (32-bit)
`CSETW`	Conditional select (32-bit)
`CSINC`	Conditional select
`CSINCW`	Conditional select (32-bit)
`CSINV`	Conditional select
`CSINVW`	Conditional select (32-bit)
`CSNEG`	Conditional select
`CSNEGW`	Conditional select (32-bit)
`DC`	Data cache maintenance
`DCPS1`
`DCPS2`
`DCPS3`
`DMB`	Barrier
`DRPS`
`DSB`	Barrier
`DWORD`
`EON`	EON (64-bit)
`EONW`	EON (32-bit)
`EOR`	EOR (64-bit)
`EORW`	EOR (32-bit)
`ERET`
`EXTR`	Bitfield extract
`EXTRW`
`FABSD`
`FABSS`
`FADDD`
`FADDS`
`FCCMPD`
`FCCMPED`
`FCCMPES`
`FCCMPS`
`FCMPD`
`FCMPED`
`FCMPES`
`FCMPS`
`FCSELD`
`FCSELS`
`FCVTDH`
`FCVTDS`
`FCVTHD`
`FCVTHS`
`FCVTSD`
`FCVTSH`
`FCVTZSD`
`FCVTZSDW`
`FCVTZSS`
`FCVTZSSW`
`FCVTZUD`
`FCVTZUDW`
`FCVTZUS`
`FCVTZUSW`
`FDIVD`
`FDIVS`
`FLDPD`	Register-pair load or store
`FLDPQ`
`FLDPS`
`FMADDD`
`FMADDS`
`FMAXD`
`FMAXNMD`
`FMAXNMS`
`FMAXS`
`FMIND`
`FMINNMD`
`FMINNMS`
`FMINS`
`FMOVD`	Move / load / store
`FMOVQ`
`FMOVS`	Move / load / store
`FMSUBD`
`FMSUBS`
`FMULD`
`FMULS`
`FNEGD`
`FNEGS`
`FNMADDD`
`FNMADDS`
`FNMSUBD`
`FNMSUBS`
`FNMULD`
`FNMULS`
`FRINTAD`
`FRINTAS`
`FRINTID`
`FRINTIS`
`FRINTMD`
`FRINTMS`
`FRINTND`
`FRINTNS`
`FRINTPD`
`FRINTPS`
`FRINTXD`
`FRINTXS`
`FRINTZD`
`FRINTZS`
`FSQRTD`
`FSQRTS`
`FSTPD`	Register-pair load or store
`FSTPQ`
`FSTPS`
`FSUBD`
`FSUBS`
`HINT`
`HLT`
`HVC`	Exception generation
`IC`
`ISB`	Barrier
`LDADDAB`
`LDADDAD`
`LDADDAH`
`LDADDALB`
`LDADDALD`
`LDADDALH`
`LDADDALW`
`LDADDAW`
`LDADDB`
`LDADDD`
`LDADDH`
`LDADDLB`
`LDADDLD`
`LDADDLH`
`LDADDLW`
`LDADDW`
`LDAR`	Atomic memory operation
`LDARB`	Atomic memory operation
`LDARH`	Atomic memory operation
`LDARW`	Atomic memory operation
`LDAXP`
`LDAXPW`
`LDAXR`	Atomic memory operation
`LDAXRB`	Atomic memory operation
`LDAXRH`	Atomic memory operation
`LDAXRW`	Atomic memory operation
`LDCLRAB`
`LDCLRAD`
`LDCLRAH`
`LDCLRALB`
`LDCLRALD`
`LDCLRALH`
`LDCLRALW`
`LDCLRAW`
`LDCLRB`
`LDCLRD`
`LDCLRH`
`LDCLRLB`
`LDCLRLD`
`LDCLRLH`
`LDCLRLW`
`LDCLRW`
`LDEORAB`
`LDEORAD`
`LDEORAH`
`LDEORALB`
`LDEORALD`
`LDEORALH`
`LDEORALW`
`LDEORAW`
`LDEORB`
`LDEORD`
`LDEORH`
`LDEORLB`
`LDEORLD`
`LDEORLH`
`LDEORLW`
`LDEORW`
`LDORAB`
`LDORAD`
`LDORAH`
`LDORALB`
`LDORALD`
`LDORALH`
`LDORALW`
`LDORAW`
`LDORB`
`LDORD`
`LDORH`
`LDORLB`
`LDORLD`
`LDORLH`
`LDORLW`
`LDORW`
`LDP`	Register-pair load or store
`LDPSW`
`LDPW`	Register-pair load or store
`LDXP`
`LDXPW`
`LDXR`
`LDXRB`
`LDXRH`
`LDXRW`
`LSL`	LSL shift
`LSLW`	LSL shift (32-bit)
`LSR`	LSR shift
`LSRW`	LSR shift (32-bit)
`MADD`	Multiply / multiply-accumulate
`MADDW`
`MNEG`	Multiply / multiply-accumulate
`MNEGW`
`MOVB`	Move / load / store
`MOVBU`	Move / load / store
`MOVD`	Move / load / store
`MOVH`	Move / load / store
`MOVHU`	Move / load / store
`MOVK`	Move wide constant
`MOVKW`	Move wide constant
`MOVN`	Move wide constant
`MOVNW`	Move wide constant
`MOVP`
`MOVPD`
`MOVPQ`
`MOVPS`
`MOVPSW`
`MOVPW`
`MOVW`	Move / load / store
`MOVWU`	Move / load / store
`MOVZ`	Move wide constant
`MOVZW`	Move wide constant
`MRS`	System register access
`MSR`	System register access
`MSUB`	Multiply / multiply-accumulate
`MSUBW`
`MUL`	Multiply / multiply-accumulate
`MULW`
`MVN`	MVN (64-bit)
`MVNW`	MVN (32-bit)
`NEG`	NEG (64-bit)
`NEGS`
`NEGSW`
`NEGW`	NEG (32-bit)
`NGC`	NGC (64-bit)
`NGCS`
`NGCSW`
`NGCW`	NGC (32-bit)
`NOOP`
`ORN`	ORN (64-bit)
`ORNW`	ORN (32-bit)
`ORR`	ORR (64-bit)
`ORRW`	ORR (32-bit)
`PACIASP`
`PACIBSP`
`PRFM`	Memory prefetch
`PRFUM`
`RBIT`	Bit manipulation
`RBITW`	Bit manipulation
`REM`
`REMW`
`REV`	Bit manipulation
`REV16`	Bit manipulation
`REV16W`
`REV32`	Bit manipulation
`REVW`	Bit manipulation
`ROR`	ROR shift
`RORW`	ROR shift (32-bit)
`SBC`	SBC (64-bit)
`SBCS`	SBCS (64-bit)
`SBCSW`	SBCS (32-bit)
`SBCW`	SBC (32-bit)
`SBFIZ`
`SBFIZW`
`SBFM`	Bitfield extract
`SBFMW`
`SBFX`	Bitfield extract
`SBFXW`
`SCVTFD`
`SCVTFS`
`SCVTFWD`
`SCVTFWS`
`SDIV`	Divide
`SDIVW`	Divide
`SEV`
`SEVL`
`SHA1C`	SHA round
`SHA1H`	SHA round
`SHA1M`	SHA round
`SHA1P`	SHA round
`SHA1SU0`	SHA round
`SHA1SU1`	SHA round
`SHA256H`	SHA round
`SHA256H2`	SHA round
`SHA256SU0`	SHA round
`SHA256SU1`	SHA round
`SHA512H`	SHA round
`SHA512H2`	SHA round
`SHA512SU0`	SHA round
`SHA512SU1`	SHA round
`SMADDL`	Multiply / multiply-accumulate
`SMC`	Exception generation
`SMNEGL`
`SMSUBL`	Multiply / multiply-accumulate
`SMULH`	Multiply / multiply-accumulate
`SMULL`	Multiply / multiply-accumulate
`STLR`	Atomic memory operation
`STLRB`	Atomic memory operation
`STLRH`	Atomic memory operation
`STLRW`	Atomic memory operation
`STLXP`
`STLXPW`
`STLXR`
`STLXRB`
`STLXRH`
`STLXRW`
`STP`	Register-pair load or store
`STPW`	Register-pair load or store
`STXP`
`STXPW`
`STXR`	Atomic memory operation
`STXRB`	Atomic memory operation
`STXRH`	Atomic memory operation
`STXRW`	Atomic memory operation
`SUB`	SUB (64-bit)
`SUBS`	SUBS (64-bit)
`SUBSW`	SUBS (32-bit)
`SUBW`	SUB (32-bit)
`SVC`	Exception generation
`SWPAB`
`SWPAD`
`SWPAH`
`SWPALB`
`SWPALD`
`SWPALH`
`SWPALW`
`SWPAW`
`SWPB`
`SWPD`
`SWPH`
`SWPLB`
`SWPLD`
`SWPLH`
`SWPLW`
`SWPW`
`SXTB`
`SXTBW`
`SXTH`
`SXTHW`
`SXTW`
`SYS`
`SYSL`
`TBNZ`	Compare/test and branch
`TBZ`	Compare/test and branch
`TLBI`
`TST`	TST (64-bit)
`TSTW`	TST (32-bit)
`UBFIZ`
`UBFIZW`
`UBFM`	Bitfield extract
`UBFMW`
`UBFX`	Bitfield extract
`UBFXW`
`UCVTFD`
`UCVTFS`
`UCVTFWD`
`UCVTFWS`
`UDIV`	Divide
`UDIVW`	Divide
`UMADDL`	Multiply / multiply-accumulate
`UMNEGL`
`UMSUBL`	Multiply / multiply-accumulate
`UMULH`	Multiply / multiply-accumulate
`UMULL`	Multiply / multiply-accumulate
`UREM`
`UREMW`
`UXTB`
`UXTBW`
`UXTH`
`UXTHW`
`UXTW`
`VADD`	NEON SIMD vector operation
`VADDP`
`VADDV`	NEON SIMD vector operation
`VAND`	NEON SIMD vector operation
`VBCAX`	Three-way XOR / rotate crypto vector operation
`VBIF`	NEON SIMD vector operation
`VBIT`
`VBSL`	NEON SIMD vector operation
`VCMEQ`
`VCMTST`
`VCNT`	NEON SIMD vector operation
`VDUP`	NEON SIMD vector operation
`VEOR`	NEON SIMD vector operation
`VEOR3`	Three-way XOR / rotate crypto vector operation
`VEXT`	NEON SIMD vector operation
`VFMLA`	NEON SIMD vector operation
`VFMLS`	NEON SIMD vector operation
`VLD1`	NEON SIMD vector operation
`VLD1R`
`VLD2`	NEON SIMD vector operation
`VLD2R`
`VLD3`	NEON SIMD vector operation
`VLD3R`
`VLD4`	NEON SIMD vector operation
`VLD4R`
`VMOV`	NEON SIMD vector operation
`VMOVD`
`VMOVI`	NEON SIMD vector operation
`VMOVQ`	NEON SIMD vector operation
`VMOVS`
`VORR`	NEON SIMD vector operation
`VPMULL`
`VPMULL2`
`VRAX1`	Three-way XOR / rotate crypto vector operation
`VRBIT`
`VREV16`	NEON SIMD vector operation
`VREV32`	NEON SIMD vector operation
`VREV64`	NEON SIMD vector operation
`VSHL`	NEON SIMD vector operation
`VSLI`
`VSRI`
`VST1`	NEON SIMD vector operation
`VST2`	NEON SIMD vector operation
`VST3`	NEON SIMD vector operation
`VST4`	NEON SIMD vector operation
`VSUB`	NEON SIMD vector operation
`VTBL`	NEON SIMD vector operation
`VTBX`	NEON SIMD vector operation
`VTRN1`	NEON SIMD vector operation
`VTRN2`	NEON SIMD vector operation
`VUADDLV`
`VUADDW`
`VUADDW2`
`VUMAX`
`VUMIN`
`VUSHLL`
`VUSHLL2`
`VUSHR`	NEON SIMD vector operation
`VUSRA`
`VUXTL`
`VUXTL2`
`VUZP1`	NEON SIMD vector operation
`VUZP2`	NEON SIMD vector operation
`VXAR`	Three-way XOR / rotate crypto vector operation
`VZIP1`	NEON SIMD vector operation
`VZIP2`	NEON SIMD vector operation
`WFE`
`WFI`
`WORD`
`YIELD`
`B`	Unconditional branch
`BL`	Branch with link

Recognised: 554 mnemonics.

13 KiB Raw Blame History

ARM64: instruction inventory

13 KiB

Raw Blame History