feat(asm): encode the legacy amd64 SSE and MMX families
The packed integer and float binaries, the imm8-controlled SSE4.1 forms, the variable blends with their X0 mask, the high/low half moves, the sign-mask extractions, the non-temporal stores, the MOVQ bank crossings and their odd spellings, the MMX shifts and shuffle and the cache-line mask stores, plus the scalar leaves LEAVE, INVPCID and the RTM controls. Every encoding is pinned byte for byte against go tool asm through every corpus line the toolchain's own amd64enc.s carries for the families (1465 lines). Two corpus-wide gaps fell out of the comparison: the 64-bit MOV immediate uses the zero-extending form across the unsigned 32-bit span, and the MMX-to-GPR MOVQ puts the bank register in reg. Assisted-by: GLM 5.3 Flash
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@@ -19,6 +19,9 @@ func (e *enc) encodeAmd64Family(upper string, ops []Operand) (bool, error) {
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if ok, err := e.encodeXsave(upper, ops); ok {
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return true, err
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}
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if ok, err := e.encodeSSEMore(upper, ops); ok {
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return true, err
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}
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return false, nil
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}
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@@ -91,6 +94,9 @@ func amd64FamilyEncodable(upper string) bool {
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if upper == "CMPXCHG8B" || upper == "CMPXCHG16B" {
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return true
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}
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if upper == "INVPCID" || upper == "XABORT" {
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return true
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}
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if _, ok := xsaveTable[upper]; ok {
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return true
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}
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@@ -99,5 +105,18 @@ func amd64FamilyEncodable(upper string) bool {
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return true
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}
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}
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switch upper {
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case "EMMS", "PSHUFW", "PSLLO", "PSRLO", "PMOVMSKB", "MOVQOZX", "MOVZWW", "MOVSWW":
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return true
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}
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if _, ok := sseMaskmov[upper]; ok {
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return true
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}
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if _, ok := mmxShiftImm[upper]; ok {
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return true
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}
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if _, ok := mmxShiftVar[upper]; ok {
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return true
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}
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return false
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}
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@@ -0,0 +1,566 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import "fmt"
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// This file implements the amd64 SIMD pieces the main tables lack: the MMX
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// bank glue (EMMS, the masked stores, the MMX shifts and shuffle, the
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// byte-mask extract), the MOVQ bank crossings' odd spellings and the leaf
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// aliases. Every encoding here is pinned byte for byte against go tool asm
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// through the corpus lines in amd64_sse_test.go.
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// sseMaskmov maps the masked cache-line stores to their prefix and opcode:
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// OP src, dst with the second operand in the reg field, no memory operand.
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var sseMaskmov = map[string]sseBin{
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"MASKMOVQ": {0, 0xF7, false},
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"MASKMOVOU": {0x66, 0xF7, false},
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}
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// sseMoreBin maps the packed and scalar legacy binaries the main table
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// lacks, reg = destination and r/m = source: the float comparisons, square
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// roots and reciprocal estimates, the SSE3 horizontal arithmetic, the SSE4.1
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// packed integers and the SSSE3 sign and horizontal ops. The MMX twins of
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// the 0x66-prefixed members drop the prefix in the shared encoder.
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var sseMoreBin = map[string]sseBin{
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"COMISS": {0, 0x2F, false},
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"UCOMISS": {0, 0x2E, false},
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"UCOMISD": {0x66, 0x2E, false},
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"SQRTPS": {0, 0x51, false},
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"SQRTPD": {0x66, 0x51, false},
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"SQRTSS": {0xF3, 0x51, false},
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"RCPPS": {0, 0x53, false},
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"RCPSS": {0xF3, 0x53, false},
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"RSQRTPS": {0, 0x52, false},
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"RSQRTSS": {0xF3, 0x52, false},
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"ADDSUBPD": {0x66, 0xD0, false},
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"ADDSUBPS": {0xF2, 0xD0, false},
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"HADDPD": {0x66, 0x7C, false},
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"HADDPS": {0xF2, 0x7C, false},
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"HSUBPD": {0x66, 0x7D, false},
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"HSUBPS": {0xF2, 0x7D, false},
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"MOVDDUP": {0xF2, 0x12, false},
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"MOVSHDUP": {0xF3, 0x16, false},
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"MOVSLDUP": {0xF3, 0x12, false},
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"LDDQU": {0xF2, 0xF0, false},
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"MOVNTDQA": {0x66, 0x2A, true},
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"PTEST": {0x66, 0x17, true},
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"PABSB": {0x66, 0x1C, true},
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"PABSW": {0x66, 0x1D, true},
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"PABSD": {0x66, 0x1E, true},
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"PACKSSWB": {0x66, 0x63, false},
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"PACKUSWB": {0x66, 0x67, false},
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"PACKSSLW": {0x66, 0x6B, false},
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"PACKUSDW": {0x66, 0x2B, true},
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"PADDSB": {0x66, 0xEC, false},
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"PADDSW": {0x66, 0xED, false},
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"PADDUSB": {0x66, 0xDC, false},
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"PADDUSW": {0x66, 0xDD, false},
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"PAVGB": {0x66, 0xE0, false},
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"PAVGW": {0x66, 0xE3, false},
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"PCMPEQQ": {0x66, 0x29, true},
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"PCMPGTQ": {0x66, 0x37, true},
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"PHADDW": {0x66, 0x01, true},
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"PHADDD": {0x66, 0x02, true},
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"PHADDSW": {0x66, 0x03, true},
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"PHSUBW": {0x66, 0x05, true},
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"PHSUBD": {0x66, 0x06, true},
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"PHSUBSW": {0x66, 0x07, true},
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"PHMINPOSUW": {0x66, 0x41, true},
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"PMADDUBSW": {0x66, 0x04, true},
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"PMADDWL": {0x66, 0xF5, false},
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"PMAXSB": {0x66, 0x3C, true},
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"PMAXSD": {0x66, 0x3D, true},
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"PMAXSW": {0x66, 0xEE, false},
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"PMAXUB": {0x66, 0xDE, false},
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"PMAXUD": {0x66, 0x3F, true},
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"PMAXUW": {0x66, 0x3E, true},
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"PMINSB": {0x66, 0x38, true},
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"PMINSD": {0x66, 0x39, true},
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"PMINSW": {0x66, 0xEA, false},
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"PMINUB": {0x66, 0xDA, false},
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"PMINUD": {0x66, 0x3B, true},
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"PMINUW": {0x66, 0x3A, true},
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"PMULDQ": {0x66, 0x28, true},
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"PMULLD": {0x66, 0x40, true},
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"PMULHRSW": {0x66, 0x0B, true},
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"PMULHUW": {0x66, 0xE4, false},
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"PMULHW": {0x66, 0xE5, false},
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"PMULLW": {0x66, 0xD5, false},
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"PMULULQ": {0x66, 0xF4, false},
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"PCMPGTL": {0x66, 0x66, false},
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"PMOVSXBD": {0x66, 0x21, true},
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"PMOVSXBQ": {0x66, 0x22, true},
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"PMOVSXBW": {0x66, 0x20, true},
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"PMOVSXDQ": {0x66, 0x25, true},
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"PMOVSXWD": {0x66, 0x23, true},
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"PMOVSXWQ": {0x66, 0x24, true},
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"PMOVZXBD": {0x66, 0x31, true},
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"PMOVZXBQ": {0x66, 0x32, true},
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"PMOVZXBW": {0x66, 0x30, true},
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"PMOVZXDQ": {0x66, 0x35, true},
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"PMOVZXWD": {0x66, 0x33, true},
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"PMOVZXWQ": {0x66, 0x34, true},
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// The conversion aliases the Plan 9 table spells with an L: the dword
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// sources and destinations of the packed integer/float converts.
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"CVTPL2PD": {0xF3, 0xE6, false},
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"CVTPL2PS": {0, 0x5B, false},
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"CVTPD2PL": {0xF2, 0xE6, false},
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"CVTPS2PL": {0x66, 0x5B, false},
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"CVTTPD2PL": {0x66, 0xE6, false},
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"CVTTPS2PL": {0xF3, 0x5B, false},
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"PSADBW": {0x66, 0xF6, false},
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"PSUBSB": {0x66, 0xE8, false},
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"PSUBSW": {0x66, 0xE9, false},
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"PSUBUSB": {0x66, 0xD8, false},
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"PSUBUSW": {0x66, 0xD9, false},
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"PSIGNB": {0x66, 0x08, true},
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"PSIGNW": {0x66, 0x09, true},
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"PSIGND": {0x66, 0x0A, true},
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"PUNPCKHBW": {0x66, 0x68, false},
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"PUNPCKHLQ": {0x66, 0x6A, false},
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"PUNPCKHQDQ": {0x66, 0x6D, false},
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"PUNPCKHWL": {0x66, 0x69, false},
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"PUNPCKLLQ": {0x66, 0x62, false},
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"PUNPCKLQDQ": {0x66, 0x6C, false},
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"PUNPCKLWL": {0x66, 0x61, false},
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}
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// sseMoreImm3 maps the imm8-controlled three-operand instructions the main
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// table lacks: OP $imm, src, dst.
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var sseMoreImm3 = map[string]sseImm3{
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"ROUNDPS": {0x66, 0x08, true},
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"ROUNDPD": {0x66, 0x09, true},
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"ROUNDSS": {0x66, 0x0A, true},
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"ROUNDSD": {0x66, 0x0B, true},
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"DPPS": {0x66, 0x40, true},
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"DPPD": {0x66, 0x41, true},
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"BLENDPS": {0x66, 0x0C, true},
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"BLENDPD": {0x66, 0x0D, true},
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"INSERTPS": {0x66, 0x21, true},
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"MPSADBW": {0x66, 0x42, true},
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"PCMPESTRM": {0x66, 0x60, true},
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"PCMPESTRI": {0x66, 0x61, true},
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"PCMPISTRM": {0x66, 0x62, true},
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"PCMPISTRI": {0x66, 0x63, true},
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}
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// sseBlendv maps the variable blends whose implicit mask is X0: the first
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// operand must be the literal X0, the register the hardware reads.
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var sseBlendv = map[string]sseBin{
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"BLENDVPS": {0x66, 0x14, true},
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"BLENDVPD": {0x66, 0x15, true},
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"PBLENDVB": {0x66, 0x10, true},
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}
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// sseHighLow maps the high/low half moves to their load/store opcode pair.
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// A memory source loads (reg = destination), a memory destination stores
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// (reg = the register source).
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var sseHighLow = map[string]sseMove{
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"MOVHPD": {0x66, 0x16, 0x17},
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"MOVHPS": {0, 0x16, 0x17},
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"MOVLPD": {0x66, 0x12, 0x13},
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"MOVLPS": {0, 0x12, 0x13},
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}
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// sseRegReg maps the register-to-register half moves, register destination
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// and register source alone: MOVHLPS and MOVLHPS.
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var sseRegReg = map[string]sseBin{
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"MOVHLPS": {0, 0x12, false},
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"MOVLHPS": {0, 0x16, false},
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}
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// sseMovmsk maps the sign-mask extractions to a GPR: OP vec, gpr.
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var sseMovmsk = map[string]sseBin{
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"MOVMSKPS": {0, 0x50, false},
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"MOVMSKPD": {0x66, 0x50, false},
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}
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// sseMovnt maps the non-temporal stores, OP reg, mem, plus MOVNTDQA's load
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// (which rides sseMoreBin).
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var sseMovnt = map[string]sseBin{
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"MOVNTPS": {0, 0x2B, false},
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"MOVNTPD": {0x66, 0x2B, false},
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"MOVNTQ": {0, 0xE7, false},
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"MOVNTO": {0x66, 0xE7, false},
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"MOVNTIL": {0, 0xC3, false},
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"MOVNTIQ": {0, 0xC3, false},
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}
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// mmxShiftImm lists the packed integer shifts whose immediate form the MMX
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// bank spells without the 0x66 prefix; the digit rides the 0F 71/72/73
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// group, the same /digits the XMM forms carry.
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var mmxShiftImm = map[string]sseShift{
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"PSLLW": {0x71, 6},
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"PSRLW": {0x71, 2},
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"PSRAW": {0x71, 4},
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"PSLLL": {0x72, 6},
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"PSRLL": {0x72, 2},
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"PSRAL": {0x72, 4},
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"PSLLQ": {0x73, 6},
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"PSRLQ": {0x73, 2},
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}
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// mmxShiftVar lists the variable-count forms over the MMX bank, the same
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// opcodes the XMM variable shifts ride, prefix dropped.
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var mmxShiftVar = map[string]byte{
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"PSLLW": 0xF1,
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"PSRLW": 0xD1,
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"PSRAW": 0xE1,
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"PSLLL": 0xF2,
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"PSRLL": 0xD2,
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"PSRAL": 0xE2,
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"PSLLQ": 0xF3,
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"PSRLQ": 0xD3,
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}
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// sseOctaShift lists the octa byte shifts' extra spellings: PSLLO and PSRLO
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// are the Plan 9 names of PSLLDQ/PSRLDQ, XMM only.
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var sseOctaShift = map[string]sseShift{
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"PSLLO": {0x73, 7},
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"PSRLO": {0x73, 3},
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}
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// isMmx reports whether the operand is an MMX register.
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func isMmx(op Operand) bool {
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r, ok := op.(Reg)
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return ok && r.mmx
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}
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// encodeSSEMore encodes the MMX glue and the leaf SIMD spellings. It
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// reports whether the mnemonic belongs to the layer; a false result hands
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// the mnemonic back to the caller.
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func (e *enc) encodeSSEMore(upper string, ops []Operand) (bool, error) {
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if upper == "EMMS" {
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if len(ops) != 0 {
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return true, fmt.Errorf("EMMS takes no operands, got %d", len(ops))
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}
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return true, e.emit(&instr{opcode: []byte{0x0F, 0x77}, modrm: -1, sib: -1})
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}
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if m, ok := sseMaskmov[upper]; ok {
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if len(ops) != 2 {
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return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
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}
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srcReg, ok1 := ops[0].(Reg)
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dstReg, ok2 := ops[1].(Reg)
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if !ok1 || !ok2 || !srcReg.isVec() && !srcReg.mmx || !dstReg.isVec() && !dstReg.mmx {
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return true, fmt.Errorf("%s takes two vector or MMX registers", upper)
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}
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i := &instr{prefix: m.prefix, opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1}
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if err := setRM(i, dstReg, srcReg, 8); err != nil {
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return true, err
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}
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return true, e.emit(i)
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}
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// The packed shifts over the MMX bank drop the 0x66 prefix the XMM forms
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// carry; only a shift name enters the MMX path, the XMM spellings of the
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// shifts and every other packed binary fall through to the main tables.
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if _, isShift := mmxShiftImm[upper]; isShift {
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if e.encodeMmxShiftGate(ops) {
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return e.encodeMmxShift(upper, ops)
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}
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} else if _, isVar := mmxShiftVar[upper]; isVar {
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if e.encodeMmxShiftGate(ops) {
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return e.encodeMmxShift(upper, ops)
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}
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}
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// PSHUFW is the MMX word shuffle, 0F 70 with no prefix: the XMM twins
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// (PSHUFD and friends) dispatch through the main shuffle table.
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if upper == "PSHUFW" {
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if len(ops) != 3 {
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return true, fmt.Errorf("PSHUFW expects 3 operands ($imm, src, dst), got %d", len(ops))
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}
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imm, ok := ops[0].(Imm)
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if !ok {
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return true, fmt.Errorf("PSHUFW needs an imm8 first operand")
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}
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immByte, err := imm8(int64(imm))
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if err != nil {
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return true, err
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}
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dstReg, ok2 := ops[2].(Reg)
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if !ok2 || !dstReg.mmx {
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return true, fmt.Errorf("PSHUFW destination must be an MMX register")
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}
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i := &instr{opcode: []byte{0x0F, 0x70}, modrm: -1, sib: -1}
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if err := setRM(i, dstReg, ops[1], 8); err != nil {
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return true, err
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}
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i.imm = []byte{immByte}
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return true, e.emit(i)
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}
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if spec, ok := sseOctaShift[upper]; ok {
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return e.encodeMmxShiftForm(upper, spec, 0x66, ops)
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}
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// The byte-mask extract over the MMX bank rides the same 0F D7 opcode
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// without the prefix; the XMM spelling falls through.
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if upper == "PMOVMSKB" && len(ops) == 2 {
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if srcReg, ok := ops[0].(Reg); ok && srcReg.mmx {
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dstReg, ok2 := ops[1].(Reg)
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if !ok2 || dstReg.isVec() || dstReg.mmx {
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return true, fmt.Errorf("%s destination must be a general register", upper)
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}
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i := newInstr(4, []byte{0x0F, 0xD7})
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if err := setRM(i, dstReg, srcReg, 4); err != nil {
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return true, err
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}
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return true, e.emit(i)
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}
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}
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// MOVQOZX is the octa-to-quad zero-extend load, F3 0F D6: an MMX or
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// memory source into an XMM destination, the MOVQ2DQ opcode.
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if upper == "MOVQOZX" {
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if len(ops) != 2 {
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return true, fmt.Errorf("MOVQOZX expects 2 operands, got %d", len(ops))
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}
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dstReg, ok := ops[1].(Reg)
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if !ok || !dstReg.isVec() {
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return true, fmt.Errorf("MOVQOZX destination must be an XMM register")
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}
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switch ops[0].(type) {
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case Reg, Mem, sbMem:
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default:
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return true, fmt.Errorf("MOVQOZX source must be an MMX register or memory")
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}
|
||||
i := &instr{prefix: 0xF3, opcode: []byte{0x0F, 0xD6}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, dstReg, ops[0], 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// MOVZWW and MOVSWW are the word zero/sign-extend moves under aliases:
|
||||
// the MOVWLZX and MOVWLSX opcodes carrying the word width's 0x66 prefix.
|
||||
switch upper {
|
||||
case "MOVZWW", "MOVSWW":
|
||||
op := []byte{0x0F, 0xB7}
|
||||
if upper == "MOVSWW" {
|
||||
op[1] = 0xBF
|
||||
}
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
dstReg, ok := ops[1].(Reg)
|
||||
if !ok {
|
||||
return true, fmt.Errorf("%s destination must be a register", upper)
|
||||
}
|
||||
i := newInstr(2, op)
|
||||
if err := setRM(i, dstReg, ops[0], 2); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// The packed and scalar binaries: reg = destination, r/m = source, the
|
||||
// shared encoder carrying the MMX prefix drop.
|
||||
if m, ok := sseMoreBin[upper]; ok {
|
||||
return true, e.encodeSSEBin(m, ops)
|
||||
}
|
||||
// The imm8-controlled instructions: OP $imm, src, dst.
|
||||
if m, ok := sseMoreImm3[upper]; ok {
|
||||
return true, e.encodeSSEImm3(m, ops)
|
||||
}
|
||||
// The variable blends with their implicit X0 mask: the first operand is
|
||||
// the literal X0, the register the encoding leaves out.
|
||||
if m, ok := sseBlendv[upper]; ok {
|
||||
if len(ops) != 3 {
|
||||
return true, fmt.Errorf("%s expects 3 operands (X0, src, dst), got %d", upper, len(ops))
|
||||
}
|
||||
x0, ok := ops[0].(Reg)
|
||||
if !ok || !x0.isVec() || x0.idx != 0 || x0.size != 16 {
|
||||
return true, fmt.Errorf("%s first operand must be X0", upper)
|
||||
}
|
||||
return true, e.encodeSSEBin(m, ops[1:])
|
||||
}
|
||||
// The high/low half moves split by direction: a memory source loads, a
|
||||
// memory destination stores, both two-operand.
|
||||
if m, ok := sseHighLow[upper]; ok {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
srcReg, srcVec := vecReg(ops[0])
|
||||
dstReg, dstVec := vecReg(ops[1])
|
||||
var op byte
|
||||
var reg Reg
|
||||
var rm Operand
|
||||
switch {
|
||||
case srcVec && isX86Mem(ops[1]):
|
||||
op, reg, rm = m.store, srcReg, ops[1]
|
||||
case dstVec && isX86Mem(ops[0]):
|
||||
op, reg, rm = m.load, dstReg, ops[0]
|
||||
default:
|
||||
return true, fmt.Errorf("%s takes one vector register and one memory operand", upper)
|
||||
}
|
||||
i := &instr{prefix: m.prefix, opcode: []byte{0x0F, op}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, reg, rm, 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// The register-to-register half moves.
|
||||
if m, ok := sseRegReg[upper]; ok {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
srcReg, srcVec := vecReg(ops[0])
|
||||
dstReg, dstVec := vecReg(ops[1])
|
||||
if !srcVec || !dstVec {
|
||||
return true, fmt.Errorf("%s takes two XMM registers", upper)
|
||||
}
|
||||
i := &instr{opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, dstReg, srcReg, 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// The sign-mask extractions: the vector source's sign bits pack into a
|
||||
// general register.
|
||||
if m, ok := sseMovmsk[upper]; ok {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
srcReg, srcVec := vecReg(ops[0])
|
||||
dstReg, ok := ops[1].(Reg)
|
||||
if !srcVec || !ok || dstReg.isVec() || dstReg.mmx {
|
||||
return true, fmt.Errorf("%s takes a vector register and a general register", upper)
|
||||
}
|
||||
i := &instr{prefix: m.prefix, opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, dstReg, srcReg, 4); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// The non-temporal stores: the register source rides reg, the memory
|
||||
// destination r/m; MOVNTIL/IQ store from a general register and MOVNTIQ
|
||||
// carries REX.W.
|
||||
if m, ok := sseMovnt[upper]; ok {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
var srcReg Reg
|
||||
switch r := ops[0].(type) {
|
||||
case Reg:
|
||||
if upper == "MOVNTIL" || upper == "MOVNTIQ" {
|
||||
if r.isVec() || r.mmx {
|
||||
return true, fmt.Errorf("%s source must be a general register", upper)
|
||||
}
|
||||
srcReg = r
|
||||
} else {
|
||||
if !r.isVec() && !r.mmx {
|
||||
return true, fmt.Errorf("%s source must be a vector or MMX register", upper)
|
||||
}
|
||||
srcReg = r
|
||||
}
|
||||
default:
|
||||
return true, fmt.Errorf("%s source must be a register", upper)
|
||||
}
|
||||
if !isX86Mem(ops[1]) {
|
||||
return true, fmt.Errorf("%s destination must be memory", upper)
|
||||
}
|
||||
i := &instr{prefix: m.prefix, opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1, rexW: upper == "MOVNTIQ"}
|
||||
if err := setRM(i, srcReg, ops[1], 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// EXTRACTPS is the lane extract to a GPR or memory, the PEXTR layout.
|
||||
if upper == "EXTRACTPS" {
|
||||
return true, e.encodeSSEExtract(sseExtract{op: []byte{0x0F, 0x3A, 0x17}}, ops)
|
||||
}
|
||||
// CVTSL2SS and CVTSQ2SS are the integer-to-scalar-single converts, the
|
||||
// CVTSL2SD pair's F3 twin: F3 0F 2A with reg = XMM destination, REX.W
|
||||
// on the quad source spelling.
|
||||
if upper == "CVTSL2SS" || upper == "CVTSQ2SS" {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
dstReg, ok := ops[1].(Reg)
|
||||
if !ok || !dstReg.isVec() {
|
||||
return true, fmt.Errorf("%s destination must be a vector register", upper)
|
||||
}
|
||||
i := newInstr(0, []byte{0x0F, 0x2A})
|
||||
i.rexW = upper == "CVTSQ2SS"
|
||||
i.prefix = 0xF3
|
||||
if err := setRM(i, dstReg, ops[0], 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
return false, nil
|
||||
}
|
||||
|
||||
// encodeMmxShiftGate reports whether the shift's destination operand is an
|
||||
// MMX register, the case the bank's own prefix-free forms cover.
|
||||
func (e *enc) encodeMmxShiftGate(ops []Operand) bool {
|
||||
if len(ops) != 2 {
|
||||
return false
|
||||
}
|
||||
dstReg, ok := ops[1].(Reg)
|
||||
return ok && dstReg.mmx
|
||||
}
|
||||
|
||||
// encodeMmxShift routes the MMX shift between its immediate form
|
||||
// (OP $imm, dst, the 0F 71/72/73 /digit group) and its variable-count form
|
||||
// (OP count, dst, the 0F D1-F3 row).
|
||||
func (e *enc) encodeMmxShift(upper string, ops []Operand) (bool, error) {
|
||||
if spec, ok := mmxShiftImm[upper]; ok {
|
||||
if _, isImm := ops[0].(Imm); isImm {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
immByte, err := imm8(int64(ops[0].(Imm)))
|
||||
if err != nil {
|
||||
return true, err
|
||||
}
|
||||
i := &instr{opcode: []byte{0x0F, spec.op}, modrm: -1, sib: -1}
|
||||
if err := setRMDigit(i, spec.digit, ops[1], 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
i.imm = []byte{immByte}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
}
|
||||
if op, ok := mmxShiftVar[upper]; ok {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
if !vecOrMem(ops[0]) && !isMmx(ops[0]) {
|
||||
return true, fmt.Errorf("%s count must be an immediate, an MMX register or memory", upper)
|
||||
}
|
||||
dstReg, ok := ops[1].(Reg)
|
||||
if !ok || !dstReg.mmx {
|
||||
return true, fmt.Errorf("%s destination must be an MMX register", upper)
|
||||
}
|
||||
i := &instr{opcode: []byte{0x0F, op}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, dstReg, ops[0], 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
return true, fmt.Errorf("unsupported instruction %q", upper)
|
||||
}
|
||||
|
||||
// encodeMmxShiftForm emits one XMM octa shift: OP $imm, dst, the 0x66
|
||||
// prefix carried.
|
||||
func (e *enc) encodeMmxShiftForm(upper string, spec sseShift, prefix byte, ops []Operand) (bool, error) {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
|
||||
}
|
||||
imm, ok := ops[0].(Imm)
|
||||
if !ok {
|
||||
return true, fmt.Errorf("%s needs an immediate count", upper)
|
||||
}
|
||||
immByte, err := imm8(int64(imm))
|
||||
if err != nil {
|
||||
return true, err
|
||||
}
|
||||
dstReg, ok2 := ops[1].(Reg)
|
||||
if !ok2 || !dstReg.isVec() {
|
||||
return true, fmt.Errorf("%s destination must be the second, vector operand", upper)
|
||||
}
|
||||
i := &instr{prefix: prefix, opcode: []byte{0x0F, spec.op}, modrm: -1, sib: -1}
|
||||
if err := setRMDigit(i, spec.digit, dstReg, 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
i.imm = []byte{immByte}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -53,6 +53,10 @@ var systemNoOperand = map[string][]byte{
|
||||
"SYSEXIT": {0x0F, 0x35},
|
||||
"SYSEXIT64": {0x48, 0x0F, 0x35},
|
||||
"SYSRET": {0x0F, 0x07},
|
||||
"LEAVE": {0xC9},
|
||||
"LEAVEQ": {0xC9},
|
||||
"XEND": {0x0F, 0x01, 0xD5},
|
||||
"XTEST": {0x0F, 0x01, 0xD6},
|
||||
"CBW": {0x66, 0x98},
|
||||
"CWDE": {0x98},
|
||||
"CDQE": {0x48, 0x98},
|
||||
@@ -253,6 +257,40 @@ func (e *enc) encodeSystem(upper string, ops []Operand) (bool, error) {
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// INVPCID invalidates a translation-cache entry: 66 0F38 82 with the
|
||||
// type in a general register and the descriptor in memory.
|
||||
if upper == "INVPCID" {
|
||||
if len(ops) != 2 {
|
||||
return true, fmt.Errorf("INVPCID expects 2 operands, got %d", len(ops))
|
||||
}
|
||||
if !isX86Mem(ops[0]) {
|
||||
return true, fmt.Errorf("INVPCID requires a memory descriptor first")
|
||||
}
|
||||
srcReg, ok := ops[1].(Reg)
|
||||
if !ok || srcReg.isVec() {
|
||||
return true, fmt.Errorf("INVPCID: the second operand must be a general register")
|
||||
}
|
||||
i := &instr{prefix: 0x66, opcode: []byte{0x0F, 0x38, 0x82}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, srcReg, ops[0], 8); err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(i)
|
||||
}
|
||||
// XABORT carries its imm8 status byte in the C6 F8 group form.
|
||||
if upper == "XABORT" {
|
||||
if len(ops) != 1 {
|
||||
return true, fmt.Errorf("XABORT expects 1 immediate operand, got %d", len(ops))
|
||||
}
|
||||
imm, ok := ops[0].(Imm)
|
||||
if !ok {
|
||||
return true, fmt.Errorf("XABORT requires an immediate")
|
||||
}
|
||||
immByte, err := imm8(int64(imm))
|
||||
if err != nil {
|
||||
return true, err
|
||||
}
|
||||
return true, e.emit(&instr{opcode: []byte{0xC6, 0xF8}, modrm: -1, sib: -1, imm: []byte{immByte}})
|
||||
}
|
||||
return false, nil
|
||||
}
|
||||
|
||||
|
||||
+39
-13
@@ -182,13 +182,24 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
|
||||
|
||||
// MMX register moves: MOVQ M0, mem and MOVQ mem, M0 are the MMX
|
||||
// load/store pair 0F 6F/0F 7F (no prefix); a register pair takes the
|
||||
// load opcode. The XMM MOVQ forms follow below.
|
||||
// load opcode. The GPR crossings ride the MOVD opcodes with REX.W
|
||||
// (0F 6E into the bank, 0F 7E out), and an XMM source crosses into the
|
||||
// bank through the F2 0F D6 move. The XMM MOVQ forms follow below.
|
||||
if m, ok := src.(Reg); ok && m.mmx {
|
||||
switch d := dst.(type) {
|
||||
case Reg:
|
||||
if !d.mmx {
|
||||
if !d.mmx && (d.isVec() || d.fp) {
|
||||
return fmt.Errorf("MOV: MMX register moves stay inside the M bank")
|
||||
}
|
||||
if !d.mmx {
|
||||
// M → GPR: 0F 7E with REX.W, the bank in reg and the GPR in
|
||||
// r/m, the store layout the toolchain picks.
|
||||
i := &instr{opcode: []byte{0x0F, 0x7E}, modrm: -1, sib: -1, rexW: true}
|
||||
if err := setRM(i, m, d, 8); err != nil {
|
||||
return err
|
||||
}
|
||||
return e.emit(i)
|
||||
}
|
||||
i := &instr{opcode: []byte{0x0F, 0x6F}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, d, src, 8); err != nil {
|
||||
return err
|
||||
@@ -204,15 +215,30 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
|
||||
return fmt.Errorf("MOV: invalid MMX destination")
|
||||
}
|
||||
if m, ok := dst.(Reg); ok && m.mmx {
|
||||
srcM, ok := src.(Mem)
|
||||
if !ok {
|
||||
return fmt.Errorf("MOV: MMX load takes a memory source")
|
||||
switch src.(type) {
|
||||
case Mem, sbMem:
|
||||
i := &instr{opcode: []byte{0x0F, 0x6F}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, m, src, 8); err != nil {
|
||||
return err
|
||||
}
|
||||
return e.emit(i)
|
||||
case Reg:
|
||||
if g := src.(Reg); g.isVec() {
|
||||
// X → M: F2 0F D6, the bank in reg, the XMM source in r/m.
|
||||
i := &instr{prefix: 0xF2, opcode: []byte{0x0F, 0xD6}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, m, src, 8); err != nil {
|
||||
return err
|
||||
}
|
||||
return e.emit(i)
|
||||
}
|
||||
// GPR → M: 0F 6E with REX.W, the bank in reg, the GPR in r/m.
|
||||
i := &instr{opcode: []byte{0x0F, 0x6E}, modrm: -1, sib: -1, rexW: true}
|
||||
if err := setRM(i, m, src, 8); err != nil {
|
||||
return err
|
||||
}
|
||||
return e.emit(i)
|
||||
}
|
||||
i := &instr{opcode: []byte{0x0F, 0x6F}, modrm: -1, sib: -1}
|
||||
if err := setRM(i, m, srcM, 8); err != nil {
|
||||
return err
|
||||
}
|
||||
return e.emit(i)
|
||||
return fmt.Errorf("MOV: MMX load takes a register or memory source")
|
||||
}
|
||||
|
||||
if srcVec || dstVec {
|
||||
@@ -323,14 +349,14 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
|
||||
case Imm:
|
||||
if dstIsReg {
|
||||
v := int64(src)
|
||||
// The Go assembler compresses 64-bit moves whose immediate fits
|
||||
// a signed int32, choosing per sign:
|
||||
// The Go assembler compresses 64-bit moves whose immediate
|
||||
// fits the zero-extending 32-bit span, choosing per sign:
|
||||
// v >= 0: B8+rd imm32 without REX.W (zero-extended by the
|
||||
// hardware, REX.B still emitted for R8-R15);
|
||||
// v < 0: REX.W C7 /0 imm32 (sign-extended, the plain B8+rd
|
||||
// form would zero-extend and corrupt the value).
|
||||
// Out-of-range immediates keep the B8+rd imm64 form.
|
||||
if size == 8 && v >= 0 && v <= (1<<31)-1 {
|
||||
if size == 8 && v >= 0 && v <= (1<<32)-1 {
|
||||
i := newInstr(4, []byte{0xB8 + byte(dstReg.idx&7)})
|
||||
i.rexB = dstReg.idx >= 8
|
||||
i.imm = le32(v)
|
||||
|
||||
Reference in new issue
Block a user