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feat(arch): the SVE2 shift-by-vector family

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 20:35:41 +02:00
1 parent b93fccc075
commit bd80499c74
4 files changed
+135 -4
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arch/arm64_ext_test.go
+31
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@@ -1440,6 +1440,37 @@ func TestArm64ExtStage4Golden(t *testing.T) {
{"ZFMINQV Z25.S, P3, V5.S4", "ZFMINQV", ExtFormQuadReduce, ExtQualNone, ExtArrNone,
[]ExtOperand{ExtVector(25, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtVReg, Reg: 5, Arr: ExtArrS}},
0x6497af25},
// The shift-by-vector family.
{"ZASR Z15.B, Z0.B, P3.M, Z0.B", "ZASR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
0x04108de0},
{"ZASR Z2.D, Z10.D, P3.M, Z10.D", "ZASR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
[]ExtOperand{ExtVector(2, ExtArrD), ExtVector(10, ExtArrD), ExtPredicate(3, ExtQualMerging), ExtVector(10, ExtArrD)},
0x04d08c4a},
{"ZASR Z7.D, Z6.H, Z13.H", "ZASR", ExtFormShiftWide, ExtQualNone, ExtArrNone,
[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrH), ExtVector(13, ExtArrH)},
0x046780cd},
{"ZASRR Z15.B, Z0.B, P3.M, Z0.B", "ZASRR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
0x04148de0},
{"ZLSL Z2.D, Z10.D, P3.M, Z10.D", "ZLSL", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
[]ExtOperand{ExtVector(2, ExtArrD), ExtVector(10, ExtArrD), ExtPredicate(3, ExtQualMerging), ExtVector(10, ExtArrD)},
0x04d38c4a},
{"ZLSL Z7.D, Z6.H, Z13.H", "ZLSL", ExtFormShiftWide, ExtQualNone, ExtArrNone,
[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrH), ExtVector(13, ExtArrH)},
0x04678ccd},
{"ZLSLR Z15.B, Z0.B, P3.M, Z0.B", "ZLSLR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
0x04178de0},
{"ZLSR Z15.B, Z0.B, P3.M, Z0.B", "ZLSR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
0x04118de0},
{"ZLSR Z7.D, Z6.H, Z13.H", "ZLSR", ExtFormShiftWide, ExtQualNone, ExtArrNone,
[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrH), ExtVector(13, ExtArrH)},
0x046784cd},
{"ZLSRR Z15.B, Z0.B, P3.M, Z0.B", "ZLSRR", ExtFormZPredicatedSource, ExtQualMerging, ExtArrNone,
[]ExtOperand{ExtVector(15, ExtArrB), ExtVector(0, ExtArrB), ExtPredicate(3, ExtQualMerging), ExtVector(0, ExtArrB)},
0x04158de0},
} {
in := extInstructionMeta(t, tt.mnem, tt.form, tt.qual, tt.arr)
got, err := in.Encode(tt.ops)