feat(arch): the SVE2 shift-by-vector family

Assisted-by: GLM 5.3 Flash

asm/arm64_ext_asm_test.go

@@ -783,6 +783,17 @@ func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
 		{"ZFMAXQV Z25.S, P3, V5.S4", 0x6496af25},
 		{"ZFMINNMQV Z25.S, P3, V5.S4", 0x6495af25},
 		{"ZFMINQV Z25.S, P3, V5.S4", 0x6497af25},
+		// The shift-by-vector family.
+		{"ZASR Z15.B, Z0.B, P3.M, Z0.B", 0x04108de0},
+		{"ZASR Z2.D, Z10.D, P3.M, Z10.D", 0x04d08c4a},
+		{"ZASR Z7.D, Z6.H, Z13.H", 0x046780cd},
+		{"ZASRR Z15.B, Z0.B, P3.M, Z0.B", 0x04148de0},
+		{"ZLSL Z2.D, Z10.D, P3.M, Z10.D", 0x04d38c4a},
+		{"ZLSL Z7.D, Z6.H, Z13.H", 0x04678ccd},
+		{"ZLSLR Z15.B, Z0.B, P3.M, Z0.B", 0x04178de0},
+		{"ZLSR Z15.B, Z0.B, P3.M, Z0.B", 0x04118de0},
+		{"ZLSR Z7.D, Z6.H, Z13.H", 0x046784cd},
+		{"ZLSRR Z15.B, Z0.B, P3.M, Z0.B", 0x04158de0},
 	}
 	for _, tt := range tests {
 		words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")

asm/extension_test.go

@@ -298,6 +298,12 @@ func TestExtensionNamesARM64(t *testing.T) {
 		"ZSMINQV",
 		"ZUMAXQV",
 		"ZUMINQV",
+		"ZASR",
+		"ZASRR",
+		"ZLSL",
+		"ZLSLR",
+		"ZLSR",
+		"ZLSRR",
 		// The stage-three families: the SVE2 crypto group, the predicate
 		// counters and loop terminators with the 32-bit while compares, and
 		// the reductions into a SIMD register.
@@ -410,7 +416,7 @@ func TestExtensionNamesARM64(t *testing.T) {
 	if strings.Join(got, ",") != strings.Join(want, ",") {
 		t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
 	}
-	if n := len(arch.Extensions(arch.ARM64)); n != 405 {
-		t.Errorf("the family registers %d instructions, want 405", n)
+	if n := len(arch.Extensions(arch.ARM64)); n != 414 {
+		t.Errorf("the family registers %d instructions, want 414", n)
 	}
 }