feat(arch): the SVE2 shift-by-vector family

Assisted-by: GLM 5.3 Flash

asm/extension_test.go

@@ -298,6 +298,12 @@ func TestExtensionNamesARM64(t *testing.T) {
 		"ZSMINQV",
 		"ZUMAXQV",
 		"ZUMINQV",
+		"ZASR",
+		"ZASRR",
+		"ZLSL",
+		"ZLSLR",
+		"ZLSR",
+		"ZLSRR",
 		// The stage-three families: the SVE2 crypto group, the predicate
 		// counters and loop terminators with the 32-bit while compares, and
 		// the reductions into a SIMD register.
@@ -410,7 +416,7 @@ func TestExtensionNamesARM64(t *testing.T) {
 	if strings.Join(got, ",") != strings.Join(want, ",") {
 		t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
 	}
-	if n := len(arch.Extensions(arch.ARM64)); n != 405 {
-		t.Errorf("the family registers %d instructions, want 405", n)
+	if n := len(arch.Extensions(arch.ARM64)); n != 414 {
+		t.Errorf("the family registers %d instructions, want 414", n)
 	}
 }