test(disasm): pin decode parity with the toolchain and the round-trip invariant
Assisted-by: GLM 5.3 Flash
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package disasm
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import (
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"encoding/hex"
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"os"
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"strings"
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"testing"
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"sourcedock.dev/petrbalvin/gasm-sdk/arch"
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"sourcedock.dev/petrbalvin/gasm-sdk/asm"
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"sourcedock.dev/petrbalvin/gasm-sdk/ast"
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"sourcedock.dev/petrbalvin/gasm-sdk/parser"
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)
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// The parity fixtures carry a deterministic slice of the Go toolchain's own
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// view of the encoder corpus, one instruction per line as
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//
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// HEXBYTES\tTOOLCHAINTEXT
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//
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// where HEXBYTES are the instruction's bytes in storage order and
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// TOOLCHAINTEXT is what `go tool objdump` prints for them (its decoder is
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// the ground truth). The slices were sampled from GOROOT's assembler test
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// data with a fixed stride: amd64enc.s (the x87, SSE/MMX, VEX, XSAVE and
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// system families), amd64enc_extra.s, amd64.s, arm64enc.s, riscv64.s and
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// loong64enc1.s.
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var parityFixtures = []struct {
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arch arch.Arch
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file string
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}{
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{arch.AMD64, "testdata/parity_amd64.txt"},
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{arch.AMD64, "testdata/parity_amd64_extra.txt"},
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{arch.AMD64, "testdata/parity_amd64_sys.txt"},
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{arch.ARM64, "testdata/parity_arm64.txt"},
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{arch.RISCV, "testdata/parity_riscv64.txt"},
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{arch.LOONG64, "testdata/parity_loong64.txt"},
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}
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// TestOracleKnownBytes pins the oracle's own fidelity on a few encodings
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// whose bytes the sources name outright, before the bulk fixtures are
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// trusted: each row was cross-checked against `go tool objdump` over an
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// object the Go toolchain's own assembler produced.
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func TestOracleKnownBytes(t *testing.T) {
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for _, tt := range []struct {
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a arch.Arch
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code []byte
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text string
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}{
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// go tool asm: MOVQ AX, CX -> 4889c1.
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{arch.AMD64, []byte{0x48, 0x89, 0xc1}, "MOVQ AX, CX"},
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// arm64enc.s: "ADCW ZR, R8, R10 // 1a1f010a".
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{arch.ARM64, []byte{0x0a, 0x01, 0x1f, 0x1a}, "ADCW ZR, R8, R10"},
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// riscv64.s: "ADDI $2047, X5 // 9382f27f".
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{arch.RISCV, []byte{0x93, 0x82, 0xf2, 0x7f}, "ADDI $2047, X5, X5"},
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// The loong64 RET the runtime emits: 0x4c000020.
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{arch.LOONG64, []byte{0x20, 0x00, 0x00, 0x4c}, "RET"},
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} {
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ins, err := Decode(tt.a, tt.code, 0)
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if err != nil {
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t.Errorf("%s % x: %v", tt.a, tt.code, err)
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continue
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}
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if ins.Text != tt.text || ins.Len != len(tt.code) {
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t.Errorf("%s % x: %q (%d bytes), want %q (%d)",
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tt.a, tt.code, ins.Text, ins.Len, tt.text, len(tt.code))
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}
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}
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}
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// TestToolchainDecodeParity requires the decoder to reproduce the
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// toolchain's text for every fixture instruction, and to agree on the
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// instruction's length: both views of the same bytes.
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func TestToolchainDecodeParity(t *testing.T) {
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for _, fx := range parityFixtures {
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lines := readFixture(t, fx.file)
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for i, ln := range lines {
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// The amd64 branch rendering carries an absolute target, which
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// is a property of the decode base and not of the bytes; those
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// lines are pinned by TestBranchTargetConvention instead.
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if fx.arch == arch.AMD64 && relativeBranch(ln.text) {
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continue
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}
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ins, err := Decode(fx.arch, ln.code, 0)
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if err != nil {
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t.Errorf("%s line %d: %v", fx.file, i+1, err)
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continue
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}
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if ins.Len != len(ln.code) {
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t.Errorf("%s line %d: % x decoded to %d bytes, toolchain says %d",
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fx.file, i+1, ln.code, ins.Len, len(ln.code))
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continue
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}
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if ins.Text != ln.text {
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t.Errorf("%s line %d: % x decodes to %q, toolchain says %q",
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fx.file, i+1, ln.code, ins.Text, ln.text)
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}
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}
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}
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}
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// TestBranchTargetConvention pins the rendering convention for relative
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// branches: the target prints as an absolute address in the address space
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// of the addr argument, which is exactly what `go tool objdump` does. Both
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// views are faithful to the bytes; they must be decoded at the same base to
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// compare.
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func TestBranchTargetConvention(t *testing.T) {
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ins, err := Decode(arch.AMD64, []byte{0x72, 0x02}, 0x1ded)
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if err != nil {
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t.Fatal(err)
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}
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// The toolchain prints "JB 0x1df1" for these bytes at the same base.
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if ins.Text != "JB 0x1df1" {
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t.Errorf("JB at base 0x1ded: %q, want JB 0x1df1", ins.Text)
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}
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// The toolchain's listing documents relocations after the text
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// ("[3:7]R_PCREL:foo+4"); that is bookkeeping of the listing, not part
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// of the disassembler's text, and the fixtures carry it stripped.
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}
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// relativeBranch reports whether the rendered text carries a PC-relative
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// or position-dependent target. Such an operand is an address, not a
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// datum: it is faithful to the bytes only at the address the instruction
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// sits at, so re-assembling it inside a fresh wrapper cannot be expected
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// to reproduce them. The amd64 J- and LOOP/CALL families, plus the
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// arm64, riscv64 and loong64 "(PC)" forms, all fall here.
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func relativeBranch(text string) bool {
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if strings.Contains(text, "(PC)") || strings.Contains(text, "(RPC)") {
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return true
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}
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// Mnemonic is the first whitespace-free token.
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m := text
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if i := strings.IndexAny(text, " \t"); i >= 0 {
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m = text[:i]
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}
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switch {
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case strings.HasPrefix(m, "J"), // amd64 Jcc, JMP; arm64/riscv JMP
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m == "CALL", m == "XBEGIN",
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m == "LOOP", m == "LOOPE", m == "LOOPNE", m == "LOOPZ", m == "LOOPNZ",
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m == "CBNZ", m == "CBZ", m == "TBZ", m == "TBNZ", m == "BL":
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return true
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}
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return false
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}
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// toolchainRenderNames lists mnemonics the toolchain's own renderer prints
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// but the gasm encoder cannot assemble. Two kinds sit here: the spellings
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// golang.org/x/arch keeps in its non-Plan 9 form (MOVZX and MOVSX where
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// the assembler spells MOVBLZX and MOVBLSX, the CMOV* family, the packed
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// shuffles it names MOVDQA and MOVDQU, the CVT conversions), so the listing
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// text is not assembler input at all, and the handful of Plan 9 names the
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// encoder has no table entry for yet (CMPPD, STOSB, PUSHL). A parse
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// failure outside this set is a test failure, so the set shrinks as the
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// encoder's vocabulary grows.
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var toolchainRenderNames = map[string]bool{
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"MOVZX": true, "MOVSX": true, "MOVSXD": true,
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"SHLDL": true, "SHLDW": true, "SHLDQ": true,
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"SHRDL": true, "SHRDW": true, "SHRDQ": true,
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"MOVBE": true, "LSL": true, "LAR": true,
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"CMOVA": true, "CMOVAE": true, "CMOVB": true, "CMOVBE": true,
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"CMOVE": true, "CMOVG": true, "CMOVGE": true, "CMOVL": true,
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"CMOVNE": true, "CMOVNO": true, "CMOVNP": true, "CMOVNS": true,
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"CMOVO": true, "CMOVP": true, "CMOVS": true,
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"PUNPCKLWD": true, "PUNPCKLDQ": true, "PUNPCKHWD": true, "PUNPCKHDQ": true,
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"PSLLD": true, "PSRLD": true, "PSRAD": true,
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"PMULUDQ": true, "PMADDWD": true, "PACKSSDW": true,
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"MOVDQA": true, "MOVDQU": true, "MASKMOVDQU": true,
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"LSS": true, "LGS": true, "LFS": true,
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"WRGSBASE": true, "RDFSBASE": true, "STR": true, "SLDT": true,
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"RDRAND": true, "POPF": true, "LRET": true,
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"FDIV": true, "FADD": true, "FRINTS": true, "FRINTM": true,
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"CMPPD": true, "STOSB": true, "PUSHL": true,
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"MOVSD_XMM": true, "CMPSD_XMM": true,
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"CMPPS": true, "CMPSS": true, "CMPSB": true, "MOVSQ": true, "OUTSW": true,
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"SLLIUW": true, "SH1ADD": true, "SH2ADDUW": true,
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"BSETI": true, "BEXTI": true, "CLMULR": true,
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"CPOPW": true, "ORCB": true, "FABS": true, "FABSS": true, "FMUL": true,
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"MRS": true, "LU12IW": true,
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"CVTTSS2SIL": true, "CVTTSD2SIL": true,
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"CVTTPS2DQ": true, "CVTTPD2DQ": true,
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"CVTSS2SIL": true, "CVTSI2SSQ": true, "CVTSI2SSL": true,
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"CVTSI2SDQ": true, "CVTSI2SDL": true, "CVTSD2SIL": true,
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"CVTPS2DQ": true, "CVTPD2DQ": true, "CVTDQ2PS": true, "CVTDQ2PD": true,
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}
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// encoderDivergences lists fixture lines whose disassembler text re-encodes
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// to a DIFFERENT reading, so neither the byte-exact invariant nor the
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// fixed-point one can hold. Every entry is a finding for the asm package's
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// encoder, reported and not fixed here; the disassembler text itself is the
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// toolchain's. amd64: CMOVLE encodes the CMOVE condition code; MOVQ to a
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// memory operand drops the FS segment prefix; MOVQ2DQ takes the F2 prefix
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// and lands in MOVDQ2Q; CRC32 with a 16-bit register widens to 32 bits.
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// arm64: the CRC32 forms take the wrong Rm; the register-indexed load and
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// store forms lose the index operand; BFXIL encodes as BFI with shifted
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// immediates. loong64: the SC displacement encodes unscaled.
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// riscv64: FSGNJXS encodes as FMIN.S; FCLASSS and FCLASSD encode as MOVF;
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// the AUIPC immediate loses its high bits. Keyed by the fixture text.
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var encoderDivergences = map[string]bool{
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"CMOVLE 0(BX), DX": true,
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"MOVQ FS:0, DX": true,
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"MOVQ2DQ M2, X11": true,
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"CRC32 DL, R11": true,
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"XADDL DL, DL": true,
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"XCHGL DL, DL": true,
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"CMPL AL, $0x7": true,
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"CMPXCHGL DL, DL": true,
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"ANDL $0x7, AL": true,
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"SBBL $0x7, DL": true,
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"SBBL DL, R11": true,
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"SUBL $0x7, AL": true,
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"TESTL R11, DL": true,
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"BFXIL $26, R8, $16, R20": true,
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"CRC32B R17, R8, R16": true,
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"CRC32CB R19, R27, R22": true,
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"MOVBU (R27)(R23), R14": true,
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"MOVHU (R5)(R25.SXTW), R15": true,
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"MOVB (R5)(R15), R16": true,
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"MOVD R27, (R5)(R15.UXTW<<3)": true,
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"MOVH R11, (R27)(R14.SXTW<<1)": true,
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"SC R4, 1024(R5)": true,
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"FSGNJXS F1, F0, F2": true,
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"FCLASSS F0, X5": true,
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"FCLASSD F0, X5": true,
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"AUIPC $524287, X10": true,
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}
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// TestDisassemblyRoundTrip is the cheap invariant over the same slice:
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// dis(assemble(x)) must re-encode to x's bytes. The listing text goes back
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// through the parser and the encoder inside a fresh function, and the
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// result must match the fixture bytes exactly.
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//
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// Three documented kinds of line cannot carry the byte-exact invariant and
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// degrade to the weaker fixed-point check, decode(assemble(text)) == text:
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// position-dependent branches (relativeBranch), mnemonics the toolchain
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// renderer leaves outside Plan 9 vocabulary (toolchainRenderNames), and
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// the encoder divergences reported for asm (encoderDivergences) only for
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// the byte comparison. A line of none of these kinds must round-trip byte
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// for byte.
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func TestDisassemblyRoundTrip(t *testing.T) {
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for _, fx := range parityFixtures {
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lines := readFixture(t, fx.file)
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skipped := 0
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for i, ln := range lines {
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if relativeBranch(ln.text) {
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skipped++
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continue
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}
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m := mnemonic(ln.text)
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switch {
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case toolchainRenderNames[m]:
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// The toolchain renders a spelling the encoder cannot take.
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skipped++
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continue
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case fx.arch == arch.RISCV && strings.HasPrefix(m, "V"):
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// The RISC-V vector slice of the corpus is the open encoder
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// roadmap item; its mnemonics do not assemble yet. The
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// decode side is fully covered by the parity test, which
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// never parses.
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skipped++
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continue
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case m == "Unknown":
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// The x/arch loong64 renderer names opcodes it has no Go
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// spelling for "Unknown ..."; that text is the toolchain's
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// own and no assembler input.
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skipped++
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continue
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}
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src := "TEXT \u00b7k(SB), NOSPLIT, $0\n\t" + ln.text + "\n\tRET\n"
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f, errs := parser.Parse("k.s", src)
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if len(errs) > 0 {
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t.Errorf("%s line %d (%s): parse: %v", fx.file, i+1, ln.text, errs[0])
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continue
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}
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img, err := assembleFor(fx.arch, f)
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if err != nil {
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t.Errorf("%s line %d (%s): assemble: %v", fx.file, i+1, ln.text, err)
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continue
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}
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fn := img.Funcs[0]
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code := img.Code[fn.Offset : fn.Offset+fn.Size]
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if len(code) >= len(ln.code) && string(code[:len(ln.code)]) == string(ln.code) {
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continue
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}
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// Weaker invariant for the documented classes: the text must be
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// a fixed point of decode followed by encode, that is, the
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// re-encoded bytes must carry the same reading. Byte-equality
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// divergences outside the encoder set are real failures.
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back, err := Decode(fx.arch, code, 0)
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if err != nil || back.Text != ln.text {
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if encoderDivergences[ln.text] {
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continue
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}
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got := "undecodable"
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if err == nil {
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got = back.Text
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}
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t.Errorf("%s line %d (%s): round trip re-decodes as %q, bytes % x",
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fx.file, i+1, ln.text, got, code)
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}
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}
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if skipped > 0 {
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t.Logf("%s: %d of %d lines excluded (branches and toolchain-only spellings)", fx.file, skipped, len(lines))
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}
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}
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}
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// mnemonic returns the first whitespace-free token of the text.
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func mnemonic(text string) string {
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if i := strings.IndexAny(text, " \t"); i >= 0 {
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return text[:i]
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}
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return text
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}
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type fixtureLine struct {
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code []byte
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text string
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}
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func readFixture(t *testing.T, name string) []fixtureLine {
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t.Helper()
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data, err := os.ReadFile(name)
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if err != nil {
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t.Fatalf("%s: %v", name, err)
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}
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var out []fixtureLine
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for i, line := range strings.Split(strings.TrimSuffix(string(data), "\n"), "\n") {
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if line == "" {
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continue
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}
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tab := strings.IndexByte(line, '\t')
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if tab < 0 {
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t.Fatalf("%s line %d: no tab separator", name, i+1)
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}
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code, err := hex.DecodeString(line[:tab])
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if err != nil {
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t.Fatalf("%s line %d: bad hex: %v", name, i+1, err)
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}
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out = append(out, fixtureLine{code: code, text: line[tab+1:]})
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}
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return out
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}
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// assemble assembles the parsed file with the encoder for a.
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func assembleFor(a arch.Arch, f *ast.File) (*asm.Image, error) {
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switch a {
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case arch.ARM64:
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return asm.AssembleFileARM64(f)
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case arch.RISCV:
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return asm.AssembleFileRISCV(f)
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case arch.LOONG64:
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return asm.AssembleFileLOONG64(f)
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default:
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return asm.AssembleFile(f)
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}
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}
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Vendored
+1228
File diff suppressed because it is too large.
Load diff
+123
@@ -0,0 +1,123 @@
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c4e2fd9034e508000000 VPGATHERDQ Y0, 0x8(X4*8), Y6
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c4a2fd9034f508000000 VPGATHERDQ Y0, 0x8(X14*8), Y6
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c4e2fd90342508000000 VPGATHERDQ Y0, 0x8(X4*1), Y6
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c4a2fd90343508000000 VPGATHERDQ Y0, 0x8(X14*1), Y6
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c4e2e9914c7d00 VPGATHERQQ X2, 0(BP)(X7*2), X1
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c4e2e9924c7d00 VGATHERDPD X2, 0(BP)(X7*2), X1
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c4e2fd9234e508000000 VGATHERDPD Y0, 0x8(X4*8), Y6
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c4a2fd9234f508000000 VGATHERDPD Y0, 0x8(X14*8), Y6
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c4e2fd92342508000000 VGATHERDPD Y0, 0x8(X4*1), Y6
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c4a2fd92343508000000 VGATHERDPD Y0, 0x8(X14*1), Y6
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c4e2e9934c7d00 VGATHERQPD X2, 0(BP)(X7*2), X1
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c4e269924c7d00 VGATHERDPS X2, 0(BP)(X7*2), X1
|
||||
c4e2619234e508000000 VGATHERDPS X3, 0x8(X4*8), X6
|
||||
c4a2619234f508000000 VGATHERDPS X3, 0x8(X14*8), X6
|
||||
c4e25192342508000000 VGATHERDPS X5, 0x8(X4*1), X6
|
||||
c4a26192343508000000 VGATHERDPS X3, 0x8(X14*1), X6
|
||||
c4e269934c7d00 VGATHERQPS X2, 0(BP)(X7*2), X1
|
||||
c4e269904c7d00 VPGATHERDD X2, 0(BP)(X7*2), X1
|
||||
c4e2619034e508000000 VPGATHERDD X3, 0x8(X4*8), X6
|
||||
c4a2619034f508000000 VPGATHERDD X3, 0x8(X14*8), X6
|
||||
c4e26190342508000000 VPGATHERDD X3, 0x8(X4*1), X6
|
||||
c4a26190343508000000 VPGATHERDD X3, 0x8(X14*1), X6
|
||||
c4e269914c7d00 VPGATHERQD X2, 0(BP)(X7*2), X1
|
||||
c4e2f991140d00000000 VPGATHERQQ X0, 0(X1*1), X2
|
||||
c4e2f991140c VPGATHERQQ X0, 0(SP)(X1*1), X2
|
||||
c4e2f991940d00020000 VPGATHERQQ X0, 0x200(BP)(X1*1), X2
|
||||
c4c2fd91540c10 VPGATHERQQ Y0, 0x10(R12)(Y1*1), Y2
|
||||
c4e3714c1300 VPBLENDVB X0, 0(BX), X1, X2
|
||||
450f38cbdb SHA256RNDS2 X0, X11, X11
|
||||
450f38c9db SHA1MSG1 X11, X11
|
||||
450f38cadb SHA1MSG2 X11, X11
|
||||
450f38c8db SHA1NEXTE X11, X11
|
||||
450f3accdb03 SHA1RNDS4 $0x3, X11, X11
|
||||
450f38ccdb SHA256MSG1 X11, X11
|
||||
450f38cddb SHA256MSG2 X11, X11
|
||||
0f20c2 MOVL CR0, DX
|
||||
0fa8 PUSHL GS
|
||||
c5fe70d1ff VPSHUFHW $0xff, Y1, Y2
|
||||
c5ed73f9ff VPSLLDQ $0xff, Y1, Y2
|
||||
c5ed73d1ff VPSRLQ $0xff, Y1, Y2
|
||||
c4e37963d1ff VPCMPISTRI $0xff, X1, X2
|
||||
c4e37d1dcaff VCVTPS2PH $0xff, Y1, X2
|
||||
c5ed71d1ff VPSRLW $0xff, Y1, Y2
|
||||
6261f50858e2 VADDPD X2, X1, X28
|
||||
6201a50858e6 VADDPD X30, X11, X28
|
||||
62f19500580401 VADDPD 0(CX)(AX*1), X29, X0
|
||||
62719500581441 VADDPD 0(CX)(AX*2), X29, X10
|
||||
6261f50858a4010f000000 VADDPD 0xf(CX)(AX*1), X1, X28
|
||||
6261ad0858a4410f000000 VADDPD 0xf(CX)(AX*2), X10, X28
|
||||
62f19520584a7f VADDPD 0xfe0(DX), Y29, Y1
|
||||
62f19540584c427f VADDPD 0x1fc0(DX)(AX*2), Z29, Z1
|
||||
62f19520588a00100000 VADDPD 0x1000(DX), Y29, Y1
|
||||
62f19540588c4200200000 VADDPD 0x2000(DX)(AX*2), Z29, Z1
|
||||
6241a52858f2 VADDPD Y10, Y11, Y30
|
||||
6261f5285820 VADDPD 0(AX), Y1, Y28
|
||||
6261ad28582401 VADDPD 0(CX)(AX*1), Y10, Y28
|
||||
62619d2058a80f000000 VADDPD 0xf(AX), Y28, Y29
|
||||
6261fd2858ac410f000000 VADDPD 0xf(CX)(AX*2), Y0, Y29
|
||||
6261fd28586c4240 VADDPD 0x800(DX)(AX*2), Y0, Y29
|
||||
6201ed4858ec VADDPD Z28, Z2, Z29
|
||||
62018d4058ec VADDPD Z28, Z30, Z29
|
||||
62619d40582c01 VADDPD 0(CX)(AX*1), Z28, Z29
|
||||
62f1954058800f000000 VADDPD 0xf(AX), Z29, Z0
|
||||
627195405894010f000000 VADDPD 0xf(CX)(AX*1), Z29, Z10
|
||||
6261f548586a20 VADDPD 0x800(DX), Z1, Z29
|
||||
c5f990e9 KMOVB K1, K5
|
||||
c5f890c0 KMOVW K0, K0
|
||||
c57893d7 KMOVW K7, R10
|
||||
c5fb92e8 KMOVD AX, K5
|
||||
c4e1f890cd KMOVQ K5, K1
|
||||
c461fb93d7 KMOVQ K7, R10
|
||||
c4e1f844e9 KNOTQ K1, K5
|
||||
c4e1c445e8 KORQ K0, K7, K5
|
||||
c4e3f933e9c4 KSHIFTLQ $0xc4, K1, K5
|
||||
6251f52c58d4 VADDPD Y12, Y1, K4, Y10
|
||||
62f1f5495808 VADDPD 0(AX), Z1, K1, Z1
|
||||
62327d2b90b4fd80020000 VPGATHERDD 0x280(BP)(Y15*8), K3, Y14
|
||||
6232fd0b9074fd50 VPGATHERDQ 0x280(BP)(X15*8), K3, X14
|
||||
6232fd4b9074fd50 VPGATHERDQ 0x280(BP)(Y15*8), K3, Z14
|
||||
6252fd2692546750 VGATHERDPD 0x280(R15)(X20*2), K6, Y10
|
||||
62527d0692946780020000 VGATHERDPS 0x280(R15)(X20*2), K6, X10
|
||||
62527d4692946780020000 VGATHERDPS 0x280(R15)(Z20*2), K6, Z10
|
||||
62527d2693946780020000 VGATHERQPS 0x280(R15)(Y20*2), K6, X10
|
||||
62527d0691946780020000 VPGATHERQD 0x280(R15)(X20*2), K6, X10
|
||||
62527d4691946780020000 VPGATHERQD 0x280(R15)(Z20*2), K6, Y10
|
||||
6252fd2691546750 VPGATHERQQ 0x280(R15)(Y20*2), K6, Y10
|
||||
6252fd0693546750 VGATHERQPD 0x280(R15)(X20*2), K6, X10
|
||||
6252fd4693546750 VGATHERQPD 0x280(R15)(Z20*2), K6, Z10
|
||||
62a1854858c7 VADDPD Z23, Z15, Z16
|
||||
6272fd21933c3a VGATHERQPD 0(DX)(Y23*1), K1, Y15
|
||||
62e1fd086ee5 VMOVQ BP, X20
|
||||
62c1fd087ea40bf1ffffff VMOVQ X20, -0xf(R11)(CX*1)
|
||||
c4c139166c0bf1 VMOVHPD -0xf(R11)(CX*1), X8, X5
|
||||
c4415116440bf1 VMOVHPD -0xf(R11)(CX*1), X5, X8
|
||||
6251dd0016840bf1ffffff VMOVHPD -0xf(R11)(CX*1), X20, X8
|
||||
62c1bd0816a40bf1ffffff VMOVHPD -0xf(R11)(CX*1), X8, X20
|
||||
62e1fd081720 VMOVHPD X20, 0(AX)
|
||||
c579170444 VMOVHPD X8, 0(SP)(AX*2)
|
||||
c4c139126c0bf1 VMOVLPD -0xf(R11)(CX*1), X8, X5
|
||||
c4415112440bf1 VMOVLPD -0xf(R11)(CX*1), X5, X8
|
||||
6251dd0012840bf1ffffff VMOVLPD -0xf(R11)(CX*1), X20, X8
|
||||
62c1bd0812a40bf1ffffff VMOVLPD -0xf(R11)(CX*1), X8, X20
|
||||
62e1fd081320 VMOVLPD X20, 0(AX)
|
||||
c579130444 VMOVLPD X8, 0(SP)(AX*2)
|
||||
62c37d0815e611 VPEXTRW $0x11, X20, R14
|
||||
62e37d0815244411 VPEXTRW $0x11, X20, 0(SP)(AX*2)
|
||||
62f1edd958cb VADDPD.RU_SAE.Z Z3, Z2, K1, Z1
|
||||
62f1ed595808 VADDPD.BCST 0(AX), Z2, K1, Z1
|
||||
62f1ef19c2c000 VCMPSD.SAE $0x0, X0, X2, K1, K0
|
||||
62619d30586a7f VADDPD.BCST 0x3f8(DX), Y28, Y29
|
||||
62617c58586a7f VADDPS.BCST 0x1fc(DX), Z0, Z29
|
||||
6261fd1858ac42f0070000 VADDPD.BCST 0x7f0(DX)(AX*2), X0, X29
|
||||
62f19550588af0070000 VADDPD.BCST 0x7f0(DX), Z29, Z1
|
||||
6261745858ac42f0070000 VADDPS.BCST 0x7f0(DX)(AX*2), Z1, Z29
|
||||
62b3fd0c66cd02 VFPCLASSPDX $0x2, X21, K4, K1
|
||||
62b3fd0866cd02 VFPCLASSPDX $0x2, X21, K1
|
||||
62f35545031003 VALIGND $0x3, 0(AX), Z21, K5, Z2
|
||||
62b16d2872cd02 VPROLD $0x2, Y21, Y2
|
||||
62e27d0da02c50 VPSCATTERDD X21, K5, 0(AX)(X2*2)
|
||||
62b1b70811d5 VMOVSD X2, X9, X21
|
||||
62b1ff0d12d5 VMOVDDUP X21, K5, X2
|
||||
62b1ff4d12d5 VMOVDDUP Z21, K5, Z2
|
||||
62d1d54058d1 VADDPD Z9, Z21, Z2
|
||||
Vendored
+23
@@ -0,0 +1,23 @@
|
||||
cd04 INT $0x4
|
||||
4883ef04 SUBQ $0x4, DI
|
||||
49836c240804 SUBQ $0x4, 0x8(R12)
|
||||
72e9 JB 0x598
|
||||
7202 JB 0x5b9
|
||||
7205 JB 0x5c7
|
||||
7204 JB 0x5d4
|
||||
7202 JB 0x5de
|
||||
ff20 JMP 0(AX)
|
||||
7203 JB 0x5f2
|
||||
7204 JB 0x5fe
|
||||
43ff24ac JMP 0(R12)(R13*4)
|
||||
ff2424 JMP 0(SP)
|
||||
7203 JB 0x61b
|
||||
410fa5c3 SHLDL CL, AX, R11
|
||||
660fafda IMULW DX, BX
|
||||
660fc2150000000004 CMPPD $0x4, 0(IP), X2
|
||||
ca0400 LRET $0x4
|
||||
f20fd6c9 MOVDQ2Q X1, M1
|
||||
488b544c20 MOVQ 0x20(SP)(CX*2), DX
|
||||
468bac64437e0000 MOVL 0x7e43(SP)(R12*2), R13
|
||||
8a0444 MOVB 0(SP)(AX*2), AL
|
||||
64488b142500000000 MOVQ FS:0, DX
|
||||
Vendored
+144
@@ -0,0 +1,144 @@
|
||||
a602093a ADCSW R9, R21, R6
|
||||
23123011 ADDW $3076, R17, R3
|
||||
67158d0b ADDW R13->5, R11, R7
|
||||
6b147731 ADDSW $(3525<<12), R3, R11
|
||||
21004192 AND $-9223372036854775808, R1, R1
|
||||
7a1ec98a AND R9@>7, R19, R26
|
||||
1f0002ea TST R2, R0
|
||||
458051f2 ANDS $-140737488289793, R2, R5
|
||||
672bce9a ASR R14, R27, R7
|
||||
ffffff17 JMP -1(PC)
|
||||
14a55ab3 BFXIL $26, R8, $16, R20
|
||||
3730b3ea BICS R19->12, R1, R23
|
||||
e0013fd6 CALL (R15)
|
||||
e7ffffb5 CBNZ R7, -1(PC)
|
||||
4beb543a CCMNW AL, R26, $20, $11
|
||||
a76b4f7a CCMPW VS, R29, $15, $7
|
||||
e44341ba CCMN MI, ZR, R1, $4
|
||||
573093da CSINV LO, R2, R19, R23
|
||||
87718cda CINV VS, R12, R7
|
||||
e615c05a CLSW R15, R6
|
||||
ff11352b CMNW R21.UXTB<<4, R15
|
||||
bf084031 CMNW $(2<<12), R5
|
||||
bf001e2b CMNW R30, R5
|
||||
ff02266b CMPW R6.UXTB, R23
|
||||
2e45895a CNEGW PL, R9, R14
|
||||
1041d11a CRC32B R17, R8, R16
|
||||
7653d31a CRC32CB R19, R27, R22
|
||||
8c30941a CSELW LO, R4, R20, R12
|
||||
e5639f5a CSETMW VC, R5
|
||||
e5e2955a CSINVW AL, R23, R21, R5
|
||||
217608d5 DC IVAC, R1
|
||||
bf3103d5 DMB $1
|
||||
c974354a EONW R21<<29, R6, R9
|
||||
d1ef02ca EOR R2<<59, R30, R17
|
||||
bf2003d5 SEVL
|
||||
df3103d5 ISB $1
|
||||
f6ffdf88 LDARW (RSP), R22
|
||||
54c17f88 LDAXPW (R10), (R20, R16)
|
||||
70fe5f08 LDAXRB (R19), R16
|
||||
480540f8 MOVD.P (R10), R8
|
||||
498d5cf9 MOVD 14616(R10), R9
|
||||
4e5c5e38 MOVBU.W -27(R2), R14
|
||||
6e6b7738 MOVBU (R27)(R23), R14
|
||||
afc87978 MOVHU (R5)(R25.SXTW), R15
|
||||
b068af38 MOVB (R5)(R15), R16
|
||||
361f9c78 MOVH.W -63(R25), R22
|
||||
688e92b8 MOVW.W -216(R19), R8
|
||||
10347fc8 LDXP (R0), (R16, R13)
|
||||
9a7d5f48 LDXRH (R12), R26
|
||||
221a47d3 LSL $57, R17, R2
|
||||
34fc4cd3 LSR $12, R1, R20
|
||||
77ff0e9b MNEG R14, R27, R23
|
||||
d4adb252 MOVW $2507014144, R20
|
||||
e7031eaa MOVD R30, R7
|
||||
e5031faa MOVD ZR, R5
|
||||
284038d5 MRS $16897, R8
|
||||
42c3139b MSUB R19, R16, R26, R2
|
||||
e97f6daa MVN R13>>31, R9
|
||||
e70302da NGC R2, R7
|
||||
032ee42a ORNW R4@>11, R16, R3
|
||||
1a110d2a ORRW R13<<4, R8, R26
|
||||
3601c05a RBITW R9, R22
|
||||
220cc0da REV R1, R2
|
||||
336f8413 EXTRW $27, R4, R25, R19
|
||||
832dc31a RORW R3, R12, R3
|
||||
73021b7a SBCSW R27, R19, R19
|
||||
f4450813 SBFXW $8, R15, $10, R20
|
||||
9f2003d5 SEV
|
||||
6ffc3a9b SMNEGL R26, R3, R15
|
||||
03ff9fc8 STLR R3, (R24)
|
||||
edfd0e88 STLXRW R13, (R15), R14
|
||||
c6ae3588 STLXPW (R6, R11), (R22), R21
|
||||
112d86a9 STP.W (R17, R11), 96(R8)
|
||||
ae4d12f8 MOVD.W R14, -220(R13)
|
||||
bb0d1a38 MOVB.W R27, -96(R13)
|
||||
53cf1c79 MOVH R19, 3686(R26)
|
||||
bb582ff8 MOVD R27, (R5)(R15.UXTW<<3)
|
||||
6bdb2e78 MOVH R11, (R27)(R14.SXTW<<1)
|
||||
61082ac8 STXP (R1, R2), (R3), R10
|
||||
627e1488 STXRW R2, (R19), R20
|
||||
f34a344b SUBW R20.UXTW<<2, R23, R19
|
||||
e8740c4b SUBW R12<<29, R7, R8
|
||||
c9b04071 SUBSW $(44<<12), R6, R9
|
||||
d03c1aeb SUBS R26<<15, R6, R16
|
||||
a91d4093 SXTB R13, R9
|
||||
0c5b2cd5 SYSL $285440, R12
|
||||
5f54ca6a TSTW R10@>21, R2
|
||||
5f54ca6a TSTW R10@>21, R2
|
||||
ef580353 UBFXW $3, R7, $20, R15
|
||||
3152a09b UMADDL R0, R20, R17, R17
|
||||
d37eb39b UMULL R19, R22, R19
|
||||
0058204e VCNT V0.B16, V0.B16
|
||||
b8f8a04e FABS V5.S4, V24.S4
|
||||
4a282c1e FADDS F12, F2, F10
|
||||
ef856b1e FCCMPD HI, F11, F15, $15
|
||||
0821201e FCMPS $(0.0), F8
|
||||
b823201e FCMPES $(0.0), F29
|
||||
075d761e FCSELD PL, F8, F22, F7
|
||||
e700789e FCVTZSD F7, R7
|
||||
3603799e FCVTZUD F25, R22
|
||||
01090f1f FMADDS F15, F2, F8, F1
|
||||
ff4b6c1e FMAXD F12, F31, F31
|
||||
82c4392e VFMAXNMP V25.S2, V4.S2, V2.S2
|
||||
95587d1e FMIND F29, F4, F21
|
||||
3bc7aa6e VFMINNMP V10.S4, V25.S4, V27.S4
|
||||
4f00669e FMOVD F2, R15
|
||||
4940601e FMOVD F2, F9
|
||||
39de756e FMUL V21.D2, V17.D2, V25.D2
|
||||
0542211e FNEGS F16, F5
|
||||
6ec32e1f FNMSUBS F14, F16, F27, F14
|
||||
1540261e FRINTAS F0, F21
|
||||
3b99614e FRINTM V9.D2, V27.D2
|
||||
4e43241e FRINTNS F26, F14
|
||||
d6c0641e FRINTPD F6, F22
|
||||
7cc0251e FRINTZS F3, F28
|
||||
dbc1611e FSQRTD F14, F27
|
||||
8402621e SCVTFWD R20, F4
|
||||
5701631e UCVTFWD R10, F23
|
||||
4986654e VADD V5.H8, V18.H8, V9.H8
|
||||
fd4b284e AESE V31.B16, V29.B16
|
||||
ac8db86e VCMEQ V24.S4, V13.S4, V12.S4
|
||||
f4071b4e VDUP V31.B[13], V20.B16
|
||||
705d196e VMOV V11.B[11], V16.B[12]
|
||||
ae2f400c VLD1 (R29), [V14.D1, V15.D1, V16.D1, V17.D1]
|
||||
78a2c40c VLD1.P (R19)(R4), [V24.B8, V25.B8]
|
||||
a04b400d VLD1 (R29), V0.H[1]
|
||||
700cce4d VLD1.P (R3)(R14), V16.B[11]
|
||||
d181c24d VLD1.P (R14)(R2), V17.S[2]
|
||||
5b06155e VMOV V18.B[10], V27
|
||||
441ca24e VMOV V2.B16, V4.B16
|
||||
cf1eb94e VORR V25.B16, V22.B16, V15.B16
|
||||
24e0224e VPMULL2 V2.B16, V1.B16, V4.H8
|
||||
b018204e VREV16 V5.B16, V16.B16
|
||||
a901629e SCVTFD R13, F9
|
||||
9b12035e SHA1P V3.S4, V20, V27
|
||||
4b40045e SHA256H V4.S4, V2, V11
|
||||
6e67000c VST1 [V14.H4, V15.H4, V16.H4], (R27)
|
||||
eeac970c VST1.P [V14.D1, V15.D1], (R7)(R23)
|
||||
9324900c VST1.P [V19.H4, V20.H4, V21.H4, V22.H4], (R4)(R16)
|
||||
e987004d VST1 V9.D[1], (RSP)
|
||||
e15a8b4d VST1.P V1.H[7], (R23)(R11)
|
||||
b786904d VST1.P V23.D[1], (R21)(R16)
|
||||
4d03631e UCVTFWD R26, F13
|
||||
2c3c0e0e VMOV V1.H[3], R12
|
||||
Vendored
+73
@@ -0,0 +1,73 @@
|
||||
1ffcff4b BFPF -1(PC)
|
||||
04020014 LU12IW $16, R4
|
||||
85001700 MOVW R4, R5
|
||||
a6901100 SUBV R4, R5, R6
|
||||
a5101100 SUB R4, R5
|
||||
05101100 NEGW R4, R5
|
||||
a5101800 SRA R4, R5
|
||||
a5901b00 ROTRV R4, R5
|
||||
85200000 CLOV R4, R5
|
||||
85380000 REVB2W R4, R5
|
||||
854c0000 Unknown BITREV.8B R4, R5
|
||||
a6900001 ADDF F4, F5, F6
|
||||
64608029 MOVW R4, 24(R3)
|
||||
a404c029 MOVV R4, 1(R5)
|
||||
64400028 MOVB 16(R3), R4
|
||||
a404002a MOVBU 1(R5), R4
|
||||
04048003 MOVW $1, R4
|
||||
84fcff02 ADDV $-1, R4
|
||||
84904400 SRL $4, R4
|
||||
84104100 SLLV $4, R4
|
||||
80040040 BEQ R4, 1(PC)
|
||||
80040068 BLTU R4, 1(PC)
|
||||
6460c02b MOVD F4, 24(R3)
|
||||
85b81401 MOVV F4, R5
|
||||
a5101600 Unknown ORN R4, R5
|
||||
a6901d00 MULV R4, R5, R6
|
||||
a6901e00 MULHVU R4, R5, R6
|
||||
a6102200 DIVV R4, R5, R6
|
||||
a4044028 MOVH 1(R5), R4
|
||||
a5901c00 MULH R4, R5
|
||||
a5902000 REM R4, R5
|
||||
a5102000 DIV R4, R5
|
||||
a5102100 DIVU R4, R5
|
||||
85804500 SRLV $32, R4, R5
|
||||
a6101300 MASKEQZ R4, R5, R6
|
||||
a6102600 CRCCWBW R4, R5, R6
|
||||
85101d01 FFINTFW F4, F5
|
||||
85081401 ABSD F4, F5
|
||||
00004003 NOOP
|
||||
a510220c CMPEQD F4, F5, FCC5
|
||||
80d01401 MOVV F4, FCC0
|
||||
85040025 Unknown STPTR.W $4, R4, R5
|
||||
a4fc7f24 Unknown LDPTR.W $-4, R5, R4
|
||||
a4040026 Unknown LDPTR.D $4, R5, R4
|
||||
84400010 Unknown ADDU16I.D $16, R4
|
||||
acb95838 AMCASH R14, (R13), R12
|
||||
acb96238 AMANDV R14, (R13), R12
|
||||
acb96538 AMMAXV R14, (R13), R12
|
||||
acb96838 AMMINVU R14, (R13), R12
|
||||
acb95a38 AMCASDBH R14, (R13), R12
|
||||
acb96b38 AMANDDBV R14, (R13), R12
|
||||
acb96e38 AMMAXDBV R14, (R13), R12
|
||||
acb97138 AMMINDBVU R14, (R13), R12
|
||||
a4001021 SC R4, 1024(R5)
|
||||
30391108 FMADDF F2, F14, F9, F16
|
||||
88a1d808 FNMSUBF F17, F8, F12, F8
|
||||
a5ac9d08 FNMADDF F27, F11, F5, F5
|
||||
a6100b01 FMIND F4, F5, F6
|
||||
a6901201 FCOPYSGF F4, F5, F6
|
||||
01201d01 FFINTDW F0, F1
|
||||
01441e01 FRINTS F0, F1
|
||||
a6900e01 Unknown FMINA.S F4, F5, F6
|
||||
02241a01 FTINTRMVF F0, F2
|
||||
02841a01 FTINTRZWF F0, F2
|
||||
02e41a01 FTINTRNEVF F0, F2
|
||||
cc350438 MOVH (R14)(R13), R12
|
||||
cc351438 MOVH R12, (R14)(R13)
|
||||
c2353c38 MOVD F2, (R14)(R13)
|
||||
85188f00 BSTRINSV $15, R4, $6, R5
|
||||
8518cf00 BSTRPICKV $15, R4, $6, R5
|
||||
04a43a03 LU52ID $-343, R0, R4
|
||||
a484cc02 ADDV $801, R5, R4
|
||||
88fcff2a Unknown PRELD $-1, R4, $8
|
||||
Vendored
+290
@@ -0,0 +1,290 @@
|
||||
1383f27f ADDI $2047, X5, X6
|
||||
13e31200 ORI $1, X5, X6
|
||||
13d31200 SRLI $1, X5, X6
|
||||
1383f27f ADDI $2047, X5, X6
|
||||
b3b36200 SLTU X6, X5, X7
|
||||
b3e36200 OR X6, X5, X7
|
||||
13c31200 XORI $1, X5, X6
|
||||
17f5ff7f AUIPC $524287, X10
|
||||
33135300 SLL X5, X6, X6
|
||||
93d21200 SRLI $1, X5, X5
|
||||
93820280 ADDI $-2048, X5, X5
|
||||
67830200 JALR X6, (X5)
|
||||
63d46200 BGE X5, X6, 2(PC)
|
||||
03930200 MOVH (X5), X6
|
||||
03c30200 MOVBU (X5), X6
|
||||
23005300 MOVB X5, (X6)
|
||||
0f003083 FENCE.TSO
|
||||
bb135300 SLLW X5, X6, X7
|
||||
1b531300 SRLIW $1, X6, X6
|
||||
bbd35340 SRAW X5, X7, X7
|
||||
03b30200 MOV (X5), X6
|
||||
73708100 CSRRCI $2, VSTART, X0
|
||||
f3229000 CSRRS X0, VXSAT, X5
|
||||
f37211c0 CSRRCI $2, TIME, X5
|
||||
f36211c0 CSRRSI $2, TIME, X5
|
||||
73208500 CSRRS X10, VSTART, X0
|
||||
f32200c0 RDCYCLE X5
|
||||
b373530e CZERONEZ X5, X6, X7
|
||||
bb035302 MULW X5, X6, X7
|
||||
bb535302 DIVUW X5, X6, X7
|
||||
af33531a SCD X5, (X6), X7
|
||||
af335366 AMOANDD X5, (X6), X7
|
||||
af3353a6 AMOMAXD X5, (X6), X7
|
||||
af3353c6 AMOMINUD X5, (X6), X7
|
||||
53011008 FSUBS F1, F0, F2
|
||||
d31200c0 FCVTWS F0, X5
|
||||
d31220c0 FCVTLS F0, X5
|
||||
538002d0 FCVTSW X5, F0
|
||||
d33210c0 FCVTWUS F0, X5
|
||||
d33230c0 FCVTLUS F0, X5
|
||||
53211020 FSGNJXS F1, F0, F2
|
||||
47822018 FMSUBS F1, F2, F3, F4
|
||||
d31200e0 FCLASSS F0, X5
|
||||
5301100a FSUBD F1, F0, F2
|
||||
d31200c2 FCVTWD F0, X5
|
||||
d31220c2 FCVTLD F0, X5
|
||||
538002d2 FCVTDW X5, F0
|
||||
d33210c2 FCVTWUD F0, X5
|
||||
d33230c2 FCVTLUD F0, X5
|
||||
53011022 FSGNJD F1, F0, F2
|
||||
4782201a FMSUBD F1, F2, F3, F4
|
||||
d31200e2 FCLASSD F0, X5
|
||||
2ab0 MOVD F10, 32(X2)
|
||||
0cb1 MOVD F11, 32(X10)
|
||||
8152 ADDI $-32, X0, X5
|
||||
8112 ADDI $-32, X5, X5
|
||||
0171 ADDI $-512, X2, X2
|
||||
7d95 SRAI $63, X10, X10
|
||||
2694 ADD X9, X8, X8
|
||||
059c SUBW X9, X8, X8
|
||||
3326b620 SH1ADD X11, X12, X12
|
||||
bbc7e720 SH2ADDUW X14, X15, X15
|
||||
9b98f80b SLLIUW $63, X17, X17
|
||||
1b9c2b60 CPOPW X23, X24
|
||||
13d37228 ORCB X5, X6
|
||||
b323530a CLMULR X5, X6, X7
|
||||
135efe4b BEXTI $63, X28, X28
|
||||
9394f42b BSETI $63, X9, X9
|
||||
57760509 VSETVLI X10, E32, M1, TU, MA, X12
|
||||
5776650d VSETVLI X10, E32, MF4, TA, MA, X12
|
||||
57f60fcd VSETIVLI $31, E32, M1, TA, MA, X12
|
||||
87610502 VLE32V (X10), V3
|
||||
a7510502 VSE16V V3, (X10)
|
||||
8701b502 VLMV (X10), V3
|
||||
8761b50a VLSE32V (X10), X11, V3
|
||||
a751b50a VSSE16V V3, X11, (X10)
|
||||
87012506 VLUXEI8V (X10), V2, V3
|
||||
87712506 VLUXEI64V (X10), V2, V3
|
||||
8761250e VLOXEI32V (X10), V2, V3
|
||||
a7512506 VSUXEI16V V3, V2, (X10)
|
||||
a701250e VSOXEI8V V3, V2, (X10)
|
||||
a771250e VSOXEI64V V3, V2, (X10)
|
||||
07040501 VLE8FFV (X10), V0, V8
|
||||
07640522 VLSEG2E32V (X10), V8
|
||||
07040542 VLSEG3E8V (X10), V8
|
||||
07640540 VLSEG3E32V (X10), V0, V8
|
||||
07040560 VLSEG4E8V (X10), V0, V8
|
||||
07640582 VLSEG5E32V (X10), V8
|
||||
070405a2 VLSEG6E8V (X10), V8
|
||||
076405a0 VLSEG6E32V (X10), V0, V8
|
||||
070405c0 VLSEG7E8V (X10), V0, V8
|
||||
076405e2 VLSEG8E32V (X10), V8
|
||||
270c0522 VSSEG2E8V V24, (X10)
|
||||
276c0520 VSSEG2E32V V24, V0, (X10)
|
||||
270c0540 VSSEG3E8V V24, V0, (X10)
|
||||
276c0562 VSSEG4E32V V24, (X10)
|
||||
270c0582 VSSEG5E8V V24, (X10)
|
||||
276c0580 VSSEG5E32V V24, V0, (X10)
|
||||
270c05a0 VSSEG6E8V V24, V0, (X10)
|
||||
276c05c2 VSSEG7E32V V24, (X10)
|
||||
270c05e2 VSSEG8E8V V24, (X10)
|
||||
276c05e0 VSSEG8E32V V24, V0, (X10)
|
||||
07040521 VLSEG2E8FFV (X10), V0, V8
|
||||
07640543 VLSEG3E32FFV (X10), V8
|
||||
07040563 VLSEG4E8FFV (X10), V8
|
||||
07640561 VLSEG4E32FFV (X10), V0, V8
|
||||
07040581 VLSEG5E8FFV (X10), V0, V8
|
||||
076405a3 VLSEG6E32FFV (X10), V8
|
||||
070405c3 VLSEG7E8FFV (X10), V8
|
||||
076405c1 VLSEG7E32FFV (X10), V0, V8
|
||||
070405e1 VLSEG8E8FFV (X10), V0, V8
|
||||
0764b52a VLSSEG2E32V (X10), X11, V8
|
||||
0704b54a VLSSEG3E8V (X10), X11, V8
|
||||
0764b548 VLSSEG3E32V (X10), X11, V0, V8
|
||||
0704b568 VLSSEG4E8V (X10), X11, V0, V8
|
||||
0764b58a VLSSEG5E32V (X10), X11, V8
|
||||
0704b5aa VLSSEG6E8V (X10), X11, V8
|
||||
0764b5a8 VLSSEG6E32V (X10), X11, V0, V8
|
||||
0704b5c8 VLSSEG7E8V (X10), X11, V0, V8
|
||||
0764b5ea VLSSEG8E32V (X10), X11, V8
|
||||
270cb52a VSSSEG2E8V V24, X11, (X10)
|
||||
276cb528 VSSSEG2E32V V24, X11, V0, (X10)
|
||||
270cb548 VSSSEG3E8V V24, X11, V0, (X10)
|
||||
276cb56a VSSSEG4E32V V24, X11, (X10)
|
||||
270cb58a VSSSEG5E8V V24, X11, (X10)
|
||||
276cb588 VSSSEG5E32V V24, X11, V0, (X10)
|
||||
270cb5a8 VSSSEG6E8V V24, X11, V0, (X10)
|
||||
276cb5ca VSSSEG7E32V V24, X11, (X10)
|
||||
270cb5ea VSSSEG8E8V V24, X11, (X10)
|
||||
276cb5e8 VSSSEG8E32V V24, X11, V0, (X10)
|
||||
07044524 VLUXSEG2EI8V (X10), V4, V0, V8
|
||||
07644546 VLUXSEG3EI32V (X10), V4, V8
|
||||
07044566 VLUXSEG4EI8V (X10), V4, V8
|
||||
07644564 VLUXSEG4EI32V (X10), V4, V0, V8
|
||||
07044584 VLUXSEG5EI8V (X10), V4, V0, V8
|
||||
076445a6 VLUXSEG6EI32V (X10), V4, V8
|
||||
070445ae VLOXSEG6EI8V (X10), V4, V8
|
||||
076445ac VLOXSEG6EI32V (X10), V4, V0, V8
|
||||
070445c4 VLUXSEG7EI8V (X10), V4, V0, V8
|
||||
076445e6 VLUXSEG8EI32V (X10), V4, V8
|
||||
270c4526 VSUXSEG2EI8V V24, V4, (X10)
|
||||
276c4524 VSUXSEG2EI32V V24, V4, V0, (X10)
|
||||
270c4544 VSUXSEG3EI8V V24, V4, V0, (X10)
|
||||
276c4566 VSUXSEG4EI32V V24, V4, (X10)
|
||||
270c4586 VSUXSEG5EI8V V24, V4, (X10)
|
||||
276c4584 VSUXSEG5EI32V V24, V4, V0, (X10)
|
||||
270c45a4 VSUXSEG6EI8V V24, V4, V0, (X10)
|
||||
276c45c6 VSUXSEG7EI32V V24, V4, (X10)
|
||||
270c45e6 VSUXSEG8EI8V V24, V4, (X10)
|
||||
276c45e4 VSUXSEG8EI32V V24, V4, V0, (X10)
|
||||
0704452c VLOXSEG2EI8V (X10), V4, V0, V8
|
||||
0764454e VLOXSEG3EI32V (X10), V4, V8
|
||||
0704456e VLOXSEG4EI8V (X10), V4, V8
|
||||
0764456c VLOXSEG4EI32V (X10), V4, V0, V8
|
||||
0704458c VLOXSEG5EI8V (X10), V4, V0, V8
|
||||
076445ce VLOXSEG7EI32V (X10), V4, V8
|
||||
070445ee VLOXSEG8EI8V (X10), V4, V8
|
||||
076445ec VLOXSEG8EI32V (X10), V4, V0, V8
|
||||
270c452c VSOXSEG2EI8V V24, V4, V0, (X10)
|
||||
276c454e VSOXSEG3EI32V V24, V4, (X10)
|
||||
270c456e VSOXSEG4EI8V V24, V4, (X10)
|
||||
276c456c VSOXSEG4EI32V V24, V4, V0, (X10)
|
||||
270c458c VSOXSEG5EI8V V24, V4, V0, (X10)
|
||||
276c45ae VSOXSEG6EI32V V24, V4, (X10)
|
||||
270c45ce VSOXSEG7EI8V V24, V4, (X10)
|
||||
276c45cc VSOXSEG7EI32V V24, V4, V0, (X10)
|
||||
270c45ec VSOXSEG8EI8V V24, V4, V0, (X10)
|
||||
87518502 VL1RE16V (X10), V3
|
||||
07618522 VL2RE32V (X10), V2
|
||||
07728562 VL4RE64V (X10), V4
|
||||
a7818502 VS1RV V3, (X11)
|
||||
d7412502 VADDVX X10, V2, V3
|
||||
d781200a VSUBVV V1, V2, V3
|
||||
d7b1270c VRSUBVI $15, V2, V0, V3
|
||||
d76125c2 VWADDUVX X10, V2, V3
|
||||
d7a120c6 VWADDVV V1, V2, V3
|
||||
d76125ce VWSUBVX X10, V2, V3
|
||||
d7a120da VWSUBUWV V1, V2, V3
|
||||
d76125d6 VWADDWX X10, V2, V3
|
||||
d76120c6 VWCVTXXV V2, V3
|
||||
d7a1234a VSEXTVF2 V2, V3
|
||||
d721214a VZEXTVF8 V2, V3
|
||||
d7b12740 VADCVIM $15, V2, V0, V3
|
||||
57b02744 VMADCVIM $15, V2, V0, V0
|
||||
57b02746 VMADCVI $15, V2, V0
|
||||
57c0254c VMSBCVXM X11, V2, V0, V0
|
||||
d7812024 VANDVV V1, V2, V0, V3
|
||||
d7812028 VORVV V1, V2, V0, V3
|
||||
d781202c VXORVV V1, V2, V0, V3
|
||||
d7b12f2c VNOTV V2, V0, V3
|
||||
d7b12794 VSLLVI $15, V2, V0, V3
|
||||
d7b127a0 VSRLVI $15, V2, V0, V3
|
||||
d7b127a4 VSRAVI $15, V2, V0, V3
|
||||
d7b12fb0 VNSRLWI $31, V2, V0, V3
|
||||
d7b12fb4 VNSRAWI $31, V2, V0, V3
|
||||
d7412560 VMSEQVX X10, V2, V0, V3
|
||||
d7412564 VMSNEVX X10, V2, V0, V3
|
||||
d7412568 VMSLTUVX X10, V2, V0, V3
|
||||
d7812070 VMSLEUVV V1, V2, V0, V3
|
||||
d7812074 VMSLEVV V1, V2, V0, V3
|
||||
d7412578 VMSGTUVX X10, V2, V0, V3
|
||||
d7b1277c VMSGTVI $15, V2, V0, V3
|
||||
d7011174 VMSLEVV V2, V1, V0, V3
|
||||
d7312770 VMSLEUVI $14, V2, V0, V3
|
||||
d7812010 VMINUVV V1, V2, V0, V3
|
||||
d7412514 VMINVX X10, V2, V0, V3
|
||||
d781201c VMAXVV V1, V2, V0, V3
|
||||
d7612594 VMULVX X10, V2, V0, V3
|
||||
d7a12090 VMULHUVV V1, V2, V0, V3
|
||||
d7612598 VMULHSUVX X10, V2, V0, V3
|
||||
d7a12084 VDIVVV V1, V2, V0, V3
|
||||
d7612588 VREMUVX X10, V2, V0, V3
|
||||
d7a120ec VWMULVV V1, V2, V0, V3
|
||||
d76125e0 VWMULUVX X10, V2, V0, V3
|
||||
d7a120b4 VMACCVV V2, V1, V0, V3
|
||||
d76125bc VNMSACVX V2, X10, V0, V3
|
||||
d7a120ac VNMSUBVV V2, V1, V0, V3
|
||||
d76125f0 VWMACCUVX V2, X10, V0, V3
|
||||
d7a120fc VWMACCSUVV V2, V1, V0, V3
|
||||
d741255c VMERGEVXM X10, V2, V0, V3
|
||||
d7812080 VSADDUVV V1, V2, V0, V3
|
||||
d7812084 VSADDVV V1, V2, V0, V3
|
||||
d7812088 VSSUBUVV V1, V2, V0, V3
|
||||
d741258c VSSUBVX X10, V2, V0, V3
|
||||
d7a12024 VAADDVV V1, V2, V0, V3
|
||||
d7612528 VASUBUVX X10, V2, V0, V3
|
||||
d781209c VSMULVV V1, V2, V0, V3
|
||||
d74125a8 VSSRLVX X10, V2, V0, V3
|
||||
d74125ac VSSRAVX X10, V2, V0, V3
|
||||
d74125b8 VNCLIPUWX X10, V2, V0, V3
|
||||
d74125bc VNCLIPWX X10, V2, V0, V3
|
||||
d7512500 VFADDVF F10, V2, V0, V3
|
||||
d751259c VFRSUBVF F10, V2, V0, V3
|
||||
d79120c8 VFWSUBVV V1, V2, V0, V3
|
||||
d75125d0 VFWADDWF F10, V2, V0, V3
|
||||
d7912090 VFMULVV V1, V2, V0, V3
|
||||
d7512580 VFDIVVF F10, V2, V0, V3
|
||||
d75125e0 VFWMULVF F10, V2, V0, V3
|
||||
d79120b4 VFNMACCVV V2, V1, V0, V3
|
||||
d75125b8 VFMSACVF V2, F10, V0, V3
|
||||
d79120a0 VFMADDVV V2, V1, V0, V3
|
||||
d75125a4 VFNMADDVF V2, F10, V0, V3
|
||||
d79120ac VFNMSUBVV V2, V1, V0, V3
|
||||
d75125f0 VFWMACCVF V2, F10, V0, V3
|
||||
d79120f8 VFWMSACVV V2, V1, V0, V3
|
||||
d75125fc VFWNMSACVF V2, F10, V0, V3
|
||||
d791224c VFREC7V V2, V0, V3
|
||||
d7912018 VFMAXVV V1, V2, V0, V3
|
||||
d7512520 VFSGNJVF F10, V2, V0, V3
|
||||
d7912028 VFSGNJXVV V1, V2, V0, V3
|
||||
d7112128 VFABSV V2, V0, V3
|
||||
d7912070 VMFNEVV V1, V2, V0, V3
|
||||
d751256c VMFLTVF F10, V2, V0, V3
|
||||
d7512574 VMFGTVF F10, V2, V0, V3
|
||||
d7111164 VMFLEVV V2, V1, V0, V3
|
||||
d7112048 VFCVTXUFV V2, V0, V3
|
||||
d7912348 VFCVTRTZXFV V2, V0, V3
|
||||
d7112448 VFWCVTXUFV V2, V0, V3
|
||||
d7912748 VFWCVTRTZXFV V2, V0, V3
|
||||
d7112648 VFWCVTFFV V2, V0, V3
|
||||
d7112b48 VFNCVTRTZXUFW V2, V0, V3
|
||||
d7912948 VFNCVTFXW V2, V0, V3
|
||||
d7a12000 VREDSUMVS V1, V2, V0, V3
|
||||
d7a12010 VREDMINUVS V1, V2, V0, V3
|
||||
d7a12008 VREDORVS V1, V2, V0, V3
|
||||
d78120c4 VWREDSUMVS V1, V2, V0, V3
|
||||
d791201c VFREDMAXVS V1, V2, V0, V3
|
||||
d79120c4 VFWREDUSUMVS V1, V2, V0, V3
|
||||
d7a1207a VMNORMM V1, V2, V3
|
||||
d7212176 VMNOTM V2, V3
|
||||
d7a12050 VMSBFM V2, V0, V3
|
||||
d7212850 VIOTAM V2, V0, V3
|
||||
57510542 VFMVSF F10, V2
|
||||
d741253c VSLIDEDOWNVX X10, V2, V0, V3
|
||||
d7512538 VFSLIDE1UPVF F10, V2, V0, V3
|
||||
d7812030 VRGATHERVV V1, V2, V0, V3
|
||||
d7312830 VRGATHERVI $16, V2, V0, V3
|
||||
73000000 ECALL
|
||||
93020080 ADDI $-2048, X0, X5
|
||||
03830200 MOVB (X5), X6
|
||||
23305300 MOV X5, (X6)
|
||||
23205300 MOVW X5, (X6)
|
||||
d3000020 MOVF F0, F1
|
||||
27b20200 MOVD F0, 4(X5)
|
||||
93c2f2ff NOT X5, X5
|
||||
6fe06f9f JMP -1922(PC)
|
||||
63840200 BEQZ X5, 2(PC)
|
||||
63745300 BGEU X6, X5, 2(PC)
|
||||
d3200020 FABSS F0, F1
|
||||
d3a200a2 FEQD F0, F1, X5
|
||||
Reference in new issue
Block a user