 petrbalvin
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0760cc91af
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feat(arch): the SVE2 three-source and bitwise combine families
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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bd80499c74
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feat(arch): the SVE2 shift-by-vector family
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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b93fccc075
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feat(arch): the SVE2.1 pairwise and quadword-reduction families
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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31ab584eee
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feat(arch): the SVE2.1 narrowing two-to-one family
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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ee2c6d51b3
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fix(arch): keep Zdn out of the class bits of the predicated Z-alias source
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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104bea036b
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feat(asm): encode the arm64 SVE gather loads and scatter stores
Assisted-by: GLM 5.3
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2026-10-07 13:51:10 +02:00 |
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petrbalvin
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6faf850793
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feat(asm): encode the arm64 SVE2 crypto, counter and reduction families
Assisted-by: GLM 5.3
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2026-10-07 13:51:10 +02:00 |
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petrbalvin
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6c4932c4ec
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feat(arch): the SVE2.1 Z-alias permutations and copies
Assisted-by: GLM 5.3 Flash
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2026-10-07 02:27:35 +02:00 |
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petrbalvin
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8231302bca
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feat(arch): the SVE predicate family in the extended layer
Assisted-by: GLM 5.3 Flash
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2026-10-07 02:26:19 +02:00 |
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petrbalvin
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9c951c232e
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feat(asm): assemble the extended instruction layer on arm64
Assisted-by: GLM 5.3 Flash
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2026-10-07 02:23:37 +02:00 |
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