 petrbalvin
|
bd80499c74
|
feat(arch): the SVE2 shift-by-vector family
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
b93fccc075
|
feat(arch): the SVE2.1 pairwise and quadword-reduction families
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
31ab584eee
|
feat(arch): the SVE2.1 narrowing two-to-one family
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
ee2c6d51b3
|
fix(arch): keep Zdn out of the class bits of the predicated Z-alias source
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
104bea036b
|
feat(asm): encode the arm64 SVE gather loads and scatter stores
Assisted-by: GLM 5.3
|
2026-10-07 13:51:10 +02:00 |
|
|
petrbalvin
|
6faf850793
|
feat(asm): encode the arm64 SVE2 crypto, counter and reduction families
Assisted-by: GLM 5.3
|
2026-10-07 13:51:10 +02:00 |
|
|
petrbalvin
|
6c4932c4ec
|
feat(arch): the SVE2.1 Z-alias permutations and copies
Assisted-by: GLM 5.3 Flash
|
2026-10-07 02:27:35 +02:00 |
|
|
petrbalvin
|
8231302bca
|
feat(arch): the SVE predicate family in the extended layer
Assisted-by: GLM 5.3 Flash
|
2026-10-07 02:26:19 +02:00 |
|
|
petrbalvin
|
9c951c232e
|
feat(asm): assemble the extended instruction layer on arm64
Assisted-by: GLM 5.3 Flash
|
2026-10-07 02:23:37 +02:00 |
|