RISC-V 64: instruction inventory

Generated by gasm-sdk's _gen from the Go toolchain's instruction table (cmd/internal/obj/riscv/anames.go, go1.27.1); DO NOT EDIT. This page lists every mnemonic go tool asm accepts on this target, which is the upper bound of the language on it: a name absent here is not an instruction of the target, and a name present here may still be one gasm's encoder cannot emit yet.

The inventory carries no per-mnemonic encoder column: on this target encodability is decided per operand shape, and the live measured coverage is reported by gasm audit-instructions.

Mnemonic	Notes
`CALL`	Call subroutine
`DUFFCOPY`
`DUFFZERO`
`END`
`FUNCDATA`
`GETCALLERPC`
`JMP`	Unconditional jump
`NOP`
`PCALIGN`
`PCALIGNMAX`
`PCDATA`
`RET`	Return
`TEXT`
`UNDEF`
`ADD`	Integer add
`ADDI`	Add immediate
`ADDIW`	Add immediate (32-bit)
`ADDUW`
`ADDW`	Add (32-bit)
`AMOADDD`	Atomic add doubleword
`AMOADDW`	Atomic add word
`AMOANDD`
`AMOANDW`
`AMOMAXD`
`AMOMAXUD`
`AMOMAXUW`
`AMOMAXW`
`AMOMIND`
`AMOMINUD`
`AMOMINUW`
`AMOMINW`
`AMOORD`
`AMOORW`
`AMOSWAPD`	Atomic swap doubleword
`AMOSWAPW`	Atomic swap word
`AMOXORD`
`AMOXORW`
`AND`	Bitwise AND
`ANDI`	AND immediate
`ANDN`
`AUIPC`	Add upper immediate to PC
`BCLR`
`BCLRI`
`BEQ`	Branch if equal
`BEQZ`
`BEXT`
`BEXTI`
`BGE`	Branch if greater or equal
`BGEU`	Branch if greater or equal unsigned
`BGEZ`
`BGT`
`BGTU`
`BGTZ`
`BINV`
`BINVI`
`BLE`
`BLEU`
`BLEZ`
`BLT`	Branch if less than
`BLTU`	Branch if less than unsigned
`BLTZ`
`BNE`	Branch if not equal
`BNEZ`
`BSET`
`BSETI`
`CADD`
`CADDI`
`CADDI16SP`
`CADDI4SPN`
`CADDIW`
`CADDW`
`CAND`
`CANDI`
`CBEQZ`
`CBNEZ`
`CEBREAK`
`CFLD`
`CFLDSP`
`CFSD`
`CFSDSP`
`CJ`
`CJALR`
`CJR`
`CLD`
`CLDSP`
`CLI`
`CLUI`
`CLW`
`CLWSP`
`CLZ`
`CLZW`
`CMV`
`CNOP`
`COR`
`CPOP`
`CPOPW`
`CSD`
`CSDSP`
`CSLLI`
`CSRAI`
`CSRLI`
`CSRRC`
`CSRRCI`
`CSRRS`
`CSRRSI`
`CSRRW`
`CSRRWI`
`CSUB`
`CSUBW`
`CSW`
`CSWSP`
`CTZ`
`CTZW`
`CXOR`
`CZEROEQZ`
`CZERONEZ`
`DIV`	Divide
`DIVU`	Divide unsigned
`DIVUW`
`DIVW`	Divide (32-bit)
`DRET`
`EBREAK`	Breakpoint
`ECALL`	Environment call
`FABSD`
`FABSS`
`FADDD`	FP add (double)
`FADDQ`
`FADDS`	FP add (single)
`FCLASSD`
`FCLASSQ`
`FCLASSS`
`FCVTDL`
`FCVTDLU`
`FCVTDQ`
`FCVTDS`
`FCVTDW`
`FCVTDWU`
`FCVTLD`
`FCVTLQ`
`FCVTLS`
`FCVTLUD`
`FCVTLUQ`
`FCVTLUS`
`FCVTQD`
`FCVTQL`
`FCVTQLU`
`FCVTQS`
`FCVTQW`
`FCVTQWU`
`FCVTSD`
`FCVTSL`
`FCVTSLU`
`FCVTSQ`
`FCVTSW`
`FCVTSWU`
`FCVTWD`
`FCVTWQ`
`FCVTWS`
`FCVTWUD`
`FCVTWUQ`
`FCVTWUS`
`FDIVD`	FP divide (double)
`FDIVQ`
`FDIVS`	FP divide (single)
`FENCE`	Memory barrier
`FEQD`
`FEQQ`
`FEQS`
`FLD`	FP load doubleword
`FLED`
`FLEQ`
`FLES`
`FLQ`
`FLTD`
`FLTQ`
`FLTS`
`FLW`	FP load word
`FMADDD`
`FMADDQ`
`FMADDS`
`FMAXD`
`FMAXQ`
`FMAXS`
`FMIND`
`FMINQ`
`FMINS`
`FMSUBD`
`FMSUBQ`
`FMSUBS`
`FMULD`	FP multiply (double)
`FMULQ`
`FMULS`	FP multiply (single)
`FMVDX`
`FMVSX`
`FMVWX`
`FMVXD`
`FMVXS`
`FMVXW`
`FNED`
`FNEGD`
`FNEGS`
`FNES`
`FNMADDD`
`FNMADDQ`
`FNMADDS`
`FNMSUBD`
`FNMSUBQ`
`FNMSUBS`
`FSD`	FP store doubleword
`FSGNJD`
`FSGNJND`
`FSGNJNQ`
`FSGNJNS`
`FSGNJQ`
`FSGNJS`
`FSGNJXD`
`FSGNJXQ`
`FSGNJXS`
`FSQ`
`FSQRTD`
`FSQRTQ`
`FSQRTS`
`FSUBD`	FP subtract (double)
`FSUBQ`
`FSUBS`	FP subtract (single)
`FSW`	FP store word
`JAL`	Jump and link
`JALR`	Jump and link register
`LB`	Load byte
`LBU`	Load byte unsigned
`LD`	Load doubleword
`LH`	Load halfword
`LHU`	Load halfword unsigned
`LRD`	Load-reserved doubleword
`LRW`	Load-reserved word
`LUI`	Load upper immediate
`LW`	Load word
`LWU`	Load word unsigned
`MAX`
`MAXU`
`MIN`
`MINU`
`MOV`
`MOVB`
`MOVBU`
`MOVD`
`MOVF`
`MOVH`
`MOVHU`
`MOVW`
`MOVWU`
`MRET`
`MUL`	Multiply
`MULH`	Multiply high
`MULHSU`	Multiply high signed/unsigned
`MULHU`	Multiply high unsigned
`MULW`	Multiply (32-bit)
`NEG`
`NEGW`
`NOT`
`OR`	Bitwise OR
`ORCB`
`ORI`	OR immediate
`ORN`
`RDCYCLE`
`RDINSTRET`
`RDTIME`
`REM`	Remainder
`REMU`	Remainder unsigned
`REMUW`
`REMW`
`REV8`
`ROL`
`ROLW`
`ROR`
`RORI`
`RORIW`
`RORW`
`SB`	Store byte
`SBREAK`
`SCALL`
`SCD`	Store-conditional doubleword
`SCW`	Store-conditional word
`SD`	Store doubleword
`SEQZ`
`SEXTB`
`SEXTH`
`SFENCEVMA`
`SH`	Store halfword
`SH1ADD`
`SH1ADDUW`
`SH2ADD`
`SH2ADDUW`
`SH3ADD`
`SH3ADDUW`
`SLL`	Shift left logical
`SLLI`	Shift left logical immediate
`SLLIUW`
`SLLIW`
`SLLW`
`SLT`	Set if less than
`SLTI`	Set if less than immediate
`SLTIU`	Set if less than unsigned immediate
`SLTU`	Set if less than unsigned
`SNEZ`
`SRA`	Shift right arithmetic
`SRAI`	Shift right arithmetic immediate
`SRAIW`
`SRAW`
`SRET`
`SRL`	Shift right logical
`SRLI`	Shift right logical immediate
`SRLIW`
`SRLW`
`SUB`	Integer subtract
`SUBW`	Subtract (32-bit)
`SW`	Store word
`VAADDUVV`
`VAADDUVX`
`VAADDVV`
`VAADDVX`
`VADCVIM`
`VADCVVM`
`VADCVXM`
`VADDVI`
`VADDVV`
`VADDVX`
`VANDVI`
`VANDVV`
`VANDVX`
`VASUBUVV`
`VASUBUVX`
`VASUBVV`
`VASUBVX`
`VCOMPRESSVM`
`VCPOPM`
`VDIVUVV`
`VDIVUVX`
`VDIVVV`
`VDIVVX`
`VFABSV`
`VFADDVF`
`VFADDVV`
`VFCLASSV`
`VFCVTFXUV`
`VFCVTFXV`
`VFCVTRTZXFV`
`VFCVTRTZXUFV`
`VFCVTXFV`
`VFCVTXUFV`
`VFDIVVF`
`VFDIVVV`
`VFIRSTM`
`VFMACCVF`
`VFMACCVV`
`VFMADDVF`
`VFMADDVV`
`VFMAXVF`
`VFMAXVV`
`VFMERGEVFM`
`VFMINVF`
`VFMINVV`
`VFMSACVF`
`VFMSACVV`
`VFMSUBVF`
`VFMSUBVV`
`VFMULVF`
`VFMULVV`
`VFMVFS`
`VFMVSF`
`VFMVVF`
`VFNCVTFFW`
`VFNCVTFXUW`
`VFNCVTFXW`
`VFNCVTRODFFW`
`VFNCVTRTZXFW`
`VFNCVTRTZXUFW`
`VFNCVTXFW`
`VFNCVTXUFW`
`VFNEGV`
`VFNMACCVF`
`VFNMACCVV`
`VFNMADDVF`
`VFNMADDVV`
`VFNMSACVF`
`VFNMSACVV`
`VFNMSUBVF`
`VFNMSUBVV`
`VFRDIVVF`
`VFREC7V`
`VFREDMAXVS`
`VFREDMINVS`
`VFREDOSUMVS`
`VFREDUSUMVS`
`VFRSQRT7V`
`VFRSUBVF`
`VFSGNJNVF`
`VFSGNJNVV`
`VFSGNJVF`
`VFSGNJVV`
`VFSGNJXVF`
`VFSGNJXVV`
`VFSLIDE1DOWNVF`
`VFSLIDE1UPVF`
`VFSQRTV`
`VFSUBVF`
`VFSUBVV`
`VFWADDVF`
`VFWADDVV`
`VFWADDWF`
`VFWADDWV`
`VFWCVTFFV`
`VFWCVTFXUV`
`VFWCVTFXV`
`VFWCVTRTZXFV`
`VFWCVTRTZXUFV`
`VFWCVTXFV`
`VFWCVTXUFV`
`VFWMACCVF`
`VFWMACCVV`
`VFWMSACVF`
`VFWMSACVV`
`VFWMULVF`
`VFWMULVV`
`VFWNMACCVF`
`VFWNMACCVV`
`VFWNMSACVF`
`VFWNMSACVV`
`VFWREDOSUMVS`
`VFWREDUSUMVS`
`VFWSUBVF`
`VFWSUBVV`
`VFWSUBWF`
`VFWSUBWV`
`VIDV`
`VIOTAM`
`VL1RE16V`
`VL1RE32V`
`VL1RE64V`
`VL1RE8V`
`VL1RV`
`VL2RE16V`
`VL2RE32V`
`VL2RE64V`
`VL2RE8V`
`VL2RV`
`VL4RE16V`
`VL4RE32V`
`VL4RE64V`
`VL4RE8V`
`VL4RV`
`VL8RE16V`
`VL8RE32V`
`VL8RE64V`
`VL8RE8V`
`VL8RV`
`VLE16FFV`
`VLE16V`
`VLE32FFV`
`VLE32V`
`VLE64FFV`
`VLE64V`
`VLE8FFV`
`VLE8V`
`VLMV`
`VLOXEI16V`
`VLOXEI32V`
`VLOXEI64V`
`VLOXEI8V`
`VLOXSEG2EI16V`
`VLOXSEG2EI32V`
`VLOXSEG2EI64V`
`VLOXSEG2EI8V`
`VLOXSEG3EI16V`
`VLOXSEG3EI32V`
`VLOXSEG3EI64V`
`VLOXSEG3EI8V`
`VLOXSEG4EI16V`
`VLOXSEG4EI32V`
`VLOXSEG4EI64V`
`VLOXSEG4EI8V`
`VLOXSEG5EI16V`
`VLOXSEG5EI32V`
`VLOXSEG5EI64V`
`VLOXSEG5EI8V`
`VLOXSEG6EI16V`
`VLOXSEG6EI32V`
`VLOXSEG6EI64V`
`VLOXSEG6EI8V`
`VLOXSEG7EI16V`
`VLOXSEG7EI32V`
`VLOXSEG7EI64V`
`VLOXSEG7EI8V`
`VLOXSEG8EI16V`
`VLOXSEG8EI32V`
`VLOXSEG8EI64V`
`VLOXSEG8EI8V`
`VLSE16V`
`VLSE32V`
`VLSE64V`
`VLSE8V`
`VLSEG2E16FFV`
`VLSEG2E16V`
`VLSEG2E32FFV`
`VLSEG2E32V`
`VLSEG2E64FFV`
`VLSEG2E64V`
`VLSEG2E8FFV`
`VLSEG2E8V`
`VLSEG3E16FFV`
`VLSEG3E16V`
`VLSEG3E32FFV`
`VLSEG3E32V`
`VLSEG3E64FFV`
`VLSEG3E64V`
`VLSEG3E8FFV`
`VLSEG3E8V`
`VLSEG4E16FFV`
`VLSEG4E16V`
`VLSEG4E32FFV`
`VLSEG4E32V`
`VLSEG4E64FFV`
`VLSEG4E64V`
`VLSEG4E8FFV`
`VLSEG4E8V`
`VLSEG5E16FFV`
`VLSEG5E16V`
`VLSEG5E32FFV`
`VLSEG5E32V`
`VLSEG5E64FFV`
`VLSEG5E64V`
`VLSEG5E8FFV`
`VLSEG5E8V`
`VLSEG6E16FFV`
`VLSEG6E16V`
`VLSEG6E32FFV`
`VLSEG6E32V`
`VLSEG6E64FFV`
`VLSEG6E64V`
`VLSEG6E8FFV`
`VLSEG6E8V`
`VLSEG7E16FFV`
`VLSEG7E16V`
`VLSEG7E32FFV`
`VLSEG7E32V`
`VLSEG7E64FFV`
`VLSEG7E64V`
`VLSEG7E8FFV`
`VLSEG7E8V`
`VLSEG8E16FFV`
`VLSEG8E16V`
`VLSEG8E32FFV`
`VLSEG8E32V`
`VLSEG8E64FFV`
`VLSEG8E64V`
`VLSEG8E8FFV`
`VLSEG8E8V`
`VLSSEG2E16V`
`VLSSEG2E32V`
`VLSSEG2E64V`
`VLSSEG2E8V`
`VLSSEG3E16V`
`VLSSEG3E32V`
`VLSSEG3E64V`
`VLSSEG3E8V`
`VLSSEG4E16V`
`VLSSEG4E32V`
`VLSSEG4E64V`
`VLSSEG4E8V`
`VLSSEG5E16V`
`VLSSEG5E32V`
`VLSSEG5E64V`
`VLSSEG5E8V`
`VLSSEG6E16V`
`VLSSEG6E32V`
`VLSSEG6E64V`
`VLSSEG6E8V`
`VLSSEG7E16V`
`VLSSEG7E32V`
`VLSSEG7E64V`
`VLSSEG7E8V`
`VLSSEG8E16V`
`VLSSEG8E32V`
`VLSSEG8E64V`
`VLSSEG8E8V`
`VLUXEI16V`
`VLUXEI32V`
`VLUXEI64V`
`VLUXEI8V`
`VLUXSEG2EI16V`
`VLUXSEG2EI32V`
`VLUXSEG2EI64V`
`VLUXSEG2EI8V`
`VLUXSEG3EI16V`
`VLUXSEG3EI32V`
`VLUXSEG3EI64V`
`VLUXSEG3EI8V`
`VLUXSEG4EI16V`
`VLUXSEG4EI32V`
`VLUXSEG4EI64V`
`VLUXSEG4EI8V`
`VLUXSEG5EI16V`
`VLUXSEG5EI32V`
`VLUXSEG5EI64V`
`VLUXSEG5EI8V`
`VLUXSEG6EI16V`
`VLUXSEG6EI32V`
`VLUXSEG6EI64V`
`VLUXSEG6EI8V`
`VLUXSEG7EI16V`
`VLUXSEG7EI32V`
`VLUXSEG7EI64V`
`VLUXSEG7EI8V`
`VLUXSEG8EI16V`
`VLUXSEG8EI32V`
`VLUXSEG8EI64V`
`VLUXSEG8EI8V`
`VMACCVV`
`VMACCVX`
`VMADCVI`
`VMADCVIM`
`VMADCVV`
`VMADCVVM`
`VMADCVX`
`VMADCVXM`
`VMADDVV`
`VMADDVX`
`VMANDMM`
`VMANDNMM`
`VMAXUVV`
`VMAXUVX`
`VMAXVV`
`VMAXVX`
`VMCLRM`
`VMERGEVIM`
`VMERGEVVM`
`VMERGEVXM`
`VMFEQVF`
`VMFEQVV`
`VMFGEVF`
`VMFGEVV`
`VMFGTVF`
`VMFGTVV`
`VMFLEVF`
`VMFLEVV`
`VMFLTVF`
`VMFLTVV`
`VMFNEVF`
`VMFNEVV`
`VMINUVV`
`VMINUVX`
`VMINVV`
`VMINVX`
`VMMVM`
`VMNANDMM`
`VMNORMM`
`VMNOTM`
`VMORMM`
`VMORNMM`
`VMSBCVV`
`VMSBCVVM`
`VMSBCVX`
`VMSBCVXM`
`VMSBFM`
`VMSEQVI`
`VMSEQVV`
`VMSEQVX`
`VMSETM`
`VMSGEUVI`
`VMSGEUVV`
`VMSGEVI`
`VMSGEVV`
`VMSGTUVI`
`VMSGTUVV`
`VMSGTUVX`
`VMSGTVI`
`VMSGTVV`
`VMSGTVX`
`VMSIFM`
`VMSLEUVI`
`VMSLEUVV`
`VMSLEUVX`
`VMSLEVI`
`VMSLEVV`
`VMSLEVX`
`VMSLTUVI`
`VMSLTUVV`
`VMSLTUVX`
`VMSLTVI`
`VMSLTVV`
`VMSLTVX`
`VMSNEVI`
`VMSNEVV`
`VMSNEVX`
`VMSOFM`
`VMULHSUVV`
`VMULHSUVX`
`VMULHUVV`
`VMULHUVX`
`VMULHVV`
`VMULHVX`
`VMULVV`
`VMULVX`
`VMV1RV`
`VMV2RV`
`VMV4RV`
`VMV8RV`
`VMVSX`
`VMVVI`
`VMVVV`
`VMVVX`
`VMVXS`
`VMXNORMM`
`VMXORMM`
`VNCLIPUWI`
`VNCLIPUWV`
`VNCLIPUWX`
`VNCLIPWI`
`VNCLIPWV`
`VNCLIPWX`
`VNCVTXXW`
`VNEGV`
`VNMSACVV`
`VNMSACVX`
`VNMSUBVV`
`VNMSUBVX`
`VNOTV`
`VNSRAWI`
`VNSRAWV`
`VNSRAWX`
`VNSRLWI`
`VNSRLWV`
`VNSRLWX`
`VORVI`
`VORVV`
`VORVX`
`VREDANDVS`
`VREDMAXUVS`
`VREDMAXVS`
`VREDMINUVS`
`VREDMINVS`
`VREDORVS`
`VREDSUMVS`
`VREDXORVS`
`VREMUVV`
`VREMUVX`
`VREMVV`
`VREMVX`
`VRGATHEREI16VV`
`VRGATHERVI`
`VRGATHERVV`
`VRGATHERVX`
`VRSUBVI`
`VRSUBVX`
`VS1RV`
`VS2RV`
`VS4RV`
`VS8RV`
`VSADDUVI`
`VSADDUVV`
`VSADDUVX`
`VSADDVI`
`VSADDVV`
`VSADDVX`
`VSBCVVM`
`VSBCVXM`
`VSE16V`
`VSE32V`
`VSE64V`
`VSE8V`
`VSETIVLI`
`VSETVL`
`VSETVLI`
`VSEXTVF2`
`VSEXTVF4`
`VSEXTVF8`
`VSLIDE1DOWNVX`
`VSLIDE1UPVX`
`VSLIDEDOWNVI`
`VSLIDEDOWNVX`
`VSLIDEUPVI`
`VSLIDEUPVX`
`VSLLVI`
`VSLLVV`
`VSLLVX`
`VSMULVV`
`VSMULVX`
`VSMV`
`VSOXEI16V`
`VSOXEI32V`
`VSOXEI64V`
`VSOXEI8V`
`VSOXSEG2EI16V`
`VSOXSEG2EI32V`
`VSOXSEG2EI64V`
`VSOXSEG2EI8V`
`VSOXSEG3EI16V`
`VSOXSEG3EI32V`
`VSOXSEG3EI64V`
`VSOXSEG3EI8V`
`VSOXSEG4EI16V`
`VSOXSEG4EI32V`
`VSOXSEG4EI64V`
`VSOXSEG4EI8V`
`VSOXSEG5EI16V`
`VSOXSEG5EI32V`
`VSOXSEG5EI64V`
`VSOXSEG5EI8V`
`VSOXSEG6EI16V`
`VSOXSEG6EI32V`
`VSOXSEG6EI64V`
`VSOXSEG6EI8V`
`VSOXSEG7EI16V`
`VSOXSEG7EI32V`
`VSOXSEG7EI64V`
`VSOXSEG7EI8V`
`VSOXSEG8EI16V`
`VSOXSEG8EI32V`
`VSOXSEG8EI64V`
`VSOXSEG8EI8V`
`VSRAVI`
`VSRAVV`
`VSRAVX`
`VSRLVI`
`VSRLVV`
`VSRLVX`
`VSSE16V`
`VSSE32V`
`VSSE64V`
`VSSE8V`
`VSSEG2E16V`
`VSSEG2E32V`
`VSSEG2E64V`
`VSSEG2E8V`
`VSSEG3E16V`
`VSSEG3E32V`
`VSSEG3E64V`
`VSSEG3E8V`
`VSSEG4E16V`
`VSSEG4E32V`
`VSSEG4E64V`
`VSSEG4E8V`
`VSSEG5E16V`
`VSSEG5E32V`
`VSSEG5E64V`
`VSSEG5E8V`
`VSSEG6E16V`
`VSSEG6E32V`
`VSSEG6E64V`
`VSSEG6E8V`
`VSSEG7E16V`
`VSSEG7E32V`
`VSSEG7E64V`
`VSSEG7E8V`
`VSSEG8E16V`
`VSSEG8E32V`
`VSSEG8E64V`
`VSSEG8E8V`
`VSSRAVI`
`VSSRAVV`
`VSSRAVX`
`VSSRLVI`
`VSSRLVV`
`VSSRLVX`
`VSSSEG2E16V`
`VSSSEG2E32V`
`VSSSEG2E64V`
`VSSSEG2E8V`
`VSSSEG3E16V`
`VSSSEG3E32V`
`VSSSEG3E64V`
`VSSSEG3E8V`
`VSSSEG4E16V`
`VSSSEG4E32V`
`VSSSEG4E64V`
`VSSSEG4E8V`
`VSSSEG5E16V`
`VSSSEG5E32V`
`VSSSEG5E64V`
`VSSSEG5E8V`
`VSSSEG6E16V`
`VSSSEG6E32V`
`VSSSEG6E64V`
`VSSSEG6E8V`
`VSSSEG7E16V`
`VSSSEG7E32V`
`VSSSEG7E64V`
`VSSSEG7E8V`
`VSSSEG8E16V`
`VSSSEG8E32V`
`VSSSEG8E64V`
`VSSSEG8E8V`
`VSSUBUVV`
`VSSUBUVX`
`VSSUBVV`
`VSSUBVX`
`VSUBVV`
`VSUBVX`
`VSUXEI16V`
`VSUXEI32V`
`VSUXEI64V`
`VSUXEI8V`
`VSUXSEG2EI16V`
`VSUXSEG2EI32V`
`VSUXSEG2EI64V`
`VSUXSEG2EI8V`
`VSUXSEG3EI16V`
`VSUXSEG3EI32V`
`VSUXSEG3EI64V`
`VSUXSEG3EI8V`
`VSUXSEG4EI16V`
`VSUXSEG4EI32V`
`VSUXSEG4EI64V`
`VSUXSEG4EI8V`
`VSUXSEG5EI16V`
`VSUXSEG5EI32V`
`VSUXSEG5EI64V`
`VSUXSEG5EI8V`
`VSUXSEG6EI16V`
`VSUXSEG6EI32V`
`VSUXSEG6EI64V`
`VSUXSEG6EI8V`
`VSUXSEG7EI16V`
`VSUXSEG7EI32V`
`VSUXSEG7EI64V`
`VSUXSEG7EI8V`
`VSUXSEG8EI16V`
`VSUXSEG8EI32V`
`VSUXSEG8EI64V`
`VSUXSEG8EI8V`
`VWADDUVV`
`VWADDUVX`
`VWADDUWV`
`VWADDUWX`
`VWADDVV`
`VWADDVX`
`VWADDWV`
`VWADDWX`
`VWCVTUXXV`
`VWCVTXXV`
`VWMACCSUVV`
`VWMACCSUVX`
`VWMACCUSVX`
`VWMACCUVV`
`VWMACCUVX`
`VWMACCVV`
`VWMACCVX`
`VWMULSUVV`
`VWMULSUVX`
`VWMULUVV`
`VWMULUVX`
`VWMULVV`
`VWMULVX`
`VWREDSUMUVS`
`VWREDSUMVS`
`VWSUBUVV`
`VWSUBUVX`
`VWSUBUWV`
`VWSUBUWX`
`VWSUBVV`
`VWSUBVX`
`VWSUBWV`
`VWSUBWX`
`VXORVI`
`VXORVV`
`VXORVX`
`VZEXTVF2`
`VZEXTVF4`
`VZEXTVF8`
`WFI`
`WORD`
`XNOR`
`XOR`	Bitwise XOR
`XORI`	XOR immediate
`ZEXTH`

Recognised: 975 mnemonics.

19 KiB Raw Permalink Blame History

RISC-V 64: instruction inventory

19 KiB

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