 petrbalvin
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a9ee2bc702
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test(parser): pin the trailing comment of a TEXT and GLOBL header
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:50:20 +02:00 |
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petrbalvin
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6f3e054bab
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test(asm): pin the flag-list TEXT shapes against the toolchain
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:50:20 +02:00 |
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petrbalvin
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9179d5cc7a
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test(format): pin the canonical rendering of the flags operand
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:50:20 +02:00 |
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petrbalvin
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431d0d9b0b
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feat(parser): read the TEXT and GLOBL operands the toolchain counts them
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:50:20 +02:00 |
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petrbalvin
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cea5db6964
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feat(parser): evaluate the TEXT and GLOBL flags operand as one expression
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:50:20 +02:00 |
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petrbalvin
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4eb9100def
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test(asm): walk the loong64 audit backlog under every operand shape
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:42:14 +02:00 |
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petrbalvin
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43494a30f0
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test(disasm): pin the toolchain's own ADDU16I.D rendering
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:42:14 +02:00 |
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petrbalvin
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f661c2fc78
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test(asm): pin the ADDV16 immediate family the toolchain assembles
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:42:14 +02:00 |
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petrbalvin
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a3eaa82f87
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feat(asm): take the loong64 register-pair spellings the toolchain parses
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:42:14 +02:00 |
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petrbalvin
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1031cd9ae7
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feat(arch): the same-size shift-immediate family
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:39:45 +02:00 |
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petrbalvin
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eda8b16c5f
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feat(arch): the shift-immediate tsz:imm3 scheme
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:39:45 +02:00 |
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petrbalvin
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718181e7a7
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feat(arch): the FP8-to-halfword conversion pairs
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:39:45 +02:00 |
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petrbalvin
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107ca512b2
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feat(arch): the ZCNOT unary pair and the vector counter step
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:39:45 +02:00 |
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petrbalvin
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4066396226
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feat(asm): encode the GETCALLERPC, REM, DWORD and half-FCVT shapes
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:34:30 +02:00 |
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petrbalvin
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df7a5091e0
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test(asm): pair the same-named GOROOT functions in definition order
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:34:30 +02:00 |
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petrbalvin
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c27ba30862
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feat(asm): encode the arm64 local-exec TLS load
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:34:30 +02:00 |
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petrbalvin
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5f6be4584d
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fix(asm): encode the flag-setting logicals to ZR and fold immediate expressions
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:34:30 +02:00 |
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petrbalvin
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c1cef7b6e8
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feat(asm): materialise frame-relative addresses the way the toolchain does
Assisted-by: GLM 5.3 Flash
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2026-10-07 21:34:30 +02:00 |
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petrbalvin
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1120a52a54
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test(asm): sweep every registered amd64 extension mnemonic from .s text
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:56:25 +02:00 |
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petrbalvin
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fa50521619
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feat(lint): surface the amd64 extension layer's refusals
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:56:25 +02:00 |
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petrbalvin
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5ee60c860b
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fix(cmd/gasm): probe the arm64 operand shapes the encoder accepts
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:39:44 +02:00 |
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petrbalvin
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76f8ba6403
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feat(asm): give riscv64 the END and GETCALLERPC the toolchain accepts
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:39:44 +02:00 |
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petrbalvin
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0211d6672d
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feat(asm): expand riscv64 memory offsets beyond the 12-bit immediate
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:39:44 +02:00 |
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petrbalvin
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7aba29ac67
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test(arch): pin the golden vectors of the last four families
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:42 +02:00 |
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petrbalvin
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aeb109a64c
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feat(arch): the vector-length arithmetic pseudo group
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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bd85f8838d
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feat(arch): the SVE2.1 last-active vector and compare families
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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12a5cfff52
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feat(arch): the rest of the SVE2 BFloat16 wall
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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cdc3a75c88
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feat(arch): the SVE multiple-structure loads and stores
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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82dbf087a8
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feat(arch): the SVE2 BFloat16 arithmetic core
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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0760cc91af
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feat(arch): the SVE2 three-source and bitwise combine families
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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bd80499c74
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feat(arch): the SVE2 shift-by-vector family
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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b93fccc075
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feat(arch): the SVE2.1 pairwise and quadword-reduction families
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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31ab584eee
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feat(arch): the SVE2.1 narrowing two-to-one family
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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ee2c6d51b3
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fix(arch): keep Zdn out of the class bits of the predicated Z-alias source
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:35:41 +02:00 |
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petrbalvin
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6e49cbd099
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feat(asm): assemble the extended instruction layer on amd64
Assisted-by: GLM 5.3 Flash
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2026-10-07 20:24:51 +02:00 |
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petrbalvin
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d4878524e8
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test(asm): pin the clean GOROOT arm64 set against the toolchain
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:54:22 +02:00 |
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petrbalvin
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07f4622ffe
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style(asm): range over the kernel generator's statement count
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:54:22 +02:00 |
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petrbalvin
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b3ede5f952
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test(asm): pin the mid-function pool flush against the toolchain
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:54:22 +02:00 |
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petrbalvin
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5a5936d222
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feat(asm): drain the arm64 literal pool mid-function at the distance bound
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:54:22 +02:00 |
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petrbalvin
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4632ac1bb9
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feat(arch): add the AVX-VNNI-INT16 dot products to the extension layer
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:49:15 +02:00 |
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petrbalvin
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96000dd64d
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feat(arch): add the VEX encoder to the extension layer
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:49:15 +02:00 |
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petrbalvin
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47d561b229
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refactor(arch): extract the displacement tail and SIB builders
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:49:15 +02:00 |
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petrbalvin
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27ef71859b
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feat(arch): add VMINMAXSH to the extension layer
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:49:15 +02:00 |
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petrbalvin
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03f9ef0ac6
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feat(arch): add the FP16 complex fused multiply-add to the extension layer
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:49:15 +02:00 |
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petrbalvin
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86cb785e58
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fix(asm): read the MOV family registers against their banks
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:40:32 +02:00 |
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petrbalvin
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4ff47fe17a
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fix(cmd/gasm): probe the riscv64 operand shapes the encoder accepts
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:40:32 +02:00 |
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petrbalvin
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d18195f581
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test(asm): pin the riscv64 error parity against the toolchain catalogues
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:40:32 +02:00 |
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petrbalvin
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f0942ff7f3
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fix(asm): reject the operand shapes the toolchain rejects on riscv64
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:40:32 +02:00 |
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petrbalvin
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6c66f5bbd9
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test(asm): encode the new FP16 families through the registry
Assisted-by: GLM 5.3 Flash
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2026-10-07 19:00:44 +02:00 |
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petrbalvin
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509afbb6c9
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feat(arch): add the FP16 complex multiply and minimum-maximum to the extension layer
Assisted-by: GLM 5.3 Flash
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2026-10-07 18:59:09 +02:00 |
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