petrbalvin
b3ede5f952
test(asm): pin the mid-function pool flush against the toolchain
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:54:22 +02:00
petrbalvin
5a5936d222
feat(asm): drain the arm64 literal pool mid-function at the distance bound
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:54:22 +02:00
petrbalvin
4632ac1bb9
feat(arch): add the AVX-VNNI-INT16 dot products to the extension layer
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
27ef71859b
feat(arch): add VMINMAXSH to the extension layer
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
03f9ef0ac6
feat(arch): add the FP16 complex fused multiply-add to the extension layer
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
86cb785e58
fix(asm): read the MOV family registers against their banks
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:40:32 +02:00
petrbalvin
d18195f581
test(asm): pin the riscv64 error parity against the toolchain catalogues
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:40:32 +02:00
petrbalvin
f0942ff7f3
fix(asm): reject the operand shapes the toolchain rejects on riscv64
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:40:32 +02:00
petrbalvin
6c66f5bbd9
test(asm): encode the new FP16 families through the registry
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Assisted-by: GLM 5.3 Flash
2026-10-07 19:00:44 +02:00
petrbalvin
509afbb6c9
feat(arch): add the FP16 complex multiply and minimum-maximum to the extension layer
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Assisted-by: GLM 5.3 Flash
2026-10-07 18:59:09 +02:00
petrbalvin
8080e0acef
feat(arch): add the AVX512-FP16 FMA families to the extension layer
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Assisted-by: GLM 5.3 Flash
2026-10-07 18:58:49 +02:00
petrbalvin
acd30088af
fix(asm): reject the operand-starved riscv64 spellings instead of panicking
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Assisted-by: GLM 5.3
2026-10-07 13:53:37 +02:00
petrbalvin
d03de62c07
feat(arch): add the amd64 fp16 packed imm8-control group
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Assisted-by: GLM 5.3
2026-10-07 13:51:48 +02:00
petrbalvin
8de1b371da
feat(arch): add the amd64 fp16 packed conversion family
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Assisted-by: GLM 5.3
2026-10-07 13:51:48 +02:00
petrbalvin
fb6d01a7d0
feat(arch): encode the amd64 embedded rounding and SAE decorations
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Assisted-by: GLM 5.3
2026-10-07 13:51:48 +02:00
petrbalvin
104bea036b
feat(asm): encode the arm64 SVE gather loads and scatter stores
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Assisted-by: GLM 5.3
2026-10-07 13:51:10 +02:00
petrbalvin
6faf850793
feat(asm): encode the arm64 SVE2 crypto, counter and reduction families
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Assisted-by: GLM 5.3
2026-10-07 13:51:10 +02:00
petrbalvin
dac0a5b51b
docs(asm): state the seed layout of the arch fuzz targets exactly
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
965b33e5b0
test(asm): seed the riscv64 and loong64 assemble fuzz targets
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
b9dfb48d79
fix(asm): encode the loong64 64-bit-span 2RI14 offsets like the toolchain
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
41aa8edfd2
fix(asm): match the toolchain's loong64 logical immediate expansion
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
8fdc511d0d
test(asm): add the loong64 error-parity catalogue
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
e5035d92e9
fix(asm): reject the offset on the loong64 register-indexed memory form
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
b54547c08d
fix(asm): reject the shifted-register compositions on loong64
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
e9510e8a68
test(asm): pin the riscv64 tail against the toolchain byte for byte
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
9d50212a71
fix(asm): refuse the riscv64 width moves across register banks
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
f2892e4f59
feat(asm): emit the riscv64 local-exec TLS sequence
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
f8dbd4f017
fix(asm): lower the riscv64 immediate CSR pseudos onto their opcode forms
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
e5aabf9801
fix(asm): encode the riscv64 FENCE predecessor and successor flags
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
36d1ac804a
fix(asm): route the riscv64 register moves through the toolchain forms
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
da35883633
fix(asm): compress the riscv64 two-operand arithmetic and immediate tail
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Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin
8bded3ea39
test(asm): pin the byte-form width reconciliation and its oracle
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Table-driven rows for the renderer's spellings (the L suffix or none with
a byte register encodes the byte form, every register joining at its low
byte), the refusals (W, Q and the MOVD alias take no byte register) and a
differential kernel of the B-suffixed spellings assembled through both
gasm and go tool asm, byte for byte.
Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin
98a562d8b3
fix(asm): settle the byte-form width from the register operands
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The suffixed scalar families derived the operand width from the mnemonic
alone, so a byte-spelled register under the L spelling or no suffix at all
encoded the widened form: XADDL DL, DL emitted 0F C1 where the byte form is
0F C0, CMPL AL, $7 emitted the 32-bit immediate form where the AL form is
3C 07, and CRC32 DL, R11 widened past the F0 byte opcode. operandWidth now
reconciles the suffix with the operands: a byte register (AL, DL, R8B, ...)
forces the 8-bit form, which is the text the toolchain's own disassembly
prints for those encodings, while the W and Q spellings never ride a byte
register and are refused as go tool asm refuses them (MOVQ AL, AX). The
shift count and the two- and three-operand IMUL forms stay out of the
reconciliation, and the byte accumulator short forms now belong to the AL
spelling alone, matching the toolchain's division (ADDB $3, AX is
80 c0 03, TESTB $7, AX is f6 c0 07).
Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin
33e7fdac98
fix(asm): enforce the arm64 TLBI, RPRFM, FCVT and integer-pair arities
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Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin
7a69be8b59
fix(asm): reject the arm64 REGTMP spellings the toolchain refuses
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Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin
2385bb7069
fix(asm): enforce the arm64 VLD/VST post-index contract
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Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin
7bc80ccb54
fix(asm): emit nothing for the arm64 NOP pseudo-instruction
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Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin
405e2427ed
fix(asm): place the arm64 literal pool the way the toolchain flushes it
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Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin
4fc96decc4
fix(asm): size the arm64 logical-immediate materialisation exactly
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Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin
409c8b348d
fix(asm): bound the arm64 VTBL table list before the destination read
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
2b2a72d54e
fix(asm): encode the arm64 bitfield aliases with their own opc
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
8ab99c9b0c
fix(asm): tighten the arm64 acceptance toward the toolchain
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
82d741514a
fix(asm): key the arm64 immediate class order on the ZR spelling
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
f20aa156d0
fix(asm): treat the arm64 $-8 frame as frameless and encode the RET forms
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
d853432dba
fix(asm): route the arm64 logical immediates to ZR through REGTMP
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
fbdad8424f
feat(asm): encode the arm64 FP immediate moves
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
a9b54b6868
fix(asm): carry the arm64 immediate to ZR through MOVZ
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
d786b90fa1
feat(asm): lower the arm64 con(register) form to the ADD chain
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
9ef14bdb71
feat(asm): encode the arm64 SIMD arrangement bits
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin
458cdd2066
feat(asm): encode the arm64 register-offset addressing forms
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Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin