petrbalvin
cea5db6964
feat(parser): evaluate the TEXT and GLOBL flags operand as one expression
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:50:20 +02:00
petrbalvin
4eb9100def
test(asm): walk the loong64 audit backlog under every operand shape
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:42:14 +02:00
petrbalvin
43494a30f0
test(disasm): pin the toolchain's own ADDU16I.D rendering
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:42:14 +02:00
petrbalvin
f661c2fc78
test(asm): pin the ADDV16 immediate family the toolchain assembles
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:42:14 +02:00
petrbalvin
a3eaa82f87
feat(asm): take the loong64 register-pair spellings the toolchain parses
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:42:14 +02:00
petrbalvin
1031cd9ae7
feat(arch): the same-size shift-immediate family
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:39:45 +02:00
petrbalvin
eda8b16c5f
feat(arch): the shift-immediate tsz:imm3 scheme
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:39:45 +02:00
petrbalvin
718181e7a7
feat(arch): the FP8-to-halfword conversion pairs
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:39:45 +02:00
petrbalvin
107ca512b2
feat(arch): the ZCNOT unary pair and the vector counter step
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:39:45 +02:00
petrbalvin
4066396226
feat(asm): encode the GETCALLERPC, REM, DWORD and half-FCVT shapes
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:34:30 +02:00
petrbalvin
df7a5091e0
test(asm): pair the same-named GOROOT functions in definition order
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:34:30 +02:00
petrbalvin
c27ba30862
feat(asm): encode the arm64 local-exec TLS load
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:34:30 +02:00
petrbalvin
5f6be4584d
fix(asm): encode the flag-setting logicals to ZR and fold immediate expressions
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:34:30 +02:00
petrbalvin
c1cef7b6e8
feat(asm): materialise frame-relative addresses the way the toolchain does
...
Assisted-by: GLM 5.3 Flash
2026-10-07 21:34:30 +02:00
petrbalvin
1120a52a54
test(asm): sweep every registered amd64 extension mnemonic from .s text
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:56:25 +02:00
petrbalvin
fa50521619
feat(lint): surface the amd64 extension layer's refusals
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:56:25 +02:00
petrbalvin
5ee60c860b
fix(cmd/gasm): probe the arm64 operand shapes the encoder accepts
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:39:44 +02:00
petrbalvin
76f8ba6403
feat(asm): give riscv64 the END and GETCALLERPC the toolchain accepts
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:39:44 +02:00
petrbalvin
0211d6672d
feat(asm): expand riscv64 memory offsets beyond the 12-bit immediate
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:39:44 +02:00
petrbalvin
7aba29ac67
test(arch): pin the golden vectors of the last four families
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:42 +02:00
petrbalvin
aeb109a64c
feat(arch): the vector-length arithmetic pseudo group
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
bd85f8838d
feat(arch): the SVE2.1 last-active vector and compare families
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
12a5cfff52
feat(arch): the rest of the SVE2 BFloat16 wall
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
cdc3a75c88
feat(arch): the SVE multiple-structure loads and stores
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
82dbf087a8
feat(arch): the SVE2 BFloat16 arithmetic core
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
0760cc91af
feat(arch): the SVE2 three-source and bitwise combine families
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
bd80499c74
feat(arch): the SVE2 shift-by-vector family
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
b93fccc075
feat(arch): the SVE2.1 pairwise and quadword-reduction families
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
31ab584eee
feat(arch): the SVE2.1 narrowing two-to-one family
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
ee2c6d51b3
fix(arch): keep Zdn out of the class bits of the predicated Z-alias source
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:35:41 +02:00
petrbalvin
6e49cbd099
feat(asm): assemble the extended instruction layer on amd64
...
Assisted-by: GLM 5.3 Flash
2026-10-07 20:24:51 +02:00
petrbalvin
d4878524e8
test(asm): pin the clean GOROOT arm64 set against the toolchain
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:54:22 +02:00
petrbalvin
07f4622ffe
style(asm): range over the kernel generator's statement count
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:54:22 +02:00
petrbalvin
b3ede5f952
test(asm): pin the mid-function pool flush against the toolchain
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:54:22 +02:00
petrbalvin
5a5936d222
feat(asm): drain the arm64 literal pool mid-function at the distance bound
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:54:22 +02:00
petrbalvin
4632ac1bb9
feat(arch): add the AVX-VNNI-INT16 dot products to the extension layer
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
96000dd64d
feat(arch): add the VEX encoder to the extension layer
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
47d561b229
refactor(arch): extract the displacement tail and SIB builders
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
27ef71859b
feat(arch): add VMINMAXSH to the extension layer
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
03f9ef0ac6
feat(arch): add the FP16 complex fused multiply-add to the extension layer
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:49:15 +02:00
petrbalvin
86cb785e58
fix(asm): read the MOV family registers against their banks
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:40:32 +02:00
petrbalvin
4ff47fe17a
fix(cmd/gasm): probe the riscv64 operand shapes the encoder accepts
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:40:32 +02:00
petrbalvin
d18195f581
test(asm): pin the riscv64 error parity against the toolchain catalogues
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:40:32 +02:00
petrbalvin
f0942ff7f3
fix(asm): reject the operand shapes the toolchain rejects on riscv64
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:40:32 +02:00
petrbalvin
6c66f5bbd9
test(asm): encode the new FP16 families through the registry
...
Assisted-by: GLM 5.3 Flash
2026-10-07 19:00:44 +02:00
petrbalvin
509afbb6c9
feat(arch): add the FP16 complex multiply and minimum-maximum to the extension layer
...
Assisted-by: GLM 5.3 Flash
2026-10-07 18:59:09 +02:00
petrbalvin
8080e0acef
feat(arch): add the AVX512-FP16 FMA families to the extension layer
...
Assisted-by: GLM 5.3 Flash
2026-10-07 18:58:49 +02:00
petrbalvin
87493d9391
build(justfile): anchor the fuzz recipe to one exact target
...
Test / test (push) Successful in 1m2s
Assisted-by: GLM 5.3
2026-10-07 15:00:28 +02:00
petrbalvin
63ed141522
fix(parser): reject macro parameter lists the toolchain rejects
...
The C variadic spellings ("..." and the GNU "name..."), an empty or
trailing parameter, a missing comma, a stray token and an unterminated
list all parsed silently before: non-identifier tokens were skipped, so
"#define M(...)" defined a zero-parameter macro and invocations were
diagnosed only by argument count, if at all. The toolchain rejects the
definition itself ("bad definition for macro"), and so does the
preprocessor now: the parameter list must be identifiers separated by
single commas and closed by the parenthesis, and a rejected definition
leaves the name unbound. The spellings join the fuzz corpus.
Assisted-by: GLM 5.3
2026-10-07 14:04:15 +02:00
petrbalvin
373ec51061
fix(format): treat a selector-folded label as naming its macro
...
The lexer folds NAME.selector into one identifier, and an object macro
reached through the selector expands with it travelling along, so a
label spelled NAME.selector: restructures exactly like the bare name
would. The macro-name checks now resolve the prefix before the first
period, and the crashing input joins the corpus.
Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin